DE3585810D1 - Hochverdichtete speicher mit einzelelementspeicherzellen. - Google Patents

Hochverdichtete speicher mit einzelelementspeicherzellen.

Info

Publication number
DE3585810D1
DE3585810D1 DE8585106319T DE3585810T DE3585810D1 DE 3585810 D1 DE3585810 D1 DE 3585810D1 DE 8585106319 T DE8585106319 T DE 8585106319T DE 3585810 T DE3585810 T DE 3585810T DE 3585810 D1 DE3585810 D1 DE 3585810D1
Authority
DE
Germany
Prior art keywords
highly compressed
memory
memory cells
cells
compressed memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8585106319T
Other languages
English (en)
Inventor
Roy Edwin Scheuerlein
Russell Charles Lange
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3585810D1 publication Critical patent/DE3585810D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/911—Light sensitive array adapted to be scanned by electron beam, e.g. vidicon device

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
DE8585106319T 1984-06-28 1985-05-23 Hochverdichtete speicher mit einzelelementspeicherzellen. Expired - Fee Related DE3585810D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/625,403 US4651183A (en) 1984-06-28 1984-06-28 High density one device memory cell arrays

Publications (1)

Publication Number Publication Date
DE3585810D1 true DE3585810D1 (de) 1992-05-14

Family

ID=24505917

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585106319T Expired - Fee Related DE3585810D1 (de) 1984-06-28 1985-05-23 Hochverdichtete speicher mit einzelelementspeicherzellen.

Country Status (4)

Country Link
US (1) US4651183A (de)
EP (1) EP0169332B1 (de)
JP (1) JPS6114747A (de)
DE (1) DE3585810D1 (de)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1305255C (en) * 1986-08-25 1992-07-14 Joseph Lebowitz Marching interconnecting lines in semiconductor integrated circuits
JPH0787219B2 (ja) * 1986-09-09 1995-09-20 三菱電機株式会社 半導体記憶装置
JPH0783053B2 (ja) * 1987-06-19 1995-09-06 三菱電機株式会社 半導体装置
JPH0815208B2 (ja) * 1987-07-01 1996-02-14 三菱電機株式会社 半導体記憶装置
DE3807162A1 (de) * 1987-07-02 1989-01-12 Mitsubishi Electric Corp Halbleiterspeichereinrichtung
KR910009805B1 (ko) * 1987-11-25 1991-11-30 후지쓰 가부시끼가이샤 다이나믹 랜덤 액세스 메모리 장치와 그의 제조방법
US20010008288A1 (en) * 1988-01-08 2001-07-19 Hitachi, Ltd. Semiconductor integrated circuit device having memory cells
US5140389A (en) * 1988-01-08 1992-08-18 Hitachi, Ltd. Semiconductor memory device having stacked capacitor cells
US5374576A (en) * 1988-12-21 1994-12-20 Hitachi, Ltd. Method of fabricating stacked capacitor cell memory devices
JP2590171B2 (ja) * 1988-01-08 1997-03-12 株式会社日立製作所 半導体記憶装置
JP2681285B2 (ja) * 1988-09-19 1997-11-26 富士通株式会社 半導体記憶装置
JPH02198154A (ja) * 1989-01-27 1990-08-06 Hitachi Ltd 配線の形成方法及びこれを利用した半導体装置
US5210596A (en) * 1989-06-30 1993-05-11 Texas Instruments Incorporated Thermally optimized interdigitated transistor
US5057882A (en) * 1989-06-30 1991-10-15 Texas Instruments Incorporated Thermally optimized interdigitated transistor
JP2974252B2 (ja) * 1989-08-19 1999-11-10 富士通株式会社 半導体記憶装置
JP2508288B2 (ja) * 1989-08-30 1996-06-19 三菱電機株式会社 半導体記憶装置
EP0449422B1 (de) * 1990-02-26 1997-06-18 Nec Corporation Halbleiterspeicheranordnung
JPH03278573A (ja) * 1990-03-28 1991-12-10 Mitsubishi Electric Corp 半導体記憶装置
JP2792211B2 (ja) * 1990-07-06 1998-09-03 日本電気株式会社 半導体記憶装置
US5770874A (en) * 1994-11-14 1998-06-23 Nippon Steel Corporation High density semiconductor memory device
KR970051170A (ko) * 1995-12-29 1997-07-29 김주용 메모리 셀 어레이 및 그를 이용한 프로그램 방법
KR100239404B1 (ko) * 1996-07-31 2000-01-15 김영환 디램(dram) 및 그의 셀 어레이방법
US5875138A (en) * 1997-06-30 1999-02-23 Siemens Aktiengesellschaft Dynamic access memory equalizer circuits and methods therefor
JP2000228509A (ja) * 1999-02-05 2000-08-15 Fujitsu Ltd 半導体装置
JP2002270788A (ja) * 2001-03-14 2002-09-20 Fujitsu Ltd 半導体装置及びその製造方法
CA2340985A1 (en) * 2001-03-14 2002-09-14 Atmos Corporation Interleaved wordline architecture
US7501676B2 (en) * 2005-03-25 2009-03-10 Micron Technology, Inc. High density semiconductor memory
US7462903B1 (en) * 2005-09-14 2008-12-09 Spansion Llc Methods for fabricating semiconductor devices and contacts to semiconductor devices
US7495294B2 (en) * 2005-12-21 2009-02-24 Sandisk Corporation Flash devices with shared word lines
US7655536B2 (en) * 2005-12-21 2010-02-02 Sandisk Corporation Methods of forming flash devices with shared word lines
WO2007081642A2 (en) * 2005-12-21 2007-07-19 Sandisk Corporation Flash devicewith shared word lines and manufacturing methods thereof
KR20110015803A (ko) * 2009-08-10 2011-02-17 삼성전자주식회사 반도체 메모리 소자
US9401363B2 (en) * 2011-08-23 2016-07-26 Micron Technology, Inc. Vertical transistor devices, memory arrays, and methods of forming vertical transistor devices
US9589962B2 (en) 2014-06-17 2017-03-07 Micron Technology, Inc. Array of conductive vias, methods of forming a memory array, and methods of forming conductive vias
GB2572148B (en) * 2018-03-19 2020-09-16 X-Fab Semiconductor Foundries Gmbh Programmable read-only memory device
CN116113237A (zh) * 2020-08-18 2023-05-12 长鑫存储技术有限公司 存储器及其制作方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4012757A (en) * 1975-05-05 1977-03-15 Intel Corporation Contactless random-access memory cell and cell pair
JPS6041463B2 (ja) * 1976-11-19 1985-09-17 株式会社日立製作所 ダイナミツク記憶装置
US4125854A (en) * 1976-12-02 1978-11-14 Mostek Corporation Symmetrical cell layout for static RAM
DE2740113A1 (de) * 1977-09-06 1979-03-15 Siemens Ag Monolithisch integrierter halbleiterspeicher
US4240195A (en) * 1978-09-15 1980-12-23 Bell Telephone Laboratories, Incorporated Dynamic random access memory
JPS5541754A (en) * 1978-09-20 1980-03-24 Fujitsu Ltd Semiconductor memory
DE2909820A1 (de) * 1979-03-13 1980-09-18 Siemens Ag Halbleiterspeicher mit eintransistorzellen in v-mos-technologie
US4482908A (en) * 1979-07-30 1984-11-13 Burroughs Corporation High capacity memory cell having a charge transfer channel covered by a stepped insulating layer
US4287571A (en) * 1979-09-11 1981-09-01 International Business Machines Corporation High density transistor arrays
US4376983A (en) * 1980-03-21 1983-03-15 Texas Instruments Incorporated High density dynamic memory cell
US4388121A (en) * 1980-03-21 1983-06-14 Texas Instruments Incorporated Reduced field implant for dynamic memory cell array
JPS57111061A (en) * 1980-12-26 1982-07-10 Fujitsu Ltd Semiconductor memory unit
JPS5922358A (ja) * 1982-07-28 1984-02-04 Toshiba Corp 半導体記憶装置

Also Published As

Publication number Publication date
US4651183A (en) 1987-03-17
EP0169332A2 (de) 1986-01-29
JPS6114747A (ja) 1986-01-22
EP0169332A3 (en) 1989-09-06
EP0169332B1 (de) 1992-04-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee