DE3584113D1 - Verfahren zum herstellen selbstjustierter bereiche in einem substrat. - Google Patents

Verfahren zum herstellen selbstjustierter bereiche in einem substrat.

Info

Publication number
DE3584113D1
DE3584113D1 DE8585107216T DE3584113T DE3584113D1 DE 3584113 D1 DE3584113 D1 DE 3584113D1 DE 8585107216 T DE8585107216 T DE 8585107216T DE 3584113 T DE3584113 T DE 3584113T DE 3584113 D1 DE3584113 D1 DE 3584113D1
Authority
DE
Germany
Prior art keywords
substrate
producing self
adjusted areas
areas
adjusted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8585107216T
Other languages
English (en)
Inventor
John T Gasner
Frederick N Hause
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Harris Corp
Original Assignee
Harris Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US06/620,835 external-priority patent/US4599789A/en
Priority claimed from US06/643,362 external-priority patent/US4578859A/en
Application filed by Harris Corp filed Critical Harris Corp
Application granted granted Critical
Publication of DE3584113D1 publication Critical patent/DE3584113D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE8585107216T 1984-06-15 1985-06-12 Verfahren zum herstellen selbstjustierter bereiche in einem substrat. Expired - Lifetime DE3584113D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/620,835 US4599789A (en) 1984-06-15 1984-06-15 Process of making twin well VLSI CMOS
US06/643,362 US4578859A (en) 1984-08-22 1984-08-22 Implant mask reversal process

Publications (1)

Publication Number Publication Date
DE3584113D1 true DE3584113D1 (de) 1991-10-24

Family

ID=27088796

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585107216T Expired - Lifetime DE3584113D1 (de) 1984-06-15 1985-06-12 Verfahren zum herstellen selbstjustierter bereiche in einem substrat.

Country Status (3)

Country Link
EP (1) EP0164737B1 (de)
JP (1) JPH0669079B2 (de)
DE (1) DE3584113D1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4767721A (en) * 1986-02-10 1988-08-30 Hughes Aircraft Company Double layer photoresist process for well self-align and ion implantation masking
FR2610141B1 (fr) * 1987-01-26 1990-01-19 Commissariat Energie Atomique Circuit integre cmos et procede de fabrication de zones d'isolation electrique dans ce circuit
JPS63196070A (ja) * 1987-02-10 1988-08-15 Sony Corp Cmosの製造方法
IT1225614B (it) * 1988-08-04 1990-11-22 Sgs Thomson Microelectronics Processo per la fabbricazione di dispositivi integrati cmos con lunghezze di gate ridotte e drain leggermente drogato
JPH088307B2 (ja) * 1988-12-20 1996-01-29 株式会社東芝 半導体装置の製造方法
US4895520A (en) * 1989-02-02 1990-01-23 Standard Microsystems Corporation Method of fabricating a submicron silicon gate MOSFETg21 which has a self-aligned threshold implant
JP2007251194A (ja) * 2007-05-14 2007-09-27 Toshiba Corp 半導体装置およびその製造方法
CN104810253B (zh) * 2014-01-28 2018-02-16 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3175081D1 (en) * 1980-12-12 1986-09-11 Toshiba Kk Method of manufacturing a semiconductor device of the mis type
US4411058A (en) * 1981-08-31 1983-10-25 Hughes Aircraft Company Process for fabricating CMOS devices with self-aligned channel stops
US4435896A (en) * 1981-12-07 1984-03-13 Bell Telephone Laboratories, Incorporated Method for fabricating complementary field effect transistor devices

Also Published As

Publication number Publication date
JPS6158265A (ja) 1986-03-25
EP0164737B1 (de) 1991-09-18
JPH0669079B2 (ja) 1994-08-31
EP0164737A2 (de) 1985-12-18
EP0164737A3 (en) 1987-05-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Free format text: PATENTANWAELTE RUFF, WILHELM, BEIER, DAUSTER & PARTNER, 70173 STUTTGART