DE3483851D1 - Verfahren zur herstellung eines schottky-gate-feldeffekttransistors. - Google Patents

Verfahren zur herstellung eines schottky-gate-feldeffekttransistors.

Info

Publication number
DE3483851D1
DE3483851D1 DE8484303864T DE3483851T DE3483851D1 DE 3483851 D1 DE3483851 D1 DE 3483851D1 DE 8484303864 T DE8484303864 T DE 8484303864T DE 3483851 T DE3483851 T DE 3483851T DE 3483851 D1 DE3483851 D1 DE 3483851D1
Authority
DE
Germany
Prior art keywords
producing
field effect
effect transistor
gate field
schottky gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8484303864T
Other languages
English (en)
Inventor
Toshiyuki C O Patent Di Terada
Nobuyuki C O Patent Div Toyoda
Akimichi C O Patent Divis Hojo
Kiyoho C O Patent Divisi Kamei
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3483851D1 publication Critical patent/DE3483851D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66848Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
    • H01L29/66856Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
    • H01L29/66863Lateral single gate transistors
    • H01L29/66871Processes wherein the final gate is made after the formation of the source and drain regions in the active layer, e.g. dummy-gate processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47Schottky barrier electrodes
    • H01L29/475Schottky barrier electrodes on AIII-BV compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/80Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/80Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Drying Of Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)
DE8484303864T 1983-06-13 1984-06-07 Verfahren zur herstellung eines schottky-gate-feldeffekttransistors. Expired - Lifetime DE3483851D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58105306A JPS59229876A (ja) 1983-06-13 1983-06-13 シヨツトキ−ゲ−ト型電界効果トランジスタの製造方法

Publications (1)

Publication Number Publication Date
DE3483851D1 true DE3483851D1 (de) 1991-02-07

Family

ID=14404016

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484303864T Expired - Lifetime DE3483851D1 (de) 1983-06-13 1984-06-07 Verfahren zur herstellung eines schottky-gate-feldeffekttransistors.

Country Status (4)

Country Link
US (1) US4569119A (de)
EP (1) EP0128751B1 (de)
JP (1) JPS59229876A (de)
DE (1) DE3483851D1 (de)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0793318B2 (ja) * 1984-10-11 1995-10-09 日本電気株式会社 半導体装置の製造方法
JPH0793319B2 (ja) * 1984-10-16 1995-10-09 松下電子工業株式会社 電界効果トランジスタの製造方法
US4632713A (en) * 1985-07-31 1986-12-30 Texas Instruments Incorporated Process of making Schottky barrier devices formed by diffusion before contacting
EP0224614B1 (de) * 1985-12-06 1990-03-14 International Business Machines Corporation Verfahren zum Herstellen eines völlig selbstjustierten Feldeffekttransistors
US4745082A (en) * 1986-06-12 1988-05-17 Ford Microelectronics, Inc. Method of making a self-aligned MESFET using a substitutional gate with side walls
JPS6362272A (ja) * 1986-09-02 1988-03-18 Seiko Instr & Electronics Ltd 半導体装置の製造方法
US4859618A (en) * 1986-11-20 1989-08-22 Sumitomo Electric Industries, Ltd. Method of producing the gate electrode of a field effect transistor
JPS63132452A (ja) * 1986-11-24 1988-06-04 Mitsubishi Electric Corp パタ−ン形成方法
WO1989001235A1 (en) * 1987-08-03 1989-02-09 Ford Microelectronics, Inc. High effective barrier height transistor and method of making same
US4843037A (en) * 1987-08-21 1989-06-27 Bell Communications Research, Inc. Passivation of indium gallium arsenide surfaces
US5229323A (en) * 1987-08-21 1993-07-20 Kabushiki Kaisha Toshiba Method for manufacturing a semiconductor device with Schottky electrodes
JPS6455871A (en) * 1987-08-26 1989-03-02 Sumitomo Electric Industries Manufacture of self-alignment type gate electrode
JPH0787195B2 (ja) * 1987-10-22 1995-09-20 三菱電機株式会社 ショットキゲート電界効果トランジスタの製造方法
JPH01114041A (ja) * 1987-10-27 1989-05-02 Nec Corp 微細パタン形成方法
US4863879A (en) * 1987-12-16 1989-09-05 Ford Microelectronics, Inc. Method of manufacturing self-aligned GaAs MESFET
JPH0748502B2 (ja) * 1988-05-13 1995-05-24 三菱電機株式会社 半導体装置の製造方法
US4947062A (en) * 1988-05-19 1990-08-07 Adams Russell Electronics Co., Inc. Double balanced mixing
DE3911512A1 (de) * 1988-09-07 1990-03-22 Licentia Gmbh Selbstjustierendes verfahren zur herstellung einer steuerelektrode
US5143857A (en) * 1988-11-07 1992-09-01 Triquint Semiconductor, Inc. Method of fabricating an electronic device with reduced susceptiblity to backgating effects
JP2550412B2 (ja) * 1989-05-15 1996-11-06 ローム株式会社 電界効果トランジスタの製造方法
JPH0817184B2 (ja) * 1989-11-08 1996-02-21 三菱電機株式会社 化合物半導体装置の製造方法
DE59009067D1 (de) * 1990-04-27 1995-06-14 Siemens Ag Verfahren zur Herstellung einer Öffnung in einem Halbleiterschichtaufbau und dessen Verwendung zur Herstellung von Kontaktlöchern.
US6406950B1 (en) * 2000-12-07 2002-06-18 Advanced Micro Devices, Inc. Definition of small damascene metal gates using reverse through approach
JP3959032B2 (ja) * 2003-01-08 2007-08-15 松下電器産業株式会社 固体撮像装置の製造方法
KR100871967B1 (ko) * 2007-06-05 2008-12-08 주식회사 하이닉스반도체 반도체 소자의 미세 패턴 형성 방법
US8950215B2 (en) * 2010-10-06 2015-02-10 Apple Inc. Non-contact polishing techniques for reducing roughness on glass surfaces

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4481704A (en) * 1978-04-21 1984-11-13 Texas Instruments Incorporated Method of making an improved MESFET semiconductor device
JPS55153377A (en) * 1979-05-18 1980-11-29 Matsushita Electronics Corp Production of semiconductor device
JPS57152168A (en) * 1981-03-13 1982-09-20 Nec Corp Manufacture of schottky barrier gate field effect transistor
US4344980A (en) * 1981-03-25 1982-08-17 The United States Of America As Represented By The Secretary Of The Navy Superior ohmic contacts to III-V semiconductor by virtue of double donor impurity
JPS57196581A (en) * 1981-05-27 1982-12-02 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JPS5896769A (ja) * 1981-12-04 1983-06-08 Oki Electric Ind Co Ltd 半導体素子の製造方法
US4403396A (en) * 1981-12-24 1983-09-13 Gte Laboratories Incorporated Semiconductor device design and process
US4561169A (en) * 1982-07-30 1985-12-31 Hitachi, Ltd. Method of manufacturing semiconductor device utilizing multilayer mask
JPS59114871A (ja) * 1982-12-21 1984-07-03 Toshiba Corp シヨツトキ−ゲ−ト型GaAs電界効果トランジスタの製造方法

Also Published As

Publication number Publication date
EP0128751A2 (de) 1984-12-19
JPS59229876A (ja) 1984-12-24
JPH0212019B2 (de) 1990-03-16
EP0128751B1 (de) 1990-12-27
US4569119A (en) 1986-02-11
EP0128751A3 (en) 1986-11-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee