DE3884924D1 - Verfahren zur Herstellung eines MIS-Transistors mit an den Endpunkten erhöhter dielektrischer Gate/Substrat-Grenzfläche. - Google Patents
Verfahren zur Herstellung eines MIS-Transistors mit an den Endpunkten erhöhter dielektrischer Gate/Substrat-Grenzfläche.Info
- Publication number
- DE3884924D1 DE3884924D1 DE88403196T DE3884924T DE3884924D1 DE 3884924 D1 DE3884924 D1 DE 3884924D1 DE 88403196 T DE88403196 T DE 88403196T DE 3884924 T DE3884924 T DE 3884924T DE 3884924 D1 DE3884924 D1 DE 3884924D1
- Authority
- DE
- Germany
- Prior art keywords
- elevated
- producing
- end points
- mis transistor
- substrate interface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000000758 substrate Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR8717725A FR2625044B1 (fr) | 1987-12-18 | 1987-12-18 | Transistor mos a extremite d'interface dielectrique de grille/substrat relevee et procede de fabrication de ce transistor |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3884924D1 true DE3884924D1 (de) | 1993-11-18 |
DE3884924T2 DE3884924T2 (de) | 1994-05-05 |
Family
ID=9358042
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE88403196T Expired - Fee Related DE3884924T2 (de) | 1987-12-18 | 1988-12-15 | Verfahren zur Herstellung eines MIS-Transistors mit an den Endpunkten erhöhter dielektrischer Gate/Substrat-Grenzfläche. |
Country Status (5)
Country | Link |
---|---|
US (1) | US4939100A (de) |
EP (1) | EP0321347B1 (de) |
JP (1) | JPH022172A (de) |
DE (1) | DE3884924T2 (de) |
FR (1) | FR2625044B1 (de) |
Families Citing this family (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5082794A (en) * | 1989-02-13 | 1992-01-21 | Motorola, Inc. | Method of fabricating mos transistors using selective polysilicon deposition |
US5296401A (en) * | 1990-01-11 | 1994-03-22 | Mitsubishi Denki Kabushiki Kaisha | MIS device having p channel MOS device and n channel MOS device with LDD structure and manufacturing method thereof |
US5279990A (en) * | 1990-03-02 | 1994-01-18 | Motorola, Inc. | Method of making a small geometry contact using sidewall spacers |
US5108937A (en) * | 1991-02-01 | 1992-04-28 | Taiwan Semiconductor Manufacturing Company | Method of making a recessed gate MOSFET device structure |
KR920022553A (ko) * | 1991-05-15 | 1992-12-19 | 문정환 | Ldd 소자의 구조 및 제조방법 |
KR940002400B1 (ko) * | 1991-05-15 | 1994-03-24 | 금성일렉트론 주식회사 | 리세스 게이트를 갖는 반도체장치의 제조방법 |
US5342796A (en) * | 1991-05-28 | 1994-08-30 | Sharp Kabushiki Kaisha | Method for controlling gate size for semiconduction process |
EP0654829A1 (de) * | 1993-11-12 | 1995-05-24 | STMicroelectronics, Inc. | MOS-gesteuerte doppelt-diffundierte Halbleiteranordnungen mit erhöhter Dichte |
US5620911A (en) * | 1993-12-31 | 1997-04-15 | Hyundai Electronics Industries Co., Ltd. | Method for fabricating a metal field effect transistor having a recessed gate |
US5814544A (en) * | 1994-07-14 | 1998-09-29 | Vlsi Technology, Inc. | Forming a MOS transistor with a recessed channel |
US5798291A (en) * | 1995-03-20 | 1998-08-25 | Lg Semicon Co., Ltd. | Method of making a semiconductor device with recessed source and drain |
US5756391A (en) * | 1995-03-24 | 1998-05-26 | Kabushiki Kaisha Toshiba | Anti-oxidation layer formation by carbon incorporation |
US5545579A (en) * | 1995-04-04 | 1996-08-13 | Taiwan Semiconductor Manufacturing Company | Method of fabricating a sub-quarter micrometer channel field effect transistor having elevated source/drain areas and lightly doped drains |
US5688700A (en) * | 1995-11-03 | 1997-11-18 | Micron Technology, Inc. | Method of forming a field effect transistor |
WO1998012741A1 (en) * | 1996-09-18 | 1998-03-26 | Advanced Micro Devices, Inc. | Short channel non-self aligned vmos field effect transistor |
TW347561B (en) * | 1997-06-20 | 1998-12-11 | Ti Acer Co Ltd | Method of forming a T-gate Lightly-Doped Drain semiconductor device |
JP3461277B2 (ja) * | 1998-01-23 | 2003-10-27 | 株式会社東芝 | 半導体装置及びその製造方法 |
US6465842B2 (en) | 1998-06-25 | 2002-10-15 | Kabushiki Kaisha Toshiba | MIS semiconductor device and method of fabricating the same |
US20010046744A1 (en) * | 1999-01-13 | 2001-11-29 | Brian S. Doyle | Transistor with reduced series resistance junction regions |
US6956263B1 (en) * | 1999-12-28 | 2005-10-18 | Intel Corporation | Field effect transistor structure with self-aligned raised source/drain extensions |
KR100505113B1 (ko) | 2003-04-23 | 2005-07-29 | 삼성전자주식회사 | 모스 트랜지스터 및 그 제조방법 |
US7282401B2 (en) | 2005-07-08 | 2007-10-16 | Micron Technology, Inc. | Method and apparatus for a self-aligned recessed access device (RAD) transistor gate |
US7867851B2 (en) | 2005-08-30 | 2011-01-11 | Micron Technology, Inc. | Methods of forming field effect transistors on substrates |
KR100660545B1 (ko) * | 2005-11-09 | 2006-12-22 | 삼성전자주식회사 | 무접촉성 비휘발성 메모리 장치의 형성 방법 및 그에 의해형성된 장치 |
US7700441B2 (en) | 2006-02-02 | 2010-04-20 | Micron Technology, Inc. | Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates |
US7456450B2 (en) * | 2006-02-09 | 2008-11-25 | International Business Machines Corporation | CMOS devices with hybrid channel orientations and method for fabricating the same |
US7602001B2 (en) | 2006-07-17 | 2009-10-13 | Micron Technology, Inc. | Capacitorless one transistor DRAM cell, integrated circuitry comprising an array of capacitorless one transistor DRAM cells, and method of forming lines of capacitorless one transistor DRAM cells |
US7772632B2 (en) | 2006-08-21 | 2010-08-10 | Micron Technology, Inc. | Memory arrays and methods of fabricating memory arrays |
US7589995B2 (en) | 2006-09-07 | 2009-09-15 | Micron Technology, Inc. | One-transistor memory cell with bias gate |
US7781278B2 (en) * | 2007-01-18 | 2010-08-24 | International Business Machines Corporation | CMOS devices having channel regions with a V-shaped trench and hybrid channel orientations, and method for forming the same |
CN101030602B (zh) * | 2007-04-06 | 2012-03-21 | 上海集成电路研发中心有限公司 | 一种可减小短沟道效应的mos晶体管及其制作方法 |
US7923373B2 (en) | 2007-06-04 | 2011-04-12 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
EP2981513B1 (de) * | 2013-04-03 | 2019-03-06 | Dinex A/S | Wabenstrukturanordnung |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54146584A (en) * | 1978-05-09 | 1979-11-15 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
JPS54154977A (en) * | 1978-05-29 | 1979-12-06 | Fujitsu Ltd | Semiconductor device and its manufacture |
US4272302A (en) * | 1979-09-05 | 1981-06-09 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | Method of making V-MOS field effect transistors utilizing a two-step anisotropic etching and ion implantation |
JPS5676571A (en) * | 1979-11-28 | 1981-06-24 | Sumitomo Electric Ind Ltd | Mos field effect transistor and manufacture thereof |
US4393391A (en) * | 1980-06-16 | 1983-07-12 | Supertex, Inc. | Power MOS transistor with a plurality of longitudinal grooves to increase channel conducting area |
JPH0682837B2 (ja) * | 1982-09-16 | 1994-10-19 | 財団法人半導体研究振興会 | 半導体集積回路 |
US4685196A (en) * | 1985-07-29 | 1987-08-11 | Industrial Technology Research Institute | Method for making planar FET having gate, source and drain in the same plane |
JPS6281727A (ja) * | 1985-10-05 | 1987-04-15 | Fujitsu Ltd | 埋込型素子分離溝の形成方法 |
DE3609274A1 (de) * | 1986-03-19 | 1987-09-24 | Siemens Ag | Verfahren zur herstellung eines selbstjustiert positionierten metallkontaktes |
-
1987
- 1987-12-18 FR FR8717725A patent/FR2625044B1/fr not_active Expired - Lifetime
-
1988
- 1988-12-12 JP JP63312128A patent/JPH022172A/ja active Pending
- 1988-12-15 DE DE88403196T patent/DE3884924T2/de not_active Expired - Fee Related
- 1988-12-15 US US07/284,540 patent/US4939100A/en not_active Expired - Fee Related
- 1988-12-15 EP EP88403196A patent/EP0321347B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US4939100A (en) | 1990-07-03 |
JPH022172A (ja) | 1990-01-08 |
FR2625044B1 (fr) | 1990-08-31 |
EP0321347B1 (de) | 1993-10-13 |
EP0321347A1 (de) | 1989-06-21 |
FR2625044A1 (fr) | 1989-06-23 |
DE3884924T2 (de) | 1994-05-05 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |