DE3482073D1 - Halbleiterspeicheranordnung. - Google Patents
Halbleiterspeicheranordnung.Info
- Publication number
- DE3482073D1 DE3482073D1 DE8484308327T DE3482073T DE3482073D1 DE 3482073 D1 DE3482073 D1 DE 3482073D1 DE 8484308327 T DE8484308327 T DE 8484308327T DE 3482073 T DE3482073 T DE 3482073T DE 3482073 D1 DE3482073 D1 DE 3482073D1
- Authority
- DE
- Germany
- Prior art keywords
- semiconductor memory
- memory arrangement
- arrangement
- semiconductor
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58227372A JPS60119698A (ja) | 1983-12-01 | 1983-12-01 | 半導体メモリ |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3482073D1 true DE3482073D1 (de) | 1990-05-31 |
Family
ID=16859768
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8484308327T Expired - Fee Related DE3482073D1 (de) | 1983-12-01 | 1984-11-30 | Halbleiterspeicheranordnung. |
Country Status (5)
Country | Link |
---|---|
US (1) | US4653027A (de) |
EP (1) | EP0144223B1 (de) |
JP (1) | JPS60119698A (de) |
KR (1) | KR910003596B1 (de) |
DE (1) | DE3482073D1 (de) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62165785A (ja) * | 1986-01-17 | 1987-07-22 | Mitsubishi Electric Corp | 半導体記憶装置 |
JPS63113892A (ja) * | 1986-10-30 | 1988-05-18 | Nec Corp | 出力回路 |
FR2607955B1 (fr) * | 1986-12-05 | 1989-02-10 | Eurotechnique Sa | Dispositif d'autosynchronisation des circuits de sortie d'une memoire |
JPH01140494A (ja) * | 1987-11-26 | 1989-06-01 | Mitsubishi Electric Corp | 半導体記憶装置の出力バッファ回路 |
JPH0752583B2 (ja) * | 1987-11-30 | 1995-06-05 | 株式会社東芝 | 半導体メモリ |
JPH0438793A (ja) | 1990-06-04 | 1992-02-07 | Toshiba Corp | データ転送制御回路およびこれを用いたダイナミック型半導体記憶装置 |
JPH04121893A (ja) * | 1990-09-12 | 1992-04-22 | Mitsubishi Electric Corp | 半導体記憶装置 |
KR930008311B1 (ko) * | 1990-12-28 | 1993-08-27 | 삼성전자 주식회사 | 센스 앰프의 출력 제어회로 |
KR940007639B1 (ko) * | 1991-07-23 | 1994-08-22 | 삼성전자 주식회사 | 분할된 입출력 라인을 갖는 데이타 전송회로 |
US9438234B2 (en) * | 2014-11-21 | 2016-09-06 | Semiconductor Energy Laboratory Co., Ltd. | Logic circuit and semiconductor device including logic circuit |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3969706A (en) * | 1974-10-08 | 1976-07-13 | Mostek Corporation | Dynamic random access memory misfet integrated circuit |
JPS5920193B2 (ja) * | 1977-08-17 | 1984-05-11 | 三菱電機株式会社 | スタテイックランダムアクセスメモリの出力バッファ回路 |
US4250412A (en) * | 1979-03-05 | 1981-02-10 | Motorola, Inc. | Dynamic output buffer |
JPS5625290A (en) * | 1979-08-07 | 1981-03-11 | Nec Corp | Semiconductor circuit |
JPS56101694A (en) * | 1980-01-18 | 1981-08-14 | Nec Corp | Semiconductor circuit |
EP0125699A3 (de) * | 1983-05-17 | 1986-10-08 | Kabushiki Kaisha Toshiba | Datenausgabeanordnung für einen dynamischen Speicher |
-
1983
- 1983-12-01 JP JP58227372A patent/JPS60119698A/ja active Granted
-
1984
- 1984-11-30 DE DE8484308327T patent/DE3482073D1/de not_active Expired - Fee Related
- 1984-11-30 EP EP84308327A patent/EP0144223B1/de not_active Expired - Lifetime
- 1984-12-01 KR KR8407596A patent/KR910003596B1/ko not_active IP Right Cessation
- 1984-12-03 US US06/677,580 patent/US4653027A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
KR850004685A (ko) | 1985-07-25 |
EP0144223A2 (de) | 1985-06-12 |
EP0144223B1 (de) | 1990-04-25 |
EP0144223A3 (en) | 1986-10-08 |
KR910003596B1 (en) | 1991-06-07 |
US4653027A (en) | 1987-03-24 |
JPS60119698A (ja) | 1985-06-27 |
JPH0378713B2 (de) | 1991-12-16 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |