CN86101621A - Improved signature analysis device for electronic circuits - Google Patents
Improved signature analysis device for electronic circuits Download PDFInfo
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- CN86101621A CN86101621A CN198686101621A CN86101621A CN86101621A CN 86101621 A CN86101621 A CN 86101621A CN 198686101621 A CN198686101621 A CN 198686101621A CN 86101621 A CN86101621 A CN 86101621A CN 86101621 A CN86101621 A CN 86101621A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
- G06F11/277—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault-free response
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Abstract
When the conflict of clock and data-signal causes unstable tense marker figure, circuit can be eliminated the instability of this marker graphic that obtains from digital electronic test system.Access delay device on data and/or clock signal channel, and the relative timing of change clock and data-signal are so that eliminate this two kinds of conflict situations that cause the signal hopping edge.For with marker graphic analysis of high frequency signal and guarantee that the marker graphic generator can measure short data-signal incident of duration, circuit can repeatedly receive data with special mode triggered mark pattern generator in each clock period in addition.The best available clock signal of square wave time clock is jumped up and down along the triggered mark pattern generator.
Description
The improvement of the signature analysis device that is used for this system is introduced or rather by the system that the present invention introduces test circuit.
The system of known test digital circuit comprises signature analysis device.This instrument generally uses feedback shift register, and this instrument converts detected digital signal on the node of tested parts (to call UUT in the following text) or bit stream to figure notation figure (digital signature).
Typical signature analysis device uses a state machine (state machine) of being realized by shift register, during clock interval each bit combination of its current data state of expression in each bit of supplied with digital signal or bit stream and the register is got up.More particularly this shift register is connected into suitable feedback formation, so that bit in its each unit and input bit combine by the binary arithmetic rule.The result just becomes the bit of digital signal and the combination of bit in advance that chooses, and on tested node, forms the marker graphic of UUT to the response of specific incoming bit stream.
Therefore, signature analysis device produces a word or the marker graphic that can accurately represent data flow characteristic.These marker graphics that on each test point of UUT or node, obtain, concerning test, can be by identification and qualitative.The marker graphic that comes from the operate as normal node is noted, so that then compare with the marker graphic of the signal that obtains from the UUT node.The marker graphic that records and the user who relatively makes system of marker graphic of record in advance can determine that UUT is whether working properly and can determine faulty circuit among the UUT or the position of node.
Typical signature analysis device is made of the marker graphic generator that contains feedback register, triggers feedback register during giving fixed clock interval, makes its receiving digital data.Yet in the prior art of signature analysis device was used, synchronizing clock signals frequency marker pattern generator generally can not be in response to short signal perdurability.More particularly, the signal generator of prior art is to receive data by the rising edge triggering of clock pulse signal.Perhaps good by the negative edge triggering of clock signal conversely.So the frequency that such marker graphic generator only changes in data signal levels is low reliable to being enough to be only under the situation that can detect under the clock frequency.Therefore, when the signal level variation frequency is higher, just can not detect reliably.
So, must the signature analysis device of prior art be improved, make it to detect the signal of upper frequency, more particularly, make it exactly when signal level variation is very fast, to detect, and can not spend a lot of money to remove to revise this test macro.
In addition, so because the reception of the test macro of prior art and analytical work are the clock edges at data signal edge and triggered mark pattern generator by clock control take place simultaneously or approximate simultaneous situation under just may obtain insecure data.
This two transition simultaneously or near the signal of transition simultaneously generally can lead to a conflict state and make output can not survey standard, depend on which signal is finished at first or measured at first on particular electrical circuit point.Consider the aging of components and parts, the variation of temperature and other environmental baseline, may under a kind of test condition, provide certain result having the marker graphic analytical work of carrying out under the conflict situation, and in the next opposite result of another kind that provides of another kind of test condition, and the performance of UUT is identical under same level.
So just more need to improve the signature analysis device of prior art, make its generation of avoiding the conflict situation between clock signal and the data-signal, so that obtain stable and reliable circuit test results.
Therefore, an object of the present invention is to provide a kind of electronic circuit test system of usage flag pattern analysis instrument to overcome the shortcoming of prior art.
Of the present invention one more specifically purpose provide a kind of signature analysis device, but its receiving and analyzing is higher than the input data signal of clock signal frequency.
Another object of the present invention provides a kind of signature analysis device, and it can receive and analyze the data-signal that doubles clock signal frequency.
The present invention further purpose provides a kind of test macro of Fundamental Digital Circuit, and signature analysis device is triggered by rising edge of clock signal and negative edge and receives the data-signal of input in this system.
An other purpose of the present invention provides a kind of test macro of Fundamental Digital Circuit, can eliminate the conflict situation between input data and clock signal in this system.
The present invention's purpose more specifically is, a kind of constructional device is provided, be input to the conflict situation of data-signal and clock signal in the marker graphic generator with elimination, its method is at a data passage or provides a delay circuit that the user is adjustable at clock and data channel simultaneously.
Partly statement in the following description of other purpose of the present invention, this part expert to this area will be very clearly in the explanation below examination, perhaps also can realize in practice of the present invention.By means of the content instrument and the system that specifically note in the claim, various purposes of the present invention and advantage just can realize and obtain.
In order to reach above-mentioned and other purpose, and according to purpose of the present invention, at this a kind of improvement project of marker graphic testing tool has been proposed, it comprises the marker graphic device, in order to detected signal on tested electronic circuit node is decided the response signal that input delivers on the node of this circuit and compared being required to give one.Tester after the improvement comprises and is used to eliminate the data-signal that is input to the marker graphic device and the device of the conflict situation between the clock signal.In addition, also provide regulating device to the device of eliminating conflict situation.
Of the present invention more specifically aspect, adjusting gear comprise one with signalling channel that the marker graphic device links to each other on insert delayer by user's control.This preferably the chronotron of user's may command adjustment be connected on data channel or the clock passage or be connected on respectively on this two passes simultaneously so that the relative timing of clock signal and data-signal is adjusted in control.
Be input to the clock of marker graphic device and this device of the conflict situation between data-signal in order to elimination, can be as eliminating replenishing of marker graphic device intramural conflict state device.This intramural conflict cancellation element can be eliminated the conflict situation that the device internal circuit configuration by marker graphic causes.Thereby improvement of the present invention just can be eliminated by external condition influences the conflict situation that clock signal and data-signal are caused.
Another characteristics of the present invention have provided a kind of structure, and this structure can increase in given clock interval and is input to the quantity of information of marker graphic device to be used to analyze.
One aspect of the present invention provides a kind of structure that not only can eliminate conflict situation but also can increase information.A kind of marker graphic circuit amount of input information that both can increase is provided again on the other hand, again can be at given clock interval internal trigger marker graphic device so that repeatedly receive the device of data.
Best this flip flop equipment is included in the given clock interval, respectively at first and second preset times, and first kind and second kind of device of triggered mark graphics device.
According to an aspect of the present invention, first and second kinds of devices can be at rising edge of clock signal and falling edge triggered mark graphics device.
Other purpose of the present invention, characteristics and advantage are easy to figure out embodiments of the invention are described from following to being about in this field, for the sake of simplicity, adopt diagram and are not limited to finish the best mode of the present invention description of (with other embodiment).In examination description of the invention and just will appreciate that from the practice of the present invention, under the situation of not violating principle of the present invention, the present invention can have other, different embodiment, and each remarkable aspect, some details of the present invention can be revised.Therefore, the diagram that proposes here and describe and to be used to represent principle of the present invention and not as limited field of the present invention.
Fig. 1 represents the typical tester of the prior art of usage flag pattern generator.
Clock that Fig. 2 represents and data waveform illustrate the shortcoming of prior art and the correction of being done according to the present invention thereof.
Fig. 3 (a), 3(b) and 3(c) expression according to notion of the present invention, the block scheme of circuit embodiments is proposed for the shortcoming that overcomes figure (2).
Another shortcoming of the waveform explanation prior art that Fig. 4 represents.
Fig. 5 is expressed as a kind of circuit arrangement block scheme that overcomes Fig. 4 shortcoming.
Fig. 6 represents to improve the specific embodiment of Fig. 5.
Fig. 7 illustrates synthesizing map 3(c) and improved a kind of configuration of Fig. 6.
Referring now to Fig. 1, the figure shows the part of the prior art electronic tester 10 of usage flag pattern generator 12.In prior art, this instrument is to adopt to determine its method to the response sequence of specific supplied with digital signal sequence on the specific node of circuit, tests digital circuit.
Because this instrument is well-known technically, and do not belong to scope of the present invention, therefore unnecessaryly be further described again and omitted, but will point out that marker graphic generator 12 shown in Figure 1 generally comprises a shift register.
As shown in Figure 1, the marker graphic generator is at its input end 14 receive clock signals.This clock signal can be by marker graphic generator 12 or by producing in the unit under test (UUT).Second input end 16 receives data-signal from UUT.Other input end 18 and 20 is used to receive special signal, so that start generation with the stop flag figure by a selected specific time window, in order that will examine or check the response of test point according to any standard known or that wish.
The generation that offers the clock signal of marker graphic generator and startup, stop signal does not belong to ingredient of the present invention.Exactly, main points of the present invention are the clock signal of marker graphic generator input end 14 and 16 and the relation between the data-signal and to the marker graphic generator, in given interval, resolution is by the data signal levels of input end 16 input and the ability at edge, and this given interval is by the clock signal defined of 14 ends input.More particularly, the shift register of marker graphic generator 12 in the time interval of clock signal 14 defineds, receives data on input end 16.As known in the art, generally labeling pattern generator 12 will be checked rising edge in clock signal along the data-signal in the time, and the waveform a of clock signal as shown in Figure 2.On the other hand, also have at the marker graphic generator of clock signal trailing edge along test data.
The problem that the present invention solves is relevant with certain situation, and in this case, data-signal may or change in clock edges when the clock signal saltus step that offers the marker graphic generator.Therefore, the real marking figure potentially unstable that produces by generator 12, and change with the small environmental change that influences clock signal or data-signal.Conflicting of existing between the clock saltus step edge of marker graphic generator and data saltus step edge is referred to as " conflict situation ", and the output result of this conflict determines the form of marker graphic.
With reference to Fig. 2, the waveform of data-signal b has 4 saltus steps.For purposes of illustration, the saltus step 2 and 3 of data-signal is close to the positive transition of clock waveform a, and saltus step 1 and 4 is close to the negative saltus step of clock waveform a.
Thereby, with the negative saltus step triggered mark pattern generator of clock signal when checking data-signal, perhaps data saltus step 1 and 4 can detect, perhaps can not, this depends on which saltus step has superiority in collision.Like this, irrelevant with the work quality of UUT, marker generator 12 will with the irrelevant fully situation of normal operation UUT under, generate the marker graphic of the normal or mal-operation of expression UUT.On the other hand, for the marker graphic generator of data signal under test with clock signal positive transition triggering, data saltus step 2 and 3 may be lost, and also may detect, and it depends on subtle change or other analogues of sequential, triggered time, environmental baseline etc.Therefore, no matter be to trigger with positive transition triggering or negative saltus step, can see that the relation between clock signal and the data-signal may cause unsettled result, promptly may produce a special marker graphic that whether normally has nothing to do fully with the UUT running.What should emphasize is, the problems referred to above are not normally to test the malfunction of the marker graphic generator of the data-signal that is sent to this end and cause owing to import 16 ends at it.
On the contrary, this unsettled marker graphic that produces of generator 12 is only with the coincidence of clock signal and data-signal saltus step or almost overlap relevant.
Therefore the present invention is at 3(a)-3 kinds of structures that overcome the problems referred to above provided in 3(c).As shown in the figure, the present invention introduces the chronotron that can adjust its relative time delay between clock signal and data-signal.As Fig. 3 (a) with 3(c), can utilize chronotron 22 to adjust the relative time delay of clock signal.As Fig. 3 (b) with 3(c), can utilize the time-delay of 24 adjustment data-signals.The scheme that Fig. 3 (c) expression can be adjusted clock signal and data-signal time-delay simultaneously is provided with an arbitrary value or nominal value with Fig. 3 (a)～3(c) chronotron, can set up the predetermined relationship between the clock signal and inhibit signal shown in Fig. 2 waveform a and waveform b.When conflict situation, the user adjusts and postpones just can eliminate conflict situation and increase the stability that generates signature, thereby has improved the reliability of the proving installation that uses this signature analysis device.
For example, shown in Fig. 2 waveform c, data-signal relative time clock signal can be done small leading adjustment.In the embodiment of Fig. 3 (a), the time-delay that available chronotron 22 increases clock signal obtains this leading.Time-delay at the available minimizing chronotron 24 of Fig. 3 (b) obtains this leading data-signal.Scheme shown in Fig. 3 (c) provides or can adjust 22 and increase time-delay, perhaps can adjust 24 and reduce time-delay, perhaps adjusts chronotron 22 and 24 simultaneously, thereby the clean relatively time-delay of the two changes and reaches clock signal with respect to time-delay that data-signal increased.Shown in Fig. 2 waveform c, the saltus step of edge 1 and 4 leading clock signals, thereby eliminated conflict situation therebetween.In like manner, also eliminated conflict situation between edge 3 and the clock signal positive transition.Yet still have conflict situation between edge 2 and the clock signal positive transition.But, with the marker graphic generator that negative edge triggers, the conflict situation that is produced by edge 2 is inessential.
Concerning the marker graphic generator that last saltus step triggers, the adjustment of relative time delay shown in the waveform c can not be any effect.Although the conflict of saltus step 3 has been eliminated, also have the conflict of saltus step 2, though test component and mark generation proving installation can normally move, the stability and the testing reliability of result queue figure also have problem.So the user can adjust delayer in the other direction, makes data-signal lag behind clock signal.Shown in waveform d, such time delay is added to data-signal after, in fact just avoided and the clock signal positive transition between conflict situation.Concerning the marker graphic generator that last saltus step triggers, the conflict situation between the negative saltus step of saltus step 2 and clock signal is inessential.
In order to obtain inhibit signal shown in the waveform D, the nominal value that can reduce chronotron 22 to be reducing the delay of its generation, thereby obtains being ahead of the data-signal of clock signal.Waveform D also can adopt the time-delay that increases chronotron 24 on the other hand, or as obtains by uniting the method for adjusting the clean time-delay that obtains data-signal relative time clock signal in Fig. 3 (c) illustrated embodiment.
Stated that at this user can utilize control to adjust the method and the instrument of signal lag,, and improved reliability of testing result with the instability of the test macro work that solves usage flag pattern analysis instrument.
According to Variable delay device provided by the invention, the user can change the relation between clock signal and the data-signal, so that obtain high-quality, stable marker graphic.This scheme, can be used for designing the signature analysis device of on upper frequency, working, at this moment the transmission delay with respect to clock interval is enough big, also must consider the distortion at clock edge and signal edge simultaneously, can not interfere with each other to guarantee two edge.Because the present invention can be in the test period adjustment of delaying time, so can avoid this two interference between signals and conflict situation.
About this point, for the relation that need between clock signal and digital signal, to obtain, thereby surely become reliable marker graphic, have necessity and repeatedly test.In test each time, can adjust the time-delay between clock signal and the data-signal, and behind some seconds or some hrs and after the changes in environmental conditions, can observe a stable marker graphic.Because the stable available electron technology for detection of marker graphic, for example adopt the method for the variation of the actual measurement marker graphic of determining some and definite marker graphic numerical value, the time-delay among Fig. 3 (a)～3(c) can be a mechanical adjustment.Can progressively increase time-delay with programmable test controller, to obtain the reading of the marker graphic in the whole reference time delay.In the most stable reading, determine the optimum delay district with electronic technology, and its intermediate value can provide more reliable signature.
As previously mentioned, the present invention can make signature analysis device work in higher clock frequency.Yet except at conflict situation shown in Figure 2, the sequential relationship of clock signal and data-signal may hinder the marker graphic generator and go to respond specific data edge.This pass ties up in the waveform of Fig. 4 represents that wherein waveform a represents clock signal, and waveform b represents data-signal.Jump the edge time on the clock and represent that with dot-and-dash line the following jumping edge time will dot, its form is similar to Fig. 2.
As diagram, have this situation, a sufficiently high data-signal of frequency promptly occurs and fail to be labeled pattern generator detecting.Particularly notice use that the marker graphic generator that the saltus step time clock triggers can not detect, reception or observation data saltus step edge 1 and 2, and with the marker graphic generator that following saltus step time clock triggers can not survey, reception or observation data saltus step edge 3,4.Although therefore the prior art device that triggers with the clock signal positive transition can be surveyed the data pulse between saltus step edge 3 and 4, do not detect the data pulse that occurs between saltus step edge 1 and 2.Equally, trigger marker graphic generator, then can only survey saltus step edge 1 and 2 with the prior art that receives data with the negative saltus step of time clock, between data, and can not receive data between saltus step edge 3 and 4.
By providing a kind of in order in clock cycle, the triggered mark pattern generator can repeatedly receive the instrument of data, and the present invention has overcome the deficiency of prior art.In the optimum implementation of mentioning at present, this improvement provides double data markers, promptly can receive a kind of circuit arrangement of two secondary data in a clock interval, as shown in Figure 5.The embodiment of Fig. 5 is at input end 14 receive clock signals, thereby produces the clock signal of twice in circuit 26.Therefore, in each clock interval, circuit 26 produces repeatedly trigger pip, make marker graphic generator 12 in each clock period repeatedly (more precisely 2 times) receive data.Best, in the clock period, it is consistent producing the time interval of repeatedly triggering, so the marker graphic generator just can measure the data-signal incident of specific duration, and no matter all period interval of this signal event.Though the repeatedly triggering sequential by circuit 26 generations can be arbitrarily, concerning the square wave clock signal, trigger pip preferably jumps the edge with going up of clock signal and the following edge of jumping is consistent, because these edges are divided into equal interval to clock signal.Therefore, improved marker graphic generator just on the multiple of clock frequency, receive the input data.
Figure 6 shows that the circuit that produces double trigger pulse in clock signal pulse.Chronotron 28 receives the clock signal of input, and XOR gate 30 is accepted the output and the clock signal of chronotron 28 thereafter.During any part of clock period, when the output level of chronotron 28 was identical with the clock signal level, XOR gate 30 was output as zero.When the clock signal changes, no matter be to rise or descend, two of XOR gate 30 incoming signal level differences then, thereby its output just becomes logical one or high level.After the time-delay that chronotron 28 provides was used up, two input signals of NOR gate circuit 30 were identical again, and made output reduce to low level.
Thereby the time-delay that ifs circuit 28 produces is less than the duration of clock signal shown in the waveform a, and then circuit 26 just produces one with each hopping edge of clock signal shown in Fig. 4 waveform a and goes up and jump edge and one and jump the edge down.Circuit 26 is producing a positive transition with the place of coincidence at each saltus step edge of clock signal, again by by circuit 28 after the time-delay of clock edges setting, produce a negative saltus step.
Therefore, marker graphic generator 12 can be received in each clock hopping edge and jump on one and a jumping triggering input down.Jump along the marker graphic generator that triggers last like this, will between the data-signal hopping edge 1 and 2 that Fig. 4 waveform B is represented, receive trigger pulse.And by hopping edge 1 and 2 and the signal events that characterize of hopping edge 3 and 4 will be accepted, and will be in order to form corresponding marker graphic.Equally, concerning jumping the marker graphic generator that triggers on the edge down, will between data-signal hopping edge 3 and 4, provide one to jump along trigger pip down, form suitable marker graphic so that can receive these two data-signals simultaneously.
This shows, during each clock period, can utilize additional information to form marker graphic by a kind of repeatedly trigger pulse is provided.The clock that produces on two hopping edges of a time clock is input to the quantity of information of twice on the register of marker graphic generator.Thereby Fig. 5 and allocation plan shown in Figure 6 have increased the reliability of marker graphic.
Because under the inspiration of above-mentioned data, just can produce many changes and change, the front only is used for description and interpretation the present invention to the description of the embodiment of the invention, and is not intended as the complete open form of the present invention or limits the invention to this simple and clear open form.The selection of embodiment and description are in order to explain principle of the present invention and practical application thereof best, thereby make other expert of this area find various embodiment and improvement project from the present invention, make it be applied to the specific occasion maturely.When doing when explaining according to the scope that the present invention has justice, a legal right, scope of the present invention plans to set forth in the claims.
Claims (13)
1, at a kind of testing tool that is used for electronic circuit, it comprises a kind of dynamic pulse signal (i.e. signal that can observe on a circuit node, sort signal is in response to a kind of predetermined dynamic pulse input signal that is added to this circuit) with a kind of marker graphic device that can be correctly compares in response to the signal (i.e. the signal that on the circuit node of corresponding operate as normal, can observe) of this pulse input signal, it is improved to be characterised in that it comprises: the device that is used to eliminate conflict situation between the clock signal that is input to aforementioned marker graphic device and the data-signal; And the used adjustable adjusting gear of device of adjusting above-mentioned elimination conflict.
2, a kind of improved tester as claimed in claim 1, wherein, but the adjusting gear of elimination conflict device is included in the controlled chronotron of user that inserts on the signalling channel that connects this marker graphic device.
3, a kind of improved tester as claimed in claim 2, wherein, the device of the controlled time-delay of above-mentioned user comprises an adjustable time delay that inserts on clock signal channel, in order to this clock signal of clock signal that adjustable sequential is provided to aforementioned marker graphic device is to receive at this marker graphic device, so that on the data-signal that occurs on the data signal channel, trigger aforementioned marker graphic device, and make the adjustable relative timing of putting in order between this clock signal and this data-signal of user thus, to eliminate the conflict situation between them.
4, a kind of improved tester as claimed in claim 3, wherein, user's adjustable time delay is included in and inserts another Variable delay device on the data signal channel, in order to adjust sequential for the used data-signal of aforementioned marker graphic device analysis, the time of reception of data-signal is definite by aforementioned clock signal, thereby the device of the relative timing between aforementioned clock signal of another kind of adjustment and the aforementioned data signal is provided.
5, a kind of improved tester as claimed in claim 2, wherein, the controlled chronotron of above-mentioned user comprises the adjustable time delay of incoming data signal passage, in order to above-mentioned clock signal be adjusted on true time receive on the above-mentioned marker graphic device, for the sequential of analyzing used data-signal, thereby adjust relative timing between above-mentioned clock signal and the aforementioned data signal to eliminate conflict situation.
6, a kind of improved tester as claimed in claim 1, wherein, above-mentioned marker graphic device also comprises in order to eliminate the device of the conflict situation that is caused by internal circuit configuration.
7, a kind of improved tester as claimed in claim 1 wherein, comprises in order to increase the device of the quantity of information that inputs to the marker graphic device in aforementioned given clock period.
8, a kind of improved tester as claimed in claim 7, wherein, the device of increase information comprises in order to triggered mark graphics device on saltus step edge on the above-mentioned clock signal and following saltus step edge, thereby in each time clock, above-mentioned marker graphic device is provided the device of twice input data.
9, be used for a kind of a kind of tester of electronic circuit, comprise the marker graphic device, in order to (it can be during clock interval with a kind of dynamic pulse signal, on a circuit junction, be added to dynamic pulse input signal this circuit input end, predetermined and be observed along with a kind of) can be exactly compare with a kind of in response to the signal of above-mentioned pulse input signal (can on a respective nodes of the circuit of an operate as normal, observe), this is improved to be characterised in that it comprises:
In order in above-mentioned clock interval, increase the device of the quantity of information that is input to aforementioned marker graphic device, it comprises:
In order in a clock interval, trigger above-mentioned marker graphic device, carry out repeatedly the device of received signal from above-mentioned node.
10, a kind of improved tester as claimed in claim 9 wherein, comprises in order to the device that triggers:
In order in aforementioned clock interval, trigger first kind of device of aforementioned marker graphic device in first schedule time.
In order in aforementioned clock interval, trigger second kind of device of aforementioned marker graphic device in second schedule time.
11, a kind of improved tester as claimed in claim 10, wherein above-mentioned first kind of device comprises the device that triggers aforementioned marker graphic fixture in order to jumping edge on time clock, and second kind of device comprises in order to jump the device that the edge triggers aforementioned marker graphic device under time clock.
12, a kind of improved tester as claimed in claim 9 also comprises in order to eliminate the conflict canceller of the conflict situation between clock signal that is limited by above-mentioned clock interval and the data-signal that is input to aforementioned marker graphic device.
Above-mentioned conflict canceller is included in the Variable delay device that inserts user's control on the clock signal channel, so that the clock signal of an adjustable sequential is provided to aforementioned marker graphic device, in order to trigger the data-signal of on the data channel on the aforementioned marker graphic device, being received, thereby make user's may command, adjust the relative timing of aforementioned clock signal and data-signal, so that eliminate the conflict situation between them.
13, a kind of improved tester as claimed in claim 9 also comprises the conflict canceller in order to the conflict situation between the clock interval of eliminating aforementioned clock signal regulation and the data-signal that is input to aforementioned marker graphic device.
Above-mentioned conflict canceller is included in the chronotron that inserts the controlled adjustment of user on the data signal channel, so that adjust the sequential for the data-signal of analyzing usefulness that aforementioned marker graphic device receives, the time of reception of this data-signal is determined by aforementioned clock signal.Thereby, just can adjust the relative timing between aforementioned clock signal and the aforementioned data signal, so that eliminate the conflict situation between them.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US76155885A | 1985-08-01 | 1985-08-01 | |
| US761,558 | 1985-08-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN86101621A true CN86101621A (en) | 1987-01-28 |
Family
ID=25062580
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN198686101621A Pending CN86101621A (en) | 1985-08-01 | 1986-03-13 | Improved signature analysis device for electronic circuits |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPS6232376A (en) |
| CN (1) | CN86101621A (en) |
| DE (1) | DE3625919A1 (en) |
| FR (1) | FR2585845A1 (en) |
| GB (1) | GB2178542B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5231314A (en) * | 1992-03-02 | 1993-07-27 | National Semiconductor Corporation | Programmable timing circuit for integrated circuit device with test access port |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3633100A (en) * | 1970-05-12 | 1972-01-04 | Ibm | Testing of nonlinear circuits by comparison with a reference simulation with means to eliminate errors caused by critical race conditions |
| US3976864A (en) * | 1974-09-03 | 1976-08-24 | Hewlett-Packard Company | Apparatus and method for testing digital circuits |
| US4551837A (en) * | 1983-03-25 | 1985-11-05 | International Telephone & Telegraph Corp. | High speed operational recurring signature evaluator for digital equipment tester |
| US4564943A (en) * | 1983-07-05 | 1986-01-14 | International Business Machines | System path stressing |
| DE3325247A1 (en) * | 1983-07-13 | 1985-01-24 | ANT Nachrichtentechnik GmbH, 7150 Backnang | CIRCUIT ARRANGEMENT FOR TESTING A DIGITAL CIRCUIT |
| JPS6089775A (en) * | 1983-08-01 | 1985-05-20 | フエアチアイルド カメラ アンド インストルメント コ−ポレ−シヨン | Test period generator for automatic testing equipment |
-
1986
- 1986-03-13 CN CN198686101621A patent/CN86101621A/en active Pending
- 1986-05-15 GB GB8611880A patent/GB2178542B/en not_active Expired - Fee Related
- 1986-07-04 FR FR8609794A patent/FR2585845A1/en active Pending
- 1986-07-04 JP JP61158637A patent/JPS6232376A/en active Pending
- 1986-07-31 DE DE19863625919 patent/DE3625919A1/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6232376A (en) | 1987-02-12 |
| GB8611880D0 (en) | 1986-06-25 |
| DE3625919A1 (en) | 1987-02-12 |
| GB2178542A (en) | 1987-02-11 |
| GB2178542B (en) | 1990-07-11 |
| FR2585845A1 (en) | 1987-02-06 |
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