CN219872231U - Vehicle-standard LIN bus high-transient-response LDO - Google Patents
Vehicle-standard LIN bus high-transient-response LDO Download PDFInfo
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Abstract
The utility model discloses a vehicle-standard LIN bus high transient response LDO, which belongs to the automobile bus technology and comprises an LDO main loop, wherein an NMOS (N-channel metal oxide semiconductor) adjusting tube N is arranged on the LDO main loop 0 OP of main loop operational amplifier a Novel slew rate enhancement module, protection module, super source follower and feedback resistor R FB ；N 0 Electrically connected OP a Novel slew rate enhancement module, protection module and R FB ；OP a The novel slew rate enhancement module and the super source follower are electrically connected; the protection module is electrically connected with the novel slew rate enhancement module and the super source follower. Through the mode, the utility modelCompared with the traditional main negative feedback load capacitor compensation mode, the compensation effect is improved, and the response time is reduced.
Description
Technical Field
The utility model relates to an automobile bus technology, in particular to a vehicle-standard LIN bus high transient response LDO.
Background
Under the background of carbon neutralization, new energy automobiles are rapidly developed. With the popularization of 5G, vehicle network technology is widely used. And the vehicle-mounted network technology comprises an automobile mobile internet technology and an automobile bus technology. Through the automobile bus technology, each electric control unit in the automobile can be associated, and each node is communicated with each other through a bus. At present, a LIN bus and a controller area network (CAN: controller Area Network) bus are widely adopted on automobiles. Compared with the conventional bus, the vehicle-standard LIN bus has the advantages of strong anti-interference performance, high integration level, good stability and the like, and gradually becomes the main development trend of the vehicle bus. LIN can have instantaneous currents up to several hundred milliamperes in the operating mode, and quiescent currents down to microampere levels in the sleep or standby mode. Therefore, in the transient switching process of the working mode (heavy load), the sleep mode and the standby mode (light load), the LIN bus can generate abrupt rising of transient voltage and current, and digital logic dysfunction or breakdown of the MOS transistor can be easily caused to damage the chip. The LDO has the characteristics of simple structure, high transient response and power supply rejection ratio and the like, so that the stable and reliable operation of the vehicle-standard LIN bus can be ensured.
FIG. 1 is a conventional LDO architecture, mainly comprising an error amplifier OP, a BUFFER (BUFFER), a tuning tube (Pass transistor) and a feedback Resistor (RFB).
The LDO performance improving module design of independent enhancement, protection, compensation and the like is omitted. Therefore, the conventional LDO mainly has the following three problems:
firstly, the traditional LDO has no transient enhancement module design, when the load suddenly changes from heavy load to light load, the adjusting tube cannot timely respond to the load suddenly by adjusting the grid voltage through the main negative feedback loop, and at the moment, the changed differential current totally floods into the feedback loop to flow to the ground, so that the hundreds of millivolts of upper-punch voltage can be caused; similarly, when the light load suddenly changes into heavy load, the large undershoot voltage is caused, so that the transient response of the traditional LDO completely depends on the regulation of the main negative feedback loop, the regulation effect is poor, and the transient response time is long.
Secondly, the traditional LDO is simple to improve transient response, and a load capacitor with several tens of picocoats to hundreds of picocoats can be externally connected to a load end. When the load suddenly changes from heavy load to light load, the changed differential current charges a load capacitor to absorb additional differential current; when the light load suddenly changes into heavy load, the load capacitor provides additional differential current for the discharge of the load end, so that the space for improving transient response is limited. Therefore, the excessive load capacitance of the conventional LDO occupies a large amount of chip area, and reduces the output pole frequency to cause output oscillation.
Thirdly, the power supply voltage in practice is non-ideal, so that the non-ideal power supply has to have noise and interference and the power supply voltage can slightly fluctuate when the load changes. Therefore, when the conventional LDO has no power supply rejection ratio enhancement design, the output voltage stabilizing value of the conventional LDO changes along with the fluctuation of non-ideal power supply voltage.
Based on the above, the utility model designs a vehicle-standard LIN bus high transient response LDO to solve the above problems.
Disclosure of Invention
Aiming at the defects existing in the prior art, the utility model provides a vehicle-standard LIN bus high transient response LDO.
In order to achieve the above purpose, the utility model is realized by the following technical scheme:
a high transient response LDO of a vehicle-standard LIN bus comprises an LDO main loop, wherein an NMOS adjusting tube N is arranged on the LDO main loop 0 OP of main loop operational amplifier a Novel slew rate enhancement module, protection module, super source follower and feedback resistor R FB ，N 0 Electrically connected OP a Novel slew rate enhancement module, protection module and R FB ；OP a The novel slew rate enhancement module and the super source follower are electrically connected; the protection module is electrically connected with the novel slew rate enhancement module and the super source follower.
Further, the novel slew rate enhancement module comprises a sampling operational amplifier OP b Compensation OP c ，OP b Electric connection protection module, OP c 、N 0 And a super source follower; OP (optical path) c Electrically connected OP a Super source follower and N 0 。
Further, it also includes a resistor R 3 Current source I PTAT PMOS tube P 1 PMOS tube P 2 PMOS tube P 6 PMOS tube P 7 NMOS tube N 1 NMOS tube N 3 And NMOS tube N 12 ；N 0 The drain electrode is connected with the power supply voltage V DD ，N 0 Source electrode connection R FB ，N 0 Gate connection OP b 、OP c And a super source follower; output voltage V out From N 0 A source electrode; r is R FB In series with N 0 Between the source and the ground terminal, V FB Is R FB For output voltage V out Is a partial pressure of (2); p (P) 1 The source is connected to a supply voltage V DD ，P 1 Gate connection to P 2 Grid electrode P 1 Drain connected to P 6 Source electrode, P 1 Gate connection to P 1 A drain electrode; p (P) 2 The source is connected to a supply voltage V DD ，P 2 Drain connected to P 7 Source electrode, P 2 The gate is connected to OP a ；P 6 Gate connection to P 7 Grid electrode P 6 Drain electrode is connected with a current source I PTAT Positive electrode, P 6 Gate connection P 6 A drain electrode; p (P) 7 Drain electrode connection N 1 Drain electrode, P 7 Gate connection OP a ；N 1 Gate connection OP a ，N 1 Source electrode connection N 3 Drain, N 1 Gate connection N 1 A drain electrode; n (N) 3 Source electrode is grounded, N 3 Gate connection OP a The method comprises the steps of carrying out a first treatment on the surface of the Current source I PTAT The negative electrode is grounded; n (N) 12 Source electrode is grounded, N 12 Gate connection OP b 、N 12 Drain connecting resistor R 3 Resistance R 3 In series with N 0 Source electrode and N 12 Between the drains.
Further, the main loop OP a Comprises a PMOS tube P 3 PMOS tube P 4 PMOS tube P 5 PMOS tube P 8 PMOS tube P 9 PMOS tube P 10 PMOS tube P 11 PMOS tube P 22 PMOS tube P 23 NMOS tube N 2 NMOS tube N 4 NMOS tube N 5 NMOS tube N 6 NMOS tube N 7 And NMOS tube N 8 ；P 3 Source electrode is connected with a power supply V DD ，P 3 Drain connected to P 5 Source electrode and P 4 Grid electrode P 3 Gate connection P 10 Grid electrode and P 2 A gate; p (P) 4 The source is connected to a supply voltage V DD ，P 4 Drain connected to P 8 Source electrode and P 9 Source electrode and P 5 A gate; p (P) 5 Drain is connected to N 2 A drain electrode; p (P) 8 Drain electrode connection N 6 Drain electrode, P 8 Source connection P 9 Source electrode, P 8 The grid electrode is connected with a reference voltage V REF ；P 9 Drain electrode connection P 22 Drain electrode, P 9 The grid electrode is connected with a feedback resistor R FB For output voltage V out Is of the partial pressure V of FB ；P 10 The source is connected with a power supply voltage V DD ，P 10 Gate connection P 11 Grid electrode P 10 Drain electrode connection P 22 A source electrode; p (P) 11 The source is connected with a power supply voltage V DD ，P 11 Drain electrode connection P 23 Source electrode, P 11 The grid electrode is connected with the super source follower; p (P) 22 Gate connection P 7 Grid electrode and P 23 Grid electrode P 22 Drain electrode connection N 5 A drain electrode; p (P) 23 Drain electrode connection N 6 Drain and super source follower; n (N) 2 Gate connection N 1 Grid and N 5 Grid electrode, N 2 Source electrode connection N 4 A drain electrode; n (N) 4 Gate connection N 3 Grid electrode, N 4 The source electrode is connected with the ground; n (N) 5 Source electrode connection N 7 Drain, N 5 Gate connection N 6 Grid electrode, N 5 Drain electrode connection N 7 A gate; n (N) 6 Source electrode connection N 8 Drain, N 6 The grid electrode is connected with the super source follower; n (N) 7 Gate connection N 8 Grid electrode, N 7 The source electrode is grounded; n (N) 8 The source is grounded.
Further, the super source follower comprises a PMOS tube P 12 PMOS tube P 24 NMOS tube N 9 And NMOS tube N 19 ；P 12 Gate connection P 23 Drain electrode, P 12 Drain electrode connection N 19 Drain electrode, P 12 Source connection P 24 Drain, N 12 Drain, OP c 、OP b And N 0 A gate electrode of (a); p (P) 24 The source is connected with a power supply voltage V DD ，P 24 Gate connection P 11 Grid and OP c ；N 9 Gate connection P 12 Drain, N 9 Source electrode is grounded, N 9 Drain electrode connection P 12 A source electrode; n (N) 19 Gate connection N 6 Grid electrode, N 19 Source electrode is grounded, N 19 Drain electrode connection N 9 And a gate.
Further, compensating OP c Comprises a compensation capacitor C 1 PMOS tube P 13 PMOS tube P 14 PMOS tube P 15 PMOS tube P 16 PMOS tube P 17 NMOS tube N 16 NMOS tube N 17 NMOS tube N 20 NMOS tube N 21 NMOS tube N 22 NMOS tube N 23 NMOS tube N 24 NMOS tube N 25 Resistance R 1 And resistance R 2 ；P 13 The source is connected with a power supply voltage V DD ，P 13 Gate connection P 15 Grid electrode P 13 Drain electrode connection N 20 Drain electrode, P 13 Drain electrode connection P 13 A gate; p (P) 14 The source is connected with a power supply voltage V DD ，P 14 Gate connection P 24 Grid electrode P 14 Drain electrode connection P 16 Source electrode and P 17 A source electrode; p (P) 15 The source is connected with a power supply voltage V DD 、P 15 Drain electrode connection N 23 A drain electrode; p (P) 16 Drain electrode connection N 23 Drain and N 25 Grid electrode P 16 Gate connection OP b ；P 17 Drain electrode connection N 25 Drain and N 24 Grid electrode P 17 The grid electrode is connected with the output voltage V out ；N 16 Source electrode is grounded, N 16 Gate connection R 2 ，N 16 Drain electrode connection P 15 Drain and N 17 A gate; n (N) 17 Source electrode is grounded, N 17 Grid connection resistor R 2 And N 16 Drain, N 17 Drain connecting resistor R 1 ；N 20 Source electrode is grounded, N 20 Gate connection N 21 Grid electrode and P 16 A drain electrode; n (N) 21 Source electrode is grounded, N 21 Drain electrode connection N 24 A source electrode; n (N) 22 Source electrode is grounded, N 22 Drain electrode connection N 25 Source, N 22 Gate connection N 23 Grid and N 25 A drain electrode; n (N) 23 The source electrode is grounded; n (N) 24 Gate connection N 25 Drain, N 24 Drain electrode connection N 21 Grid and N 25 A gate; n (N) 25 Drain electrode connection N 22 A gate; r is R 1 In series with N 17 Drain and P 12 The source electrodes are arranged between the source electrodes; r is R 2 In series with N 16 Grid and N 17 The grid electrodes are arranged between the grid electrodes; c (C) 1 The negative electrode is grounded, C 1 Positive electrode connection P 12 And a gate.
Further, the sampling operational amplifier OP b Comprises a PMOS tube P 18 PMOS tube P 19 PMOS tube P 20 PMOS tube P 21 NMOS tube N 10 NMOS tube N 11 NMOS tube N 14 NMOS tube N 15 NMOS tube N 18 NMOS tube N 19 ；P 18 The source is connected with a power supply voltage V DD 、P 18 Drain electrode connection N 10 Drain electrode, P 18 Gate connection P 19 Grid electrode P 18 Gate connection P 18 A drain electrode; p (P) 19 The source is connected with a power supply voltage V DD ，P 19 Drain electrode connection P 20 Source electrode and P 21 A source electrode; p (P) 20 Drain electrode connection N 18 Drain electrode, P 20 Gate connection P 16 Grid and N 14 A drain electrode; p (P) 21 Drain electrode connection N 14 Grid and N 19 Drain electrode, P 21 Gate connection P 17 Gate and output voltage V out ；N 10 Source electrode is grounded, N 10 Gate connection N 1 Source electrode and N 11 A gate; n (N) 11 Source electrode is grounded, N 11 Gate connection N 12 Grid electrode, N 11 Drain electrode connection N 14 Source electrode and N 14 A gate; n (N) 14 Gate connection P 19 Drain and N 19 Drain, N 14 Drain electrode connection N 15 Source electrode and P 16 A gate; n (N) 15 Gate connection P 24 Drain and N 0 Grid electrode, N 15 The drain electrode is connected with the power supply voltage V DD ；N 18 Source electrode is grounded, N 18 Drain electrode connection P 20 Drain, N 18 Gate connection N 19 Grid electrode, N 18 Grid and N 18 The drain electrode is connected; n (N) 19 Source electrode is grounded, N 19 Drain electrode connection N 14 Grid electrode and P 21 And a drain electrode.
Further, the protection module comprises a first protector and a second protector; the protection module comprises a first protector and a second protector, wherein the first protector is electrically connected with the N 0 、OP b 、OP c And a super source follower; second protector electric connection first protector N 0 、OP b 、OP c And a super source follower.
Further, the protector I consists of a diode D 1 And NMOS tube N 13 Constructing; d (D) 1 Positive electrode connection N 0 Grid electrode D 1 Negative electrode connection N 13 A drain electrode; n (N) 13 Gate connection N 11 Drain, N 13 The source is grounded.
Further, the second protector consists of N 15 And resistance R 4 Constructing; resistor R 4 Connected in series with the power supply voltage V DD And N 15 Between the sources.
Advantageous effects
With the structure of the utility model, the main loop operational amplifier OP a Ensuring loop gain, loop bandwidth, load adjustment rate and power supply rejection ratio for the LDO main loop; the novel slew rate enhancement module is used for carrying out mutation compensation on the overshoot or undershoot caused by load mutation; the protection module is used for protecting the novel slew rate enhancement module from still working stably when the LDO or the power supply voltage is abnormal; the novel slew rate enhancement module does not depend on a capacitive element to compensate for load abrupt change, so that the problem that a large amount of chip area is occupied by overlarge load capacitance is avoided; the novel slew rate enhancement module can rapidly transfer the overshoot or the undershoot and rapidly carry out the overshoot or the undershoot compensation, and compared with the traditional main negative feedback load capacitor compensation mode, the slew rate enhancement module has the advantages of improving the compensation effect and reducing the response time.
With the structure of the utility model, the main loop operational amplifier OP a Adopt folding Casode operational amplifierAt the same time at OP a The internal tail current designs the negative feedback circuit structure. OP (optical path) a Internal tail current negative feedback circuit P 5 And P 4 If P is formed by 5 P when the gate voltage of (1) rises or falls due to power supply fluctuation 5 And P 3 Can be equivalently a source follower, so P 5 The source voltage of P rises or falls 5 Is also taken as P 4 Gate voltage of (a); at this time P 9 、P 8 And P 4 Common source amplifier capable of equivalently using MOS tube as load, so P 4 Is decreased or increased, P 4 Is also taken as P 5 The fluctuation of the final power supply is offset by negative feedback, and thus the slight fluctuation of the power supply voltage can be resisted.
With the structure of the utility model, OP c To compensate for operational amplification, the OP is not in the LDO main loop c The circuit is of a two-stage operational amplifier structure, the first-stage circuit structure is of an AB type symmetrical operational amplifier, and a pair of cross-coupled MOS transistors N with proper size (W/L) is designed through alternating current and transient simulation 24 And N 25 The second stage is R 1 And N 17 Is included in the common source amplifier of (a). OP (optical path) c The function of (2) is to dynamically adjust N along with load change when load suddenly changes 1 Grid voltage control adjusting tube N 0 Gate terminal charge-discharge speed.
With the structure of the utility model, OP b For sampling op-amp, not in the LDO main loop. The circuit structure is a two-stage operational amplifier. OP (optical path) b The function of (2) is mainly to clamp P by means of high gain characteristic of two-stage operational amplifier 20 And P 21 Is transferred to OP c Is connected to the inverting input terminal P of (1) 16 。
By adopting the structure of the utility model, the process consists of OP b And OP (optical path) c The novel slew rate enhancement module can improve transient response. OP when load mutation occurs b Transfer of undershoot or undershoot to OP c ，OP c The overshoot or undershoot caused by the abrupt load change can be compensated rapidly. When the load end suddenly changes from heavy load to light load to cause the up-rush, the OP c P of (2) 16 Gate end sampling OP b Output voltage, OP of (a) c P of (2) 17 Sampling the voltage of the output end of the LDO, and OP in the process of up-flushing c The output voltage of the first stage is suddenly increased and used as the second stage N 17 Is biased by the gate terminal of N 17 Branch current suddenly increases and branches to power tube N 0 The charging current at the gate end pulls down the gate voltage of the power tube, and reduces the V of the power tube GS Thus, the output branch current is reduced, and the up-cancellation is realized. When the load end suddenly changes from light load to heavy load to cause undershoot, OP c Is sampled OP at the inverting input of (1) b Output voltage, OP of (a) c The in-phase input end of the second-stage amplifier samples the voltage of the output end, so that the output voltage of the first-stage amplifier is suddenly reduced and is used as the grid voltage of the input tube of the second-stage amplifier, so that the current of the second-stage amplifier circuit suddenly drops, and flows to the grid end of the power tube to charge the equivalent capacitance of the grid oxide layer, thereby raising the grid voltage of the power tube and raising the V of the power tube GS Thereby raising the output current and realizing undershoot compensation.
With the structure of the utility model, OP b N of the second stage of (2) 11 Is biased in the linear region, N when LDO is normal 11 The voltage of the drain terminal is very small and the post-stage N 13 And D 1 Form a current-limiting protection circuit, when N 15 Or N 14 The grid voltage of the LDO is rapidly increased due to the abnormal work of the LDO or the abnormal power supply voltage, so that N 11 The drain voltage of (a) rises to N 13 V of (2) TH After turn on N 13 And D 1 The path is used for discharging the LDO, thereby protecting the LDO. OP (optical path) b N of (2) 15 And a resistance R of 140KΩ 4 Parallel connection can reduce N 15 The output impedance of the output terminal, pushing the pole to high frequency without compensating OP b 。
Drawings
In order to more clearly illustrate the embodiments of the present utility model or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It is evident that the drawings in the following description are only some embodiments of the present utility model and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a diagram of a conventional LDO architecture;
FIG. 2 is a schematic diagram of a vehicle-standard LIN bus high transient response LDO architecture according to the present utility model;
FIG. 3 is a schematic diagram of a vehicle-standard LIN bus high transient response LDO circuit of the present utility model;
FIG. 4 is a schematic diagram of an equivalent circuit of a vehicle-standard LIN bus high transient response LDO small signal according to the present utility model;
FIG. 5 is a simulation graph of TT process corner transient response;
FIG. 6 is a graph of a full process corner transient response simulation;
FIG. 7 is a graph of amplitude-frequency characteristic simulation at full process angle;
FIG. 8 is a graph of amplitude-frequency characteristic simulation under full load;
FIG. 9 is a simulation graph of the full process corner power supply rejection ratio for a load current of 50 mA;
FIG. 10 is a graph of simulation of load adjustment rate over TT process corner and full temperature range;
FIG. 11 is a graph of a full process angle and full load range Tran slow power-up simulation;
fig. 12 is a graph of simulated ttprocess corner transient response.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present utility model more clear, the technical solutions of the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model. It will be apparent that the described embodiments are some, but not all, embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
The utility model is further described below with reference to examples.
Example 1
Referring to the accompanying drawings 2-3 of the specification, a vehicle-standard LIN bus high transient response LDO comprises an LDO main loop, wherein the LDO main loop is provided with a main loopOperational amplifier OP a Novel slew rate enhancement modules, protection modules, super source followers, tuning tubes (NMOS, i.e. N 0 ) And a feedback resistor R FB ；N 0 Electrically connected OP a Novel slew rate enhancement module, protection module and R FB ；OP a The novel slew rate enhancement module and the super source follower are electrically connected; the protection module is electrically connected with the novel slew rate enhancement module and the super source follower.
Main loop operational amplifier OP a Ensuring loop gain, loop bandwidth, load adjustment rate and power supply rejection ratio for the LDO main loop; the novel slew rate enhancement module is used for carrying out mutation compensation on the overshoot or undershoot caused by load mutation; the protection module is used for protecting the novel slew rate enhancement module from still working stably when the LDO or the power supply voltage is abnormal; the novel slew rate enhancement module does not depend on a capacitive element to compensate for load abrupt change, so that the problem that a large amount of chip area is occupied by overlarge load capacitance is avoided; the novel slew rate enhancement module can rapidly transfer the overshoot or the undershoot and rapidly carry out the overshoot or the undershoot compensation, and compared with the traditional main negative feedback load capacitor compensation mode, the slew rate enhancement module has the advantages that the compensation effect is improved and the response time is reduced.
Novel slew rate enhancement module comprises sampling operational amplifier OP b Compensation OP c ，OP b Electric connection protection module, OP c 、N 0 And a super source follower; OP (optical path) c Electrically connected OP a Super source follower and N 0 。
When a load mutation occurs, OP b Transfer of the undershoot or undershoot to the OP c ，OP c The overshoot or undershoot caused by the abrupt load change can be compensated rapidly.
Main loop operational amplifier OP a Comprises a PMOS tube P 3 PMOS tube P 4 PMOS tube P 5 PMOS tube P 8 PMOS tube P 9 PMOS tube P 10 PMOS tube P 11 PMOS tube P 22 PMOS tube P 23 NMOS tube N 2 NMOS tube N 4 NMOS tube N 5 NMOS tube N 6 NMOS tube N 7 And NMOS tube N 8 The method comprises the steps of carrying out a first treatment on the surface of the The main loop also comprises a resistor R 3 Current source I PTAT PMOS tube P 1 PMOS tube P 2 PMOS tube P 6 PMOS tube P 7 NMOS tube N 1 NMOS tube N 3 And NMOS tube N 12 ；N 0 The drain electrode is connected with the power supply voltage V DD ，N 0 Source electrode connection R FB ，N 0 Gate connection OP b 、OP c And a super source follower; output voltage V out Taking N 0 A voltage between the source and ground; r is R FB In series with N 0 Between source and ground, V FB Is R FB For output voltage V out Partial pressure; p (P) 1 The source is connected to a supply voltage V DD ，P 1 Gate connection to P 2 Grid electrode P 1 Drain connected to P 6 Source electrode, P 1 Gate connection to P 1 A drain electrode; p (P) 2 The source is connected to a supply voltage V DD ，P 2 Drain connected to P 7 Source electrode, P 2 Gate connection to P 3 A gate; p (P) 3 Source electrode is connected with a power supply V DD ，P 3 Drain connected to P 5 Source electrode and P 4 Grid electrode P 3 Gate connection P 10 A gate; p (P) 4 The source is connected to a supply voltage V DD ，P 4 Drain connected to P 8 Source electrode and P 9 Source electrode and P 5 A gate; p (P) 5 Drain is connected to N 2 A drain electrode; p (P) 6 Gate connection to P 7 Grid electrode P 6 Drain electrode is connected with a current source I PTAT Positive electrode, P 6 Gate connection P 6 A drain electrode; p (P) 7 Drain electrode connection N 1 Drain electrode, P 7 Gate connection P 22 A gate; p (P) 8 Drain electrode connection N 6 Drain electrode, P 8 Source connection P 9 Source electrode, P 8 The grid electrode is connected with a reference voltage V REF ；P 9 Drain electrode connection P 22 Drain electrode, P 9 The grid electrode is connected with a feedback resistor R FB For output voltage V out Is of the partial pressure V of FB ；P 10 The source is connected with a power supply voltage V DD ，P 10 Gate connection P 11 Grid electrode P 10 Drain electrode connection P 22 A source electrode; p (P) 11 The source is connected with a power supply voltage V DD ，P 11 Drain electrode connection P 23 Source electrode, P 11 The grid electrode is connected with the super source follower; p (P) 22 Gate connection P 23 Grid electrode P 22 Drain electrode connection N 5 A drain electrode; p (P) 23 Drain electrode connection N 6 Drain and super source follower; n (N) 1 Gate connection N 2 Grid electrode, N 1 Source electrode connection N 3 Drain, N 1 Gate connection N 1 A drain electrode; n (N) 2 Gate connection N 5 Grid electrode, N 2 Source electrode connection N 4 A drain electrode; n (N) 3 Source electrode is grounded, N 3 Gate connection N 4 A gate; n (N) 4 The source electrode is connected with the ground; n (N) 5 Source electrode connection N 7 Drain, N 5 Gate connection N 6 Grid electrode, N 5 Drain electrode connection N 7 A gate; n (N) 6 Source electrode connection N 8 Drain, N 6 The grid electrode is connected with the super source follower; n (N) 7 Gate connection N 8 Grid electrode, N 7 The source electrode is grounded; n (N) 8 The source electrode is grounded; current source I PTAT The negative electrode is grounded; n (N) 12 Source electrode is grounded, N 12 Gate connection OP b 、N 12 Drain connecting resistor R 3 Resistance R 3 In series with N 0 Source electrode and N 12 Between the drains.
Main loop operational amplifier OP a The circuit is a main operational amplifier, is positioned in an LDO main loop and has a folding operational amplifier structure. Using folded Casode OP-amp at the same time as OP a The internal tail current designs the negative feedback circuit structure. OP (optical path) a Internal tail current negative feedback circuit P 5 And P 4 If P is formed by 5 P when the gate voltage of (1) rises or falls due to power supply fluctuation 5 And P 3 Can be equivalently a source follower, so P 5 The source voltage of P rises or falls 5 Is also taken as P 4 Gate voltage of (a); at this time P 9 、P 8 And P 4 Common source amplifier capable of equivalently using MOS tube as load, so P 4 The drain voltage of (2) drops or rises, which in turn acts as P 5 The fluctuation of the final power supply is offset by negative feedback, and thus the slight fluctuation of the power supply voltage can be resisted.
Super source follower including PMOS pipe P 12 PMOS tube P 24 NMOS tube N 9 And NMOS tube N 19 ；P 12 Gate connection P 23 Drain electrode, P 12 Drain electrode connection N 19 Drain electrode, P 12 Source connection P 24 Drain, N 12 Drain, OP c 、OP b And N 0 A gate electrode of (a); p (P) 24 The source is connected with a power supply voltage V DD ，P 24 Gate connection P 11 Grid and OP c ；N 9 Gate connection P 12 Drain, N 9 Source electrode is grounded, N 9 Drain electrode connection P 12 A source electrode; n (N) 19 Gate connection N 6 Grid electrode, N 19 Source electrode is grounded, N 19 Drain electrode connection N 9 And a gate.
Compensation OP c Comprising compensation capacitor C 1 PMOS tube P 13 PMOS tube P 14 PMOS tube P 15 PMOS tube P 16 PMOS tube P 17 NMOS tube N 16 NMOS tube N 17 NMOS tube N 20 NMOS tube N 21 NMOS tube N 22 NMOS tube N 23 NMOS tube N 24 NMOS tube N 25 Resistance R 1 And resistance R 2 ；P 13 The source is connected with a power supply voltage V DD ，P 13 Gate connection P 15 Grid electrode P 13 Drain electrode connection N 20 Drain electrode, P 13 Drain electrode connection P 13 A gate; p (P) 14 The source is connected with a power supply voltage V DD ，P 14 Gate connection P 24 Grid electrode P 14 Drain electrode connection P 16 Source electrode and P 17 A source electrode; p (P) 15 The source is connected with a power supply voltage V DD 、P 15 Drain electrode connection N 23 A drain electrode; p (P) 16 Drain electrode connection N 23 Drain and N 25 Grid electrode P 16 Gate connection OP b ；P 17 Drain electrode connection N 25 Drain and N 24 Grid electrode P 17 The grid electrode is connected with the output voltage V out ；N 16 Source electrode is grounded, N 16 Gate connection R 2 ，N 16 Drain electrode connection P 15 Drain and N 17 A gate; n (N) 17 Source electrode is grounded, N 17 Grid connection resistor R 2 And N 16 Drain, N 17 Drain connecting resistor R 1 ；N 20 Source electrode is grounded, N 20 Gate connection N 21 Grid electrode and P 16 A drain electrode; n (N) 21 Source electrode is grounded, N 21 Drain electrode connection N 24 A source electrode; n (N) 22 Source electrode is grounded, N 22 Drain electrode connection N 25 Source, N 22 Gate connection N 23 Grid and N 25 A drain electrode; n (N) 23 The source electrode is grounded; n (N) 24 Gate connection N 25 Drain, N 24 Drain electrode connection N 21 Grid and N 25 A gate; n (N) 25 Drain electrode connection N 22 A gate; r is R 1 In series with N 17 Drain and P 12 The source electrodes are arranged between the source electrodes; r is R 2 In series with N 16 Grid and N 17 The grid electrodes are arranged between the grid electrodes; capacitor C 1 The negative electrode is grounded, the capacitor C 1 Positive electrode connection P 12 And a gate.
OP c To compensate for the op-amp, it is not in the LDO main loop. OP (optical path) c The circuit is of a two-stage operational amplifier structure, the first-stage circuit structure is of an AB type symmetrical operational amplifier, and a pair of cross-coupled MOS transistors N with proper size (W/L) is designed through alternating current and transient simulation 24 And N 25 The second stage is R 1 And N 17 Is included in the common source amplifier of (a). OP (optical path) c The function of (2) is to dynamically adjust N along with load change when load suddenly changes 1 Grid voltage control adjusting tube N 0 Gate terminal charge-discharge speed.
Sampling operational amplifier OP b Comprises a PMOS tube P 18 PMOS tube P 19 PMOS tube P 20 PMOS tube P 21 NMOS tube N 10 NMOS tube N 11 NMOS tube N 14 NMOS tube N 15 NMOS tube N 18 NMOS tube N 19 ；P 18 The source is connected with a power supply voltage V DD 、P 18 Drain electrode connection N 10 Drain electrode, P 18 Gate connection P 19 Grid electrode P 18 Gate connection P 18 A drain electrode; p (P) 19 The source is connected with a power supply voltage V DD ，P 19 Drain electrode connection P 20 Source electrode and P 21 A source electrode; p (P) 20 Drain electrode connection N 18 Drain electrode, P 20 Gate connection P 16 Grid and N 14 A drain electrode; p (P) 21 Drain electrode connection N 14 Grid and N 19 Drain electrode, P 21 Gate connection P 17 Gate and output voltage V out ；N 10 Source electrode is grounded, N 10 Gate connection N 1 Source electrode and N 11 A gate; n (N) 11 Source electrode is grounded, N 11 Gate connection N 12 Grid electrode, N 11 Drain electrode connection N 14 Source electrode and N 14 A gate; n (N) 14 Gate connection P 19 Drain and N 19 Drain, N 14 Drain electrode connection N 15 Source electrode and P 16 A gate; n (N) 15 Gate connection P 24 Drain and N 0 Grid electrode, N 15 The drain electrode is connected with the power supply voltage V DD ；N 18 Source electrode is grounded, N 18 Drain electrode connection P 20 Drain, N 18 Gate connection N 19 Grid electrode, N 18 Grid and N 18 The drain electrode is connected; n (N) 19 Source electrode is grounded, N 19 Drain electrode connection N 14 Grid electrode and P 21 And a drain electrode.
OP b For sampling op-amp, not in the LDO main loop. The circuit structure is a two-stage operational amplifier. OP (optical path) b The function of (2) is mainly to clamp P by means of high gain characteristic of two-stage operational amplifier 20 And P 21 Is transferred to OP c Is connected to the inverting input terminal P of (1) 16 。
From OP b And OP (optical path) c The novel slew rate enhancement module can improve transient response. OP when load mutation occurs b Transfer of the undershoot or undershoot to the OP c ，OP c The overshoot or undershoot caused by the abrupt load change is rapidly compensated. When the load end suddenly changes from heavy load to light load to cause the up-rush, the OP c P of (2) 16 Gate end sampling OP b Output voltage, OP of (a) c P of (2) 17 Sampling the voltage of the output end of the LDO, and OP in the process of up-flushing c The output voltage of the first stage is suddenly increased and used as the second stage N 17 Is biased by the gate terminal of N 17 Branch current suddenly increases and branches to power tube N 0 The charging current at the gate end pulls down the gate voltage of the power tube, thereby reducingV of power tube GS Thus, the output branch current is reduced, and the up-cancellation is realized. When the load end suddenly changes from light load to heavy load to cause undershoot, OP c Is sampled OP at the inverting input of (1) b Output voltage, OP of (a) c The in-phase input end of the second-stage amplifier samples the voltage of the output end, so that the output voltage of the first-stage amplifier is suddenly reduced and is used as the grid voltage of the input tube of the second-stage amplifier, so that the current of the second-stage amplifier circuit suddenly drops, and flows to the grid end of the power tube to charge the equivalent capacitance of the grid oxide layer, thereby raising the grid voltage of the power tube and raising the V of the power tube GS Thereby raising the output current and realizing undershoot compensation.
Example 2
Based on the embodiment 2, please refer to fig. 2-3 of the specification.
The LDO main circuit also comprises a first protector, wherein the first protector is composed of a diode D 1 And NMOS tube N 13 Constructing; d (D) 1 Positive electrode connection N 0 Grid electrode D 1 Negative electrode connection N 13 A drain electrode; n (N) 13 Gate connection N 11 Drain, N 13 The source is grounded.
OP b N of the second stage of (2) 11 Is biased in the linear region, N when LDO is normal 11 The voltage of the drain terminal is very small and the post-stage N 13 And D 1 Form a current-limiting protection circuit, when N 15 Or N 14 The grid voltage of the LDO is rapidly increased due to the abnormal work of the LDO or the abnormal power supply voltage, so that N 11 The drain voltage of (a) rises to N 13 V of (2) TH After turn on N 13 And D 1 The path is used for discharging the LDO, thereby protecting the LDO.
Example 3
Based on the embodiment 2, please refer to fig. 2-4 of the specification.
The LDO main circuit also comprises a second protector, which consists of a resistor R 4 And N 15 Constitution, resistance R 4 Connected in series with the power supply voltage V DD And N 15 Between the sources.
OP b N of (2) 15 And a resistance R of 140KΩ 4 Parallel connection can reduce N 15 The output impedance of the output terminal is set,pushing the pole to high frequency without compensating OP b 。
Experimental example 1
On the basis of example 3, please refer to fig. 1-12 of the specification.
The simulation and verification section of the present utility model is as follows.
The utility model is realized based on Hua Hong nm CMOS technology, full-load full-process angle (TT, SS, SF, FF, FS, MC) simulation is carried out through Cadence spectrum software, T refers to Typical, F refers to Fast, and S refers to Slow. TT, SS, SF, FF, FS the drive current speed of NMOS and PMOS, respectively. The IC design takes the simulation result of the TT process angle as a main reference standard, MC is the Monte Carlo process angle, and the simulation curve is consistent with the TT. The simulation environment is provided with a power supply voltage of 5V, an ambient temperature of 25 ℃, a band gap reference voltage of 1.21V, a no-load capacitor and a load current range of 100 mu A-500mA.
Fig. 5 is a graph of the load transient response of the output of the present utility model, 5 (a) being a current load current graph, 5 (b) being a current output voltage graph; the TT process angle temperature is set to 25 ℃ in a simulation mode, the input voltage is 5V, the output voltage is 2.8V when the output voltage is stable, and the load current is switched between light load and heavy load within 1 mu s. The maximum and minimum values of the instantaneous output voltage are 2.81916V and 2.74359V respectively, at the moment, the instantaneous upper-punch and lower-punch voltage values of the load are 19.16mV and 56.41mV respectively, the response time is 0.1 mu s and 0.2 mu s respectively, and the voltage stabilizing error delta V 2 Only 0.9mV.
FIG. 6 is the same simulation environment setup as FIG. 5, FIG. 6 is a graph of transient response at full process angle, FIG. 6 (a) is a current load current graph, and FIG. 6 (b) is a current output voltage graph; as shown in FIG. 6, the best load jump effect is TT and MC process angles under the full process angle, the worst load jump effect is SF process angle, the maximum and minimum values of the output voltage of the SF process angle are 2.85131V and 2.72003V respectively, and the maximum upper punch and lower punch voltage values of the SF process angle are 51.31mV and 79.97mV respectively.
FIG. 7 is the same simulation environment setup as FIG. 5, FIG. 7 is a graph of amplitude-frequency characteristic simulation at full process angle, 7 (a) is a loop gain graph, and 7 (b) is a phase margin graph; according to 7, the low-frequency loop gain of 67dB is achieved under the TT process angle, the phase margin of the unit gain (0 dB) is 61 degrees, and the unit gain bandwidth product (GBW) is 60mHz; the low frequency has a loop gain of 47dB, a unity gain (0 dB) phase margin of 92 DEG, and a unity gain bandwidth product (GBW) of 60mHz at the SS process angle. The simulation curve of fig. 7 proves that the utility model has a loop gain of 47dB to 70dB and a phase margin of 57 deg. to 71 deg. under the full process angle, and can ensure that small signal oscillation does not occur in the loop stable output during the slow power-up or transient response of TRAN. And the loop gain does not have a tendency to drop significantly at the frequency of 10kHz, so the utility model can work at higher frequencies.
FIG. 8 is the same as FIG. 5 in the simulation environment, FIG. 8 is a graph of amplitude-frequency characteristic simulation under full load, 8 (a) is a loop gain graph, and 8 (b) is a phase margin graph; the load current of the output end is respectively simulated in the amplitude-frequency characteristics of the full load range at 0mA, 125mA, 250mA, 375mA and 500mA. As can be seen from fig. 8, the loop gain is 67dB, the phase margin is 65 °, and GBW is 60mHz at the load current of 0 mA; the loop gain was 56dB, the phase margin was 90℃and GBW was 60mHz at a load current of 500mA. The loop gain of the present utility model drops only 11dB at maximum in the no load to heavy load range and has sufficient bit margin. When the load becomes large, the equivalent impedance of the output end is reduced so as to be P 3 The pole moves to high frequency; n (N) 0 The gate voltage of (1) rises by P 2 Node equivalent impedance decreases so P 2 The pole moves to high frequency; p (P) 1 Pole P due to isolation of super source follower 1 The pole is not changed so much that the pole moves slowly to high frequency with a trend away from the origin; therefore, the phase margin of the present utility model increases with increasing load, and the phase margin is the lowest when no load is present and the phase margin is the highest when heavy load is present.
FIG. 9 is a simulation environment setting identical to FIG. 5 and a load current of 50mA, and FIG. 9 is a simulation graph of a full process corner power supply rejection ratio of 50mA for the load current of the present utility model; as shown in fig. 9, the power supply rejection ratio is greater than 74dB at the 10kHz frequency. The power supply has the best voltage ripple and noise suppression capability under the TT process angle, and the power supply suppression ratio is 108dB, 96dB and 80dB respectively at 10Hz, 1kHz and 10kHz frequencies; the worst voltage ripple and noise suppression effect is the FF process corner, and the power supply suppression ratio is 74dB at 10Hz, 1kHz and 10kHz frequencies.
FIG. 10 is a simulation graph showing the TT process angle and the load adjustment rate in the full temperature range according to the present utility model, wherein the simulation environment is the same as that of FIG. 5, and the simulation graph is shown in FIG. 10 (a), in which the maximum load current of the present utility model is V at 500mA MAX And V MIN 2.80058V and 2.799105V, respectively, so the load adjustment rate is 0.00295 V.A -1 . As can be seen from 10 (b), the load adjustment rate at-40℃to 150℃ Quan Wenpiao, and FIG. 10 shows that the load adjustment rate becomes worse with increasing temperature, and that the LDR is preferably 0.000738 V.A at-40 ℃ -1 The worst LDR is 0.0971 V.A at 150 DEG C -1 。
Fig. 11 is a simulation environment setting identical to fig. 5, and fig. 11 is a novel full process angle and full load range Tran slow power-up simulation graph of the present utility model, wherein Tran slow power-up simulates a power-up process of non-ideal power supply in LDO practice. 11 And (a) is a Tran slow power-on simulation graph under the full process angle, and 11 (a) shows that when the regulated output is 2.8V, the time consumed by the LDO to enter the normal regulated state is within 1 mu s, and the power-on error voltage DeltaVmax under the full process angle is 0.5mV.11 And (b) is a simulation graph of Tran slow power-up under 0mV,125mV,250mV,375mV and 500mA of load current, and 11 (b) shows that when the regulated output is 2.8V, the time consumed by the LDO to enter the normal regulated state is also within 1 mu s, and the power-up error voltage DeltaVmax under the full load is 0.9mV.
Fig. 12 is a graph imitating the TT process angle transient response of the present utility model, where 12 (a) is a current load current graph, and 12 (b) is a current output voltage graph, and the simulation environment setting is the same as that of fig. 5. As can be seen from FIG. 12, the post-imitation upper punch and lower punch voltages were 2.82412V and 2.741111V, respectively, which were 4.96mV and 2.48mV worse than the prior-imitation upper punch and lower punch voltages, respectively. The response times of the undershoot and the undershoot are 0.6 and 0.3 μs respectively, and the response times are respectively poorer by 0.2 and 0.1 μs than the previous imitation response times. The voltage stabilizing error voltage DeltaV is 1.1mV when the load is light and heavy, and is 0.2mV worse than the previous error simulating voltage.
The above embodiments are only for illustrating the technical solution of the present utility model, and are not limiting; although the utility model has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present utility model.
Claims (10)
1. The utility model provides a car rule level LIN bus high transient response LDO, includes LDO main loop, its characterized in that: NMOS regulating tube N is arranged on the LDO main loop 0 OP of main loop operational amplifier a Novel slew rate enhancement module, protection module, super source follower and feedback resistor R FB ，N 0 Electrically connected OP a Novel slew rate enhancement module, protection module and R FB ；OP a The novel slew rate enhancement module and the super source follower are electrically connected; the protection module is electrically connected with the novel slew rate enhancement module and the super source follower.
2. The vehicle-standard LIN bus high-transient-response LDO of claim 1, wherein the novel slew-rate enhancement module comprises a sampling OP-amp b Compensation OP c ，OP b Electric connection protection module, OP c 、N 0 And a super source follower; OP (optical path) c Electrically connected OP a Super source follower and N 0 。
3. The vehicle-standard LIN bus high transient response LDO of claim 2, further comprising a resistor R 3 Current source I PTAT PMOS tube P 1 PMOS tube P 2 PMOS tube P 6 PMOS tube P 7 NMOS tube N 1 NMOS tube N 3 And NMOS tube N 12 ；N 0 The drain electrode is connected with the power supply voltage V DD ，N 0 Source electrode connection R FB ，N 0 Gate connection OP b 、OP c And a super source follower; output voltage V out From N 0 A source electrode; r is R FB In series with N 0 Between the source and the ground terminal, V FB Is R FB For output voltage V out Is a partial pressure of (2); p (P) 1 The source is connected to a supply voltage V DD ，P 1 Gate connection to P 2 Grid electrode P 1 Drain connected to P 6 Source electrode, P 1 Gate connection to P 1 A drain electrode; p (P) 2 The source is connected to a supply voltage V DD ，P 2 Drain connected to P 7 Source electrode, P 2 The gate is connected to OP a ；P 6 Gate connection to P 7 Grid electrode P 6 Drain electrode is connected with a current source I PTAT Positive electrode, P 6 Gate connection P 6 A drain electrode; p (P) 7 Drain electrode connection N 1 Drain electrode, P 7 Gate connection OP a ；N 1 Gate connection OP a ，N 1 Source electrode connection N 3 Drain, N 1 Gate connection N 1 A drain electrode; n (N) 3 Source electrode is grounded, N 3 Gate connection OP a The method comprises the steps of carrying out a first treatment on the surface of the Current source I PTAT The negative electrode is grounded; n (N) 12 Source electrode is grounded, N 12 Gate connection OP b 、N 12 Drain connecting resistor R 3 Resistance R 3 In series with N 0 Source electrode and N 12 Between the drains.
4. A vehicle-mounted LIN bus high transient response LDO as recited in claim 3, wherein the main loop OP is an OP a Comprises a PMOS tube P 3 PMOS tube P 4 PMOS tube P 5 PMOS tube P 8 PMOS tube P 9 PMOS tube P 10 PMOS tube P 11 PMOS tube P 22 PMOS tube P 23 NMOS tube N 2 NMOS tube N 4 NMOS tube N 5 NMOS tube N 6 NMOS tube N 7 And NMOS tube N 8 ；P 3 Source electrode is connected with a power supply V DD ，P 3 Drain connected to P 5 Source electrode and P 4 Grid electrode P 3 Gate connection P 10 Grid electrode and P 2 A gate; p (P) 4 The source is connected to a supply voltage V DD ，P 4 Drain connected to P 8 Source electrode and P 9 Source electrode and P 5 A gate; p (P) 5 Drain is connected to N 2 Drain electrode；P 8 Drain electrode connection N 6 Drain electrode, P 8 Source connection P 9 Source electrode, P 8 The grid electrode is connected with a reference voltage V REF ；P 9 Drain electrode connection P 22 Drain electrode, P 9 The grid electrode is connected with a feedback resistor R FB For output voltage V out Is of the partial pressure V of FB ；P 10 The source is connected with a power supply voltage V DD ，P 10 Gate connection P 11 Grid electrode P 10 Drain electrode connection P 22 A source electrode; p (P) 11 The source is connected with a power supply voltage V DD ，P 11 Drain electrode connection P 23 Source electrode, P 11 The grid electrode is connected with the super source follower; p (P) 22 Gate connection P 7 Grid electrode and P 23 Grid electrode P 22 Drain electrode connection N 5 A drain electrode; p (P) 23 Drain electrode connection N 6 Drain and super source follower; n (N) 2 Gate connection N 1 Grid and N 5 Grid electrode, N 2 Source electrode connection N 4 A drain electrode; n (N) 4 Gate connection N 3 Grid electrode, N 4 The source electrode is connected with the ground; n (N) 5 Source electrode connection N 7 Drain, N 5 Gate connection N 6 Grid electrode, N 5 Drain electrode connection N 7 A gate; n (N) 6 Source electrode connection N 8 Drain, N 6 The grid electrode is connected with the super source follower; n (N) 7 Gate connection N 8 Grid electrode, N 7 The source electrode is grounded; n (N) 8 The source is grounded.
5. The vehicle-mounted LIN bus high transient response LDO of claim 4, wherein said super source follower comprises a PMOS tube P 12 PMOS tube P 24 NMOS tube N 9 And NMOS tube N 19 ；P 12 Gate connection P 23 Drain electrode, P 12 Drain electrode connection N 19 Drain electrode, P 12 Source connection P 24 Drain, N 12 Drain, OP c 、OP b And N 0 A gate electrode of (a); p (P) 24 The source is connected with a power supply voltage V DD ，P 24 Gate connection P 11 Grid and OP c ；N 9 Gate connection P 12 Drain, N 9 Source electrode is grounded, N 9 Drain electrode connection P 12 A source electrode; n (N) 19 Gate connection N 6 Grid electrode, N 19 Source electrode is grounded, N 19 Drain electrode connection N 9 And a gate.
6. The vehicle-mounted LIN bus high transient response LDO of claim 5, wherein the compensating OP-amp is configured to c Comprises a compensation capacitor C 1 PMOS tube P 13 PMOS tube P 14 PMOS tube P 15 PMOS tube P 16 PMOS tube P 17 NMOS tube N 16 NMOS tube N 17 NMOS tube N 20 NMOS tube N 21 NMOS tube N 22 NMOS tube N 23 NMOS tube N 24 NMOS tube N 25 Resistance R 1 And resistance R 2 ；P 13 The source is connected with a power supply voltage V DD ，P 13 Gate connection P 15 Grid electrode P 13 Drain electrode connection N 20 Drain electrode, P 13 Drain electrode connection P 13 A gate; p (P) 14 The source is connected with a power supply voltage V DD ，P 14 Gate connection P 24 Grid electrode P 14 Drain electrode connection P 16 Source electrode and P 17 A source electrode; p (P) 15 The source is connected with a power supply voltage V DD 、P 15 Drain electrode connection N 23 A drain electrode; p (P) 16 Drain electrode connection N 23 Drain and N 25 Grid electrode P 16 Gate connection OP b ；P 17 Drain electrode connection N 25 Drain and N 24 Grid electrode P 17 The grid electrode is connected with the output voltage V out ；N 16 Source electrode is grounded, N 16 Gate connection R 2 ，N 16 Drain electrode connection P 15 Drain and N 17 A gate; n (N) 17 Source electrode is grounded, N 17 Grid connection resistor R 2 And N 16 Drain, N 17 Drain connecting resistor R 1 ；N 20 Source electrode is grounded, N 20 Gate connection N 21 Grid electrode and P 16 A drain electrode; n (N) 21 Source electrode is grounded, N 21 Drain electrode connection N 24 A source electrode; n (N) 22 Source electrode is grounded, N 22 Drain electrode connection N 25 Source, N 22 Grid electrodeConnection N 23 Grid and N 25 A drain electrode; n (N) 23 The source electrode is grounded; n (N) 24 Gate connection N 25 Drain, N 24 Drain electrode connection N 21 Grid and N 25 A gate; n (N) 25 Drain electrode connection N 22 A gate; r is R 1 In series with N 17 Drain and P 12 The source electrodes are arranged between the source electrodes; r is R 2 In series with N 16 Grid and N 17 The grid electrodes are arranged between the grid electrodes; c (C) 1 The negative electrode is grounded, C 1 Positive electrode connection P 12 And a gate.
7. The vehicle-mounted LIN bus high transient response LDO of claim 5, wherein the sampling OP-amp is configured to sample the operating amplifier OP b Comprises a PMOS tube P 18 PMOS tube P 19 PMOS tube P 20 PMOS tube P 21 NMOS tube N 10 NMOS tube N 11 NMOS tube N 14 NMOS tube N 15 NMOS tube N 18 NMOS tube N 19 ；P 18 The source is connected with a power supply voltage V DD 、P 18 Drain electrode connection N 10 Drain electrode, P 18 Gate connection P 19 Grid electrode P 18 Gate connection P 18 A drain electrode; p (P) 19 The source is connected with a power supply voltage V DD ，P 19 Drain electrode connection P 20 Source electrode and P 21 A source electrode; p (P) 20 Drain electrode connection N 18 Drain electrode, P 20 Gate connection P 16 Grid and N 14 A drain electrode; p (P) 21 Drain electrode connection N 14 Grid and N 19 Drain electrode, P 21 Gate connection P 17 Gate and output voltage V out ；N 10 Source electrode is grounded, N 10 Gate connection N 1 Source electrode and N 11 A gate; n (N) 11 Source electrode is grounded, N 11 Gate connection N 12 Grid electrode, N 11 Drain electrode connection N 14 Source electrode and N 14 A gate; n (N) 14 Gate connection P 19 Drain and N 19 Drain, N 14 Drain electrode connection N 15 Source electrode and P 16 A gate; n (N) 15 Gate connection P 24 Drain and N 0 Grid electrode, N 15 The drain electrode is connected with the power supply voltage V DD ；N 18 Source electrode is grounded, N 18 Drain electrode connection P 20 Drain, N 18 Gate connection N 19 Grid electrode, N 18 Grid and N 18 The drain electrode is connected; n (N) 19 Source electrode is grounded, N 19 Drain electrode connection N 14 Grid electrode and P 21 And a drain electrode.
8. The vehicle-mounted LIN bus high transient response LDO of claim 7, wherein the protection module comprises a first protector and a second protector, the first protector being electrically connected to N 0 、OP b 、OP c And a super source follower; second protector electric connection first protector N 0 、OP b 、OP c And a super source follower.
9. The vehicle-specific LIN bus high transient response LDO of claim 8, wherein said protector one is a diode D 1 And NMOS tube N 13 Constructing; d (D) 1 Positive electrode connection N 0 Grid electrode D 1 Negative electrode connection N 13 A drain electrode; n (N) 13 Gate connection N 11 Drain, N 13 The source is grounded.
10. The vehicle-mounted LIN bus high transient response LDO of claim 8, wherein said second protector consists of N 15 And resistance R 4 Constructing; resistor R 4 Connected in series with the power supply voltage V DD And N 15 Between the sources.
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