CN114756083A - Low-dropout linear voltage stabilizing circuit and electronic equipment - Google Patents
Low-dropout linear voltage stabilizing circuit and electronic equipment Download PDFInfo
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- CN114756083A CN114756083A CN202210339416.0A CN202210339416A CN114756083A CN 114756083 A CN114756083 A CN 114756083A CN 202210339416 A CN202210339416 A CN 202210339416A CN 114756083 A CN114756083 A CN 114756083A
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Abstract
The application provides a low dropout linear voltage stabilizing circuit and an electronic device, wherein the circuit comprises a feedback unit and a transient response unit, the feedback unit comprises a power transistor and a load module, the power transistor is electrically connected with the load module, and the feedback unit adjusts the output voltage of the feedback unit by adjusting the current flowing through the power transistor; the output end of the transient response unit is electrically connected with the power transistor, when the current of the load module jumps in a step mode, the voltage of the power transistor changes, and the transient response unit adjusts the output voltage of the feedback unit under the condition that the voltage of the power transistor changes, so that the problem that the overshoot or undershoot voltage of the low-dropout linear voltage regulator in the prior art is overlarge is solved, the transient response characteristic of the low-dropout linear voltage regulator circuit is effectively improved, the overshoot or undershoot of the output voltage caused by sudden change of the load or sudden change of the power supply voltage is reduced, and the output voltage is kept stable.
Description
Technical Field
The application relates to the technical field of low dropout linear regulators, in particular to a low dropout linear voltage regulator circuit and an electronic device.
Background
The low dropout linear regulator utilizes an error amplifier and a negative feedback loop in a system to regulate the sampling voltage of a sampling network to be equal to a reference voltage, thereby realizing a circuit which forms a certain multiple of output voltage with the reference voltage. The power supply has the advantages of low cost, simple circuit structure, no inductance, on-chip integration, no switching noise, good power supply ripple suppression effect, conversion efficiency irrelevant to load and extremely low static power consumption. Although the low dropout regulator has the defects of only realizing voltage reduction, large dropout and low efficiency, the low dropout regulator is very suitable for some integrated circuits sensitive to noise due to the good performances of simple circuit structure, low power consumption, no need of inductors and the like, and the low dropout regulator is widely applied to portable electronic products due to the small area and low cost and becomes the first choice for application of various products.
In the circuit operation, when the magnitude of the power supply voltage or the load current of the low dropout linear regulator suddenly generates a step jump, the output voltage cannot be changed as quickly as the load current due to the limitation of the product of the slew rate and the gain bandwidth, and relatively, the output voltage is delayed, so that overshoot and undershoot voltages can occur in the circuit. If the overshoot or undershoot voltage is too large, the circuit may be severely affected. If the output of the low dropout regulator is used as a power supply of an analog circuit, the working state of a transistor can be influenced, and the precision of the analog circuit is reduced. If the LDO is used as a power supply for a digital circuit, an output logic error may be caused. It is therefore important to reduce overshoot or undershoot due to load or supply voltage transients.
Disclosure of Invention
The present application provides a low dropout linear voltage regulator and an electronic device, so as to solve the problem of excessive overshoot or undershoot voltage of the low dropout linear voltage regulator in the prior art.
In order to achieve the above object, according to one aspect of the present application, there is provided a low dropout linear voltage regulating circuit, the circuit including: the transient response control circuit comprises a feedback unit and a transient response unit, wherein the feedback unit comprises a power transistor and a load module, the power transistor is electrically connected with the load module, and the feedback unit regulates the output voltage of the feedback unit by regulating the current flowing through the power transistor; the output end of the transient response unit is electrically connected with the power transistor, when the current of the load module generates step jump, the voltage of the power transistor changes, and the transient response unit adjusts the output voltage of the feedback unit under the condition that the voltage of the power transistor changes.
Furthermore, the feedback unit further comprises a first feedback resistor and a second feedback resistor, wherein a first end of the first feedback resistor is electrically connected with an output end of the feedback unit and a source electrode of the power transistor respectively, and a first end of the second feedback resistor is grounded; the circuit further comprises a reference voltage generation module and an amplifier, wherein the reference voltage generation module is used for providing a reference voltage; the amplifier is provided with a first input end, a second input end and an output end, the first input end of the amplifier is electrically connected with the output end of the reference voltage generation module, the second input end of the amplifier is respectively electrically connected with the second end of the first feedback resistor and the second end of the second feedback resistor, and the output end of the amplifier is electrically connected with the input end of the transient response unit.
Further, the transient response unit comprises a parasitic capacitance module, a current amplification module and a driving module, wherein the parasitic capacitance module comprises a first end and a second end, the first end of the parasitic capacitance module is electrically connected with the gate of the power transistor, and the second end of the parasitic capacitance module is grounded; the current amplification module comprises an input end and an output end, and the input end of the current amplification module is electrically connected with the output end of the amplifier; the driving module comprises an input end and an output end, the input end of the driving module is electrically connected with the output end of the current amplification module, and the output end of the driving module is electrically connected with the first end of the parasitic capacitance module and used for driving the parasitic capacitance module.
Further, the current amplification module comprises a fifth amplification transistor, a first current mirror module, a second current mirror module and a third current mirror module, the first current mirror module is respectively electrically connected with the drain of the fifth amplification transistor and the second current mirror module, the second current mirror module is electrically connected with the third current mirror module, the grid of the fifth amplification transistor is electrically connected with a first voltage source, and the source of the fifth amplification transistor is grounded.
Further, the first current mirror module includes a first amplifying transistor, a second amplifying transistor, a third amplifying transistor and a fourth amplifying transistor, the first amplifying transistor and the second amplifying transistor are in mirror symmetry, the third amplifying transistor and the fourth amplifying transistor are in mirror symmetry, a source of the third amplifying transistor is electrically connected to a drain of the first amplifying transistor, a source of the fourth amplifying transistor is electrically connected to a drain of the second amplifying transistor, the source of the first amplifying transistor and the source of the second amplifying transistor are respectively electrically connected to a drain of the fifth amplifying transistor, a gate of the first amplifying transistor is electrically connected to an output terminal of the amplifier, a gate of the second amplifying transistor is grounded, and a drain of the first amplifying transistor is respectively connected to a source of the third amplifying transistor, The grid electrode of the third amplifying transistor is electrically connected with the input end of the driving module, the grid electrode of the fourth amplifying transistor is electrically connected with the drain electrode of the second amplifying transistor, the second current mirror module and the input end of the driving module respectively, and the drain electrode of the third amplifying transistor and the drain electrode of the fourth amplifying transistor are electrically connected with a second voltage source respectively.
Further, the second current mirror module includes a sixth amplifying transistor, a seventh amplifying transistor, an eighth amplifying transistor and a ninth amplifying transistor, the sixth amplifying transistor is mirror-symmetrical to the seventh amplifying transistor, the eighth amplifying transistor is mirror-symmetrical to the ninth amplifying transistor, a source of the sixth amplifying transistor is electrically connected to a drain of the eighth amplifying transistor, a source of the seventh amplifying transistor is electrically connected to a drain of the ninth amplifying transistor, a gate of the sixth amplifying transistor is electrically connected to the first current mirror module and the input terminal of the driving module, respectively, a gate of the seventh amplifying transistor is electrically connected to the input terminal of the driving module and the first current mirror module, respectively, and a gate of the eighth amplifying transistor is electrically connected to a gate of the ninth amplifying transistor, the source electrode of the eighth amplifying transistor is electrically connected with the third current mirror module, the source electrode of the ninth amplifying transistor is electrically connected with the output ends of the third current mirror module and the driving module respectively, and the drain electrode of the sixth amplifying transistor and the drain electrode of the seventh amplifying transistor are electrically connected with a second voltage source respectively.
Further, the third current mirror module includes a tenth amplifying transistor, an eleventh amplifying transistor, a twelfth amplifying transistor and a thirteenth amplifying transistor, the tenth amplifying transistor is mirror-symmetric to the eleventh amplifying transistor, the twelfth amplifying transistor is mirror-symmetric to the thirteenth amplifying transistor, a source of the tenth amplifying transistor is electrically connected to a drain of the twelfth amplifying transistor, a source of the eleventh amplifying transistor is electrically connected to a drain of the thirteenth amplifying transistor, a drain of the second current mirror module, a drain of the tenth amplifying transistor and a gate of the twelfth amplifying transistor are respectively electrically connected to a gate of the thirteenth amplifying transistor, and a gate of the tenth amplifying transistor is respectively electrically connected to a gate of the eleventh amplifying transistor and a third voltage source, a gate of the twelfth amplifying transistor is electrically connected to a gate of the thirteenth amplifying transistor, the second current mirror module and a drain of the tenth amplifying transistor, respectively, and a source of the twelfth amplifying transistor and a source of the thirteenth amplifying transistor are grounded, respectively.
Further, the driving module includes a fourth current mirror module, a first driving transistor, a second driving transistor, a third driving transistor, a fourth driving transistor, a fifth driving transistor, and a sixth driving transistor, the first driving transistor and the fourth amplifying transistor are in mirror symmetry, a source of the first driving transistor and a source of the second driving transistor are electrically connected to the fourth current mirror module, a gate of the first driving transistor is electrically connected to the first current mirror module and the second current mirror module, a gate of the third driving transistor is electrically connected to the first current mirror module and the second current mirror module, a source of the third driving transistor and a drain of the fourth driving transistor are electrically connected to a gate of the sixth driving transistor, and a source of the fifth driving transistor, The drain electrode of the sixth driving transistor, the second current mirror module and the third current mirror module are respectively electrically connected with the first end of the parasitic capacitance module, the gate electrode of the second driving transistor is electrically connected with a fourth voltage source, the fourth driving transistor is electrically connected with a fifth voltage source, the gate electrode of the fifth driving transistor is respectively electrically connected with the source electrode of the second driving transistor and the fourth current mirror module, the source electrode of the fourth driving transistor and the source electrode of the sixth driving transistor are respectively grounded, and the drain electrode of the first driving transistor, the drain electrode of the second driving transistor, the drain electrode of the third driving transistor and the drain electrode of the fifth driving transistor are respectively electrically connected with the second voltage source.
Further, the fourth current mirror module includes a seventh driving transistor and an eighth driving transistor, the seventh driving transistor and the eighth driving transistor are mirror-symmetric, a source of the first driving transistor, a drain of the seventh driving transistor, and a gate of the seventh driving transistor are electrically connected to a gate of the eighth driving transistor, respectively, a source of the second driving transistor and a gate of the fifth driving transistor are electrically connected to a drain of the eighth driving transistor, respectively, and a source of the seventh driving transistor and a source of the eighth driving transistor are grounded, respectively.
Further, the feedback unit further comprises a frequency compensation module, a drain of the power transistor is electrically connected to a sixth voltage source, and the frequency compensation module is electrically connected to a source of the power transistor.
Furthermore, the frequency compensation module includes a compensation capacitor and a compensation resistor, a first end of the compensation capacitor is electrically connected to a first end of the compensation resistor, a second end of the compensation capacitor is grounded, a second end of the compensation resistor is electrically connected to a source of the power transistor, a first end of the load module is electrically connected to the source of the power transistor, and a second end of the load module is grounded.
According to another aspect of the present application, there is provided an electronic device comprising the low dropout linear voltage regulator circuit of any one of the above.
By applying the technical scheme of the application, the power transistor is electrically connected with the load module, and the feedback unit adjusts the output voltage of the feedback unit by adjusting the current flowing through the power transistor; the output end of the transient response unit is electrically connected with the power transistor, when the current of the load module jumps in a step mode, the voltage of the power transistor changes, and the transient response unit adjusts the output voltage of the feedback unit under the condition that the voltage of the power transistor changes, so that the problem that the overshoot or undershoot voltage of the low-dropout linear voltage regulator in the prior art is overlarge is solved, the transient response characteristic of the low-dropout linear voltage regulator is effectively improved, the overshoot or undershoot of the output voltage caused by sudden load change or sudden power supply voltage change is reduced, and the output voltage is kept stable.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:
FIG. 1 illustrates a schematic diagram of a low dropout linear voltage regulator circuit according to an embodiment of the present application;
fig. 2 shows a schematic diagram of a transient response unit according to an embodiment of the application.
Wherein the figures include the following reference numerals:
10. a transient response unit; 101. a current amplification module; 1011. a first current mirror module; 1012. a second current mirror module; 1013. a third current mirror module; 102. a drive module; 1021. a fourth current mirror module; 20. a feedback unit; 201. a frequency compensation module; 30. a reference voltage generation module; 40. an amplifier.
Detailed Description
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the accompanying drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances in order to facilitate the description of the embodiments of the application herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As mentioned in the background art, when a sudden step occurs in the magnitude of the power supply voltage or the load current of the low dropout regulator, the output voltage cannot be changed as quickly as the load current due to the limitation of the product of the slew rate and the gain bandwidth, and the output voltage is relatively delayed, so that the circuit may generate overshoot and undershoot voltages. If the overshoot voltage or the undershoot voltage is too large, the circuit is seriously influenced; in order to solve the problem of overlarge overshoot voltage or undershoot voltage of the low-dropout linear voltage regulator in the prior art, a low-dropout linear voltage regulator circuit and electronic equipment are provided.
According to the embodiment of the application, a low dropout linear voltage regulator circuit and an electronic device are provided.
FIG. 1 is a schematic diagram of a low dropout linear voltage regulating circuit according to an embodiment of the present application. As shown in fig. 1, the circuit includes: a transient response unit 10 and a feedback unit 20;
the feedback unit 20 includes a power transistor M and a load module RLThe power transistor M and the load module RLElectrically connected, said feedback unit 20 flowing through by regulationA current of the power transistor M to adjust an output voltage of the feedback unit 20 (specifically, the power transistor M is a P-type transistor); an output terminal of the transient response unit 10 is electrically connected to the power transistor M, and the load module R LWhen the current of (3) changes in a step-like manner, the voltage of the power transistor M changes, and the transient response means 10 adjusts the output voltage of the feedback means 20 when the voltage of the power transistor M changes. The circuit solves the problem that the overshoot or undershoot voltage of the low dropout linear voltage regulator is overlarge, effectively improves the transient response characteristic of the low dropout linear voltage regulator circuit, reduces the overshoot or undershoot of the output voltage caused by sudden change of load or sudden change of power voltage, and ensures the stability of the output voltage.
In an embodiment of the present application, as shown in fig. 1, the feedback unit 20 further includes a first feedback resistor R1 and a second feedback resistor R2, a first end of the first feedback resistor R1 is electrically connected to the output terminal of the feedback unit 20 and the source of the power transistor M, respectively, and a first end of the second feedback resistor R2 is grounded; the circuit further comprises a reference voltage generating module 30 and an amplifier 40 (the amplifier is an error amplifier), wherein the reference voltage generating module 30 is used for providing a reference voltage; the amplifier 40 has a first input terminal, a second input terminal, and an output terminal, the first input terminal of the amplifier 40 is electrically connected to the output terminal of the reference voltage generating module 30, the second input terminal of the amplifier 40 is electrically connected to the second terminal of the first feedback resistor R1 and the second terminal of the second feedback resistor R2, respectively, and the output terminal of the amplifier 40 is electrically connected to the input terminal of the transient response unit 10. Sampling the output voltage of the circuit to obtain a feedback voltage V fb＝Vout·R2/(R1+R2) The feedback voltage is compared with the reference voltage generated by the reference voltage generating module 30, and after passing through the amplifier, the amplifier amplifies the voltage difference of the two signals and transmits the voltage difference to the gate of the power transistor M, and then the stable output of the low-dropout linear voltage regulator circuit is ensured by adjusting the current flowing through the power transistor M.VrefIs the output voltage, V, of the reference voltage generation module 30fbIs the voltage at the intermediate node between the second terminal of the first feedback resistor R1 and the second feedback resistor R2;
Vref＝Vfb；
the working process of the feedback system is as follows: when the output voltage V of the circuit isoutWhen rising, VfbRises while VrefThe output voltage of the amplifier is kept constant, the gate-source voltage of the power transistor M is reduced, the current flowing through the power transistor M is reduced, and V is reducedoutTo reach the output voltage V of the low dropout linear voltage stabilizing circuitoutAchieving the purpose of stability. If VoutThe opposite is true when increasing.
When the circuit normally works in a light load state, the adjusting tube works in a saturation region, and when the external load changes, the circuit can change the grid voltage of the adjusting tube through an internal feedback loop, so that the output voltage is stabilized on the expected output. When the circuit load is infinite, i.e. no load current flows through the regulating tube, it operates in a subthreshold state, and only generates a current flowing through the voltage-dividing resistor.
In an embodiment of the present application, fig. 2 is a schematic diagram of a transient response unit according to an embodiment of the present application, and as shown in fig. 1 and 2, the transient response unit 10 includes a parasitic capacitance module CLThe parasitic capacitance module comprises a first end and a second end, the first end of the parasitic capacitance module is electrically connected with the grid electrode of the power transistor M, and the second end of the parasitic capacitance module is grounded; the current amplifying module 101 includes an input terminal and an output terminal, and the current amplifierThe input end of the large module 101 is electrically connected with the output end of the amplifier 40; the driving module 102 includes an input terminal and an output terminal, the input terminal of the driving module 102 is electrically connected to the output terminal of the current amplifying module 101, the output terminal of the driving module 102 is electrically connected to the first terminal of the parasitic capacitor module for driving the parasitic capacitor module, and the parasitic capacitor module may be a parasitic capacitor CL. The current amplifying module 101 is for amplifying, and the driving module 102 is for driving the parasitic capacitance module CLThe parasitic capacitance module CLBy discharging, the gate voltage of the power transistor M is rapidly reduced, and the parasitic capacitance module C LThe gate voltage of the power transistor M is rapidly increased by the charging.
In one embodiment of the present invention, as shown in fig. 2, the current amplification module 101 includes a fifth amplification transistor M5, a first current mirror module 1011, a second current mirror module 1012, and a third current mirror module 1013, the first current mirror module 1011 is electrically connected to the drain of the fifth amplification transistor M5 and the second current mirror module 1012, the second current mirror module 1012 is electrically connected to the third current mirror module 1013, the gate of the fifth amplification transistor M5 is electrically connected to a first voltage source Vb1, the source of the fifth amplification transistor M5 is grounded, and the first current mirror module 1011, the second current mirror module 1012, and the third current mirror module 1013 all function as an amplification.
In one embodiment of the present invention, as shown in fig. 2, the first current mirror module 1011 includes a first amplifying transistor M1, a second amplifying transistor M2, a third amplifying transistor M3 and a fourth amplifying transistor M4, the first amplifying transistor M1 is mirror-symmetrical to the second amplifying transistor M2, the third amplifying transistor M3 is mirror-symmetrical to the fourth amplifying transistor M4, the source of the third amplifying transistor M3 is electrically connected to the drain of the first amplifying transistor M1, the source of the fourth amplifying transistor M4 is electrically connected to the drain of the second amplifying transistor M2, the source of the first amplifying transistor M1 and the source of the second amplifying transistor M2 are electrically connected to the drain of the fifth amplifying transistor M5, the gate of the first amplifying transistor M1 is electrically connected to the output terminal of the amplifier 40, and the gate of the second amplifying transistor M2 is grounded, a drain of the first amplifying transistor M1 is electrically connected to a source of the third amplifying transistor M3, a gate of the third amplifying transistor M3 and an input terminal of the driving module 102, a gate of the fourth amplifying transistor M4 is electrically connected to a drain of the second amplifying transistor M2, an input terminal of the second current mirror module 1012 and the driving module 102, and a drain of the third amplifying transistor M3 and a drain of the fourth amplifying transistor M4 are electrically connected to a second voltage source; the third amplifying transistor M3 and the fourth amplifying transistor M4 are both P-type transistors, the first amplifying transistor M1, the second amplifying transistor M2 and the fifth amplifying transistor M5 are all N-type transistors, and the first amplifying transistor M1, the second amplifying transistor M2, the third amplifying transistor M3 and the fourth amplifying transistor M4 all perform an amplifying function.
In one embodiment of the present invention, as shown in fig. 2, the second current mirror module 1012 includes a sixth amplifying transistor M6, a seventh amplifying transistor M7, an eighth amplifying transistor M8 and a ninth amplifying transistor M9, the sixth amplifying transistor M6 is mirror-symmetrical to the seventh amplifying transistor M7, the eighth amplifying transistor M8 is mirror-symmetrical to the ninth amplifying transistor M9, a source of the sixth amplifying transistor M6 is electrically connected to a drain of the eighth amplifying transistor M8, a source of the seventh amplifying transistor M7 is electrically connected to a drain of the ninth amplifying transistor M9, a gate of the sixth amplifying transistor M6 is electrically connected to the first current mirror module 1011 and an input terminal of the driving module 102, respectively, a gate of the seventh amplifying transistor M7 is electrically connected to an input terminal of the driving module 102 and the first current mirror module 1011, a gate of the eighth amplifying transistor M8 is electrically connected to a gate of the ninth amplifying transistor M9, a source of the eighth amplifying transistor M8 is electrically connected to the third current mirror module 1013, a source of the ninth amplifying transistor M9 is electrically connected to the third current mirror module 1013 and an output terminal of the driving module 102, a drain of the sixth amplifying transistor M6 and a drain of the seventh amplifying transistor M7 are electrically connected to a second voltage source, and the sixth amplifying transistor M6, the seventh amplifying transistor M7, the eighth amplifying transistor M8 and the ninth amplifying transistor M9 form a cascode input pair transistor as a part of an amplifier;
A gate of the sixth amplifying transistor M6 is electrically connected to a gate of the fourth amplifying transistor M4, a source of the fourth amplifying transistor M4 and an input terminal of the driving block 102, a gate of the seventh amplifying transistor M7 is electrically connected to an input terminal of the driving block 102, a source of the third amplifying transistor M3 and a gate of the third amplifying transistor M3, and the sixth amplifying transistor M6, the seventh amplifying transistor M7, the eighth amplifying transistor M8 and the ninth amplifying transistor M9 are P-type transistors.
In one embodiment of the present invention, as shown in fig. 2, the third current mirror module 1013 includes a tenth amplification transistor M10, an eleventh amplification transistor M11, a twelfth amplification transistor M12 and a thirteenth amplification transistor M13, the tenth amplification transistor M10 is mirror-symmetrical to the eleventh amplification transistor M11, the twelfth amplification transistor M12 is mirror-symmetrical to the thirteenth amplification transistor M13, a source of the tenth amplification transistor M10 is electrically connected to a drain of the twelfth amplification transistor M12, a source of the eleventh amplification transistor M11 is electrically connected to a drain 1012 of the thirteenth amplification transistor M13, drains of the second current mirror module, the tenth amplification transistor M10 and a gate of the twelfth amplification transistor M12 are electrically connected to gates of the thirteenth amplification transistors M13, gates of the tenth amplification transistors M10 are electrically connected to an eleventh voltage source M6335 and a third voltage source 2 of the eleventh amplification transistor M11, a gate of the twelfth amplifying transistor M12 is electrically connected to a gate of the thirteenth amplifying transistor M13, a drain of the second current mirror module 1012 and a drain of the tenth amplifying transistor M10, respectively, and a source of the twelfth amplifying transistor M12 and a source of the thirteenth amplifying transistor M13 are grounded, respectively;
A source of the eighth amplifying transistor M8, a drain of the tenth amplifying transistor M10, and a gate of the twelfth amplifying transistor M12 are electrically connected to a gate of the thirteenth amplifying transistor M13, a gate of the twelfth amplifying transistor M12 is electrically connected to a gate of the thirteenth amplifying transistor M13, a source of the eighth amplifying transistor M8, and a drain of the tenth amplifying transistor M10, respectively, the tenth amplifying transistor M10, the eleventh amplifying transistor M11, the twelfth amplifying transistor M12, and the thirteenth amplifying transistor M13 are all N-type transistors, and the tenth amplifying transistor M10, the eleventh amplifying transistor M11, the twelfth amplifying transistor M12, and the thirteenth amplifying transistor M13 constitute a cascode structure with an active load as a part of an amplifier.
In one embodiment of the present invention, as shown in fig. 2, the driving module 102 includes a fourth current mirror module 1021, a first driving transistor Md1, a second driving transistor Md2, a third driving transistor Md3, a fourth driving transistor Md4, a fifth driving transistor Md5 and a sixth driving transistor Md6, the first driving transistor Md1 is mirror-symmetrical to the fourth amplifying transistor M4 of the first current mirror module 1011, the source of the first driving transistor Md1 and the source of the second driving transistor Md2 are electrically connected to the fourth current mirror module 1021, the gate of the first driving transistor Md1 is electrically connected to the first current mirror module 1011 and the second current mirror module 1012, the gate of the third driving transistor Md3 is electrically connected to the first current mirror module 1011 and the second current mirror module 1012, the source of the third driving transistor Md3 and the drain of the fourth driving transistor Md4 are electrically connected to the drain of the fourth driving transistor Md4 The gate of the Md6 is electrically connected, the source of the fifth drive transistor Md5, the drain of the sixth drive transistor Md6, the second current mirror module 1012 and the third current mirror module 1013 are electrically connected to the first end of the parasitic capacitor module, the gate of the second drive transistor Md2 is electrically connected to a fourth voltage source Vb3, the fourth drive transistor Md4 is electrically connected to a fifth voltage source Vb4, the gate of the fifth drive transistor Md5 is electrically connected to the source of the second drive transistor Md2 and the fourth current mirror module 1021, the source of the fourth drive transistor Md4 and the source of the sixth drive transistor Md6 are grounded, the drain of the first drive transistor Md1, the drain of the second drive transistor Md2, the drain of the third drive transistor Md3, and the drain of the fifth drive transistor Md5 are electrically connected to a second voltage source, the fourth current mirror module 1021 performs an amplification function, and the third drive transistor Md3 and the fourth drive transistor Md4 also perform an amplification function;
As shown in fig. 2, the source of the first driving transistor Md1 and the source of the second driving transistor Md2 are electrically connected to the fourth current mirror module 1021, the gate of the third amplification transistor M3, the source of the third amplification transistor M3, the drain of the first amplification transistor M1, and the gate of the seventh amplification transistor M7 are electrically connected to the gate of the first drive transistor Md1, the gate of the fourth amplifying transistor M4, the source of the fourth amplifying transistor M4, the gate of the sixth amplifying transistor M6 and the drain of the second amplifying transistor M2 are electrically connected to the gate of the third drive transistor Md3, the source of the fifth drive transistor Md5, the drain of the sixth drive transistor Md6, the source of the ninth amplification transistor M9, and the drain of the eleventh amplification transistor M11 are electrically connected to the first end of the parasitic capacitance block, respectively; the first drive transistor Md1, the second drive transistor Md2, the third drive transistor Md3, and the fifth drive transistor Md5 are all P-type transistors, and the fourth drive transistor Md4 and the sixth drive transistor Md6 are all N-type transistors.
In one embodiment of the present application, as shown in fig. 2, the fourth current mirror module 1021 includes a seventh driving transistor Md7 and an eighth driving transistor Md8, the seventh drive transistor Md7 and the eighth drive transistor Md8 are mirror-symmetrical, the source of the first drive transistor Md1, the drain of the seventh drive transistor Md7 and the gate of the seventh drive transistor Md7 are electrically connected to the gate of the eighth drive transistor Md8, the source of the second drive transistor Md2 and the gate of the fifth drive transistor Md5 are electrically connected to the drain of the eighth drive transistor Md8, the source of the seventh drive transistor Md7 and the source of the eighth drive transistor Md8 are grounded, the seventh drive transistor Md7 and the eighth drive transistor Md8 are both N-type transistors, the seventh drive transistor Md7 and the eighth drive transistor Md8 described above function as a current mirror.
In an embodiment of the present application, as shown in fig. 1, the feedback unit 20 further includes a frequency compensation module 201, a drain of the power transistor M is electrically connected to a sixth voltage source, and the frequency compensation module 201 is electrically connected to a source of the power transistor M. The frequency compensation module is used for enabling the circuit to output stable output voltage, and plays a role in frequency compensation, so that the circuit can output stable output voltage under a light load state.
In an embodiment of the present application, as shown in fig. 1, the frequency compensation module 201 includes a compensation capacitor CoutAnd a compensation resistor RserThe compensation capacitor CoutFirst terminal of (2) and the compensation resistor RserIs electrically connected to the first terminal of the compensation capacitor CoutThe second terminal of (3) is grounded, and the compensation resistor RserIs electrically connected to the source of the power transistor M, the load module RLIs electrically connected to the source of the power transistor M, the load module RLIs grounded, the load module RLMay be a load resistor RL。
As shown in fig. 1 and 2, the operation principle of the circuit is as follows: the working principle and the working process of the circuit are as follows: by providing the fourth voltage source Vb3 and the fifth voltage source Vb4, the second drive transistor Md2 and the fourth drive transistor Md4 are in a linear operation region, and the eighth drive transistor Md8 and the third drive transistor Md3 are in a saturation operation region due to a current mirror effect. In a normal operation state, the currents of the second driving transistor Md2 and the eighth driving transistor Md8 are equal to each otherThe currents in the third driving transistor Md3 and the fourth driving transistor Md4 are equal, and since the second driving transistor Md2 is in the linear region, the voltage at the node N1 approaches the voltage of the second voltage source (i.e., VDD in fig. 2), so that the fifth driving transistor Md5 is in the off state. Similarly, the fourth driving transistor Md4 is in the linear region, the voltage at the node N2 is close to VSS as in fig. 2, and therefore the sixth driving transistor Md6 is in the off state. When the load current suddenly increases (any one of the modules suddenly works), the output voltage V of the circuit is caused to be increased outAn undershoot occurs to cause a decrease in the gate voltage of the power transistor M and a decrease in the gate voltage of the second amplification transistor M2, so that the current in the first amplification transistor M1 increases, the current in the third amplification transistor M3 increases, the current in the first drive transistor Md1 increases, the current in the seventh drive transistor Md7 increases, and the current in the eighth drive transistor Md8 increases due to a current mirror effect. Since the current of the eighth driving transistor Md8 is equal to the current of the second driving transistor Md2, the current of the second driving transistor Md2 will also increase, and since the second driving transistor Md2 is in the linear operating region in the normal state, the voltage of the node N1 will decrease, so that the fifth driving transistor Md5 will be turned on, and since the sixth driving transistor Md6 is still in the off state at this time, a large current will flow from the second voltage source to the parasitic capacitor C of the gate terminal of the power transistor M through the fifth driving transistor Md5LThe gate of the power transistor M is charged quickly, so that the gate voltage of the power transistor M is increased quickly, the output current of the power transistor M is adjusted quickly to be reduced, the output voltage of the low dropout linear voltage regulator circuit is reduced quickly, and the effect of improving the transient response characteristic is achieved.
The same reasoning is that when the load current suddenly decreases (power off and on), the output voltage V is caused to decreaseoutAn overshoot is generated, causing the gate voltage of the power transistor M to rise, the gate voltage of the second amplification transistor M2 to rise, the current in the second amplification transistor M2 to increase, and the fourth amplification transistor M2 to increaseThe current in the transistor M4 increases, and due to current mirroring, the current in the third drive transistor Md3 increases. Since the current of the third driving transistor Md3 is equal to the current of the fourth driving transistor Md4, the current of the fourth driving transistor Md4 will also increase, and since the fourth driving transistor Md4 is in the linear operating region in the normal state, the voltage of the N2 node will increase, so that the sixth driving transistor Md6 is turned on, and since the fifth driving transistor Md5 is still in the off state at this time, a large current will pass through the sixth driving transistor Md6 to supply the external load capacitor C with the currentLDischarging to rapidly reduce the gate voltage of the power transistor M, thereby rapidly adjusting the output current of the power transistor M to increase, and enabling the output voltage V of the low dropout linear voltage regulator circuitoutThe transient response characteristic is improved by rapid rising.
An embodiment of the present application further provides an electronic device, where the electronic device includes any one of the above low dropout linear voltage regulator circuits.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (12)
1. A low dropout linear voltage regulator circuit, comprising:
the feedback unit comprises a power transistor and a load module, the power transistor is electrically connected with the load module, and the feedback unit adjusts the output voltage of the feedback unit by adjusting the current flowing through the power transistor;
the output end of the transient response unit is electrically connected with the power transistor, when the current of the load module jumps in a step mode, the voltage of the power transistor changes, and the transient response unit adjusts the output voltage of the feedback unit under the condition that the voltage of the power transistor changes.
2. The circuit of claim 1, wherein the feedback unit further comprises a first feedback resistor and a second feedback resistor, a first end of the first feedback resistor is electrically connected to the output end of the feedback unit and the source of the power transistor, respectively, and a first end of the second feedback resistor is grounded; the circuit further comprises:
the reference voltage generating module is used for providing reference voltage;
the amplifier is provided with a first input end, a second input end and an output end, the first input end of the amplifier is electrically connected with the output end of the reference voltage generation module, the second input end of the amplifier is respectively and electrically connected with the second end of the first feedback resistor and the second end of the second feedback resistor, and the output end of the amplifier is electrically connected with the input end of the transient response unit.
3. The circuit of claim 2, wherein the transient response unit comprises:
the parasitic capacitance module comprises a first end and a second end, the first end of the parasitic capacitance module is electrically connected with the grid electrode of the power transistor, and the second end of the parasitic capacitance module is grounded;
the current amplification module comprises an input end and an output end, and the input end of the current amplification module is electrically connected with the output end of the amplifier;
The driving module comprises an input end and an output end, the input end of the driving module is electrically connected with the output end of the current amplification module, and the output end of the driving module is electrically connected with the first end of the parasitic capacitance module and used for driving the parasitic capacitance module.
4. The circuit of claim 3, wherein the current amplifying module comprises a fifth amplifying transistor, a first current mirror module, a second current mirror module and a third current mirror module, the first current mirror module is electrically connected to the drain of the fifth amplifying transistor and the second current mirror module, respectively, the second current mirror module is electrically connected to the third current mirror module, the gate of the fifth amplifying transistor is electrically connected to a first voltage source, and the source of the fifth amplifying transistor is grounded.
5. The circuit according to claim 4, wherein the first current mirror module comprises a first amplifying transistor, a second amplifying transistor, a third amplifying transistor and a fourth amplifying transistor, the first amplifying transistor and the second amplifying transistor are in mirror symmetry, the third amplifying transistor and the fourth amplifying transistor are in mirror symmetry, a source of the third amplifying transistor is electrically connected with a drain of the first amplifying transistor, a source of the fourth amplifying transistor is electrically connected with a drain of the second amplifying transistor, a source of the first amplifying transistor and a source of the second amplifying transistor are respectively electrically connected with a drain of the fifth amplifying transistor, a gate of the first amplifying transistor is electrically connected with an output terminal of the amplifier, a gate of the second amplifying transistor is grounded, and a drain of the first amplifying transistor is respectively connected with a source of the third amplifying transistor, a drain of the first amplifying transistor is electrically connected with a drain of the fifth amplifying transistor, a drain of the first amplifying transistor is electrically connected with a drain of the second amplifying transistor, The grid electrode of the third amplifying transistor is electrically connected with the input end of the driving module, the grid electrode of the fourth amplifying transistor is electrically connected with the drain electrode of the second amplifying transistor, the second current mirror module and the input end of the driving module respectively, and the drain electrode of the third amplifying transistor and the drain electrode of the fourth amplifying transistor are electrically connected with a second voltage source respectively.
6. The circuit according to claim 4, wherein the second current mirror module comprises a sixth amplifying transistor, a seventh amplifying transistor, an eighth amplifying transistor and a ninth amplifying transistor, the sixth amplifying transistor is mirror-symmetrical to the seventh amplifying transistor, the eighth amplifying transistor is mirror-symmetrical to the ninth amplifying transistor, a source of the sixth amplifying transistor is electrically connected to a drain of the eighth amplifying transistor, a source of the seventh amplifying transistor is electrically connected to a drain of the ninth amplifying transistor, a gate of the sixth amplifying transistor is electrically connected to the first current mirror module and the input of the driving module, respectively, a gate of the seventh amplifying transistor is electrically connected to the input of the driving module and the first current mirror module, respectively, and a gate of the eighth amplifying transistor is electrically connected to a gate of the ninth amplifying transistor, the source electrode of the eighth amplifying transistor is electrically connected with the third current mirror module, the source electrode of the ninth amplifying transistor is electrically connected with the output ends of the third current mirror module and the driving module respectively, and the drain electrode of the sixth amplifying transistor and the drain electrode of the seventh amplifying transistor are electrically connected with a second voltage source respectively.
7. The circuit of claim 4, wherein the third current mirror module comprises a tenth amplifying transistor, an eleventh amplifying transistor, a twelfth amplifying transistor and a thirteenth amplifying transistor, the tenth amplifying transistor is mirror-symmetrical to the eleventh amplifying transistor, the twelfth amplifying transistor is mirror-symmetrical to the thirteenth amplifying transistor, a source of the tenth amplifying transistor is electrically connected to a drain of the twelfth amplifying transistor, a source of the eleventh amplifying transistor is electrically connected to a drain of the thirteenth amplifying transistor, a drain of the second current mirror module, a drain of the tenth amplifying transistor and a gate of the twelfth amplifying transistor are electrically connected to a gate of the thirteenth amplifying transistor, respectively, and a gate of the tenth amplifying transistor is electrically connected to a gate of the eleventh amplifying transistor and a third voltage source, respectively, a gate of the twelfth amplifying transistor is electrically connected to a gate of the thirteenth amplifying transistor, the second current mirror module and a drain of the tenth amplifying transistor, respectively, and a source of the twelfth amplifying transistor and a source of the thirteenth amplifying transistor are grounded, respectively.
8. The circuit of claim 5, wherein the driving module comprises a fourth current mirror module, a first driving transistor, a second driving transistor, a third driving transistor, a fourth driving transistor, a fifth driving transistor and a sixth driving transistor, the first driving transistor is mirror-symmetrical to the fourth amplifying transistor, a source of the first driving transistor and a source of the second driving transistor are electrically connected to the fourth current mirror module, respectively, a gate of the first driving transistor is electrically connected to the first current mirror module and the second current mirror module, respectively, a gate of the third driving transistor is electrically connected to the first current mirror module and the second current mirror module, respectively, a source of the third driving transistor and a drain of the fourth driving transistor are electrically connected to a gate of the sixth driving transistor, respectively, the source electrode of the fifth driving transistor, the drain electrode of the sixth driving transistor, the second current mirror module and the third current mirror module are respectively and electrically connected with the first end of the parasitic capacitance module, the grid electrode of the second driving transistor is electrically connected with a fourth voltage source, the fourth driving transistor is electrically connected with a fifth voltage source, the grid electrode of the fifth driving transistor is respectively and electrically connected with the source electrode of the second driving transistor and the fourth current mirror module, the source electrode of the fourth driving transistor and the source electrode of the sixth driving transistor are respectively grounded, and the drain electrode of the first driving transistor, the drain electrode of the second driving transistor, the drain electrode of the third driving transistor and the drain electrode of the fifth driving transistor are respectively and electrically connected with a second voltage source.
9. The circuit of claim 8, wherein the fourth current mirror module comprises a seventh driving transistor and an eighth driving transistor, the seventh driving transistor and the eighth driving transistor are mirror-symmetric, a source of the first driving transistor, a drain of the seventh driving transistor, and a gate of the seventh driving transistor are electrically connected to a gate of the eighth driving transistor, respectively, a source of the second driving transistor and a gate of the fifth driving transistor are electrically connected to a drain of the eighth driving transistor, respectively, and a source of the seventh driving transistor and a source of the eighth driving transistor are grounded, respectively.
10. The circuit according to any one of claims 2 to 9, wherein the feedback unit further comprises a frequency compensation module, a drain of the power transistor is electrically connected to a sixth voltage source, and the frequency compensation module is electrically connected to a source of the power transistor.
11. The circuit of claim 10, wherein the frequency compensation module comprises a compensation capacitor and a compensation resistor, a first terminal of the compensation capacitor is electrically connected to a first terminal of the compensation resistor, a second terminal of the compensation capacitor is connected to ground, a second terminal of the compensation resistor is electrically connected to the source of the power transistor, a first terminal of the load module is electrically connected to the source of the power transistor, and a second terminal of the load module is connected to ground.
12. An electronic device, wherein the electronic device comprises the low dropout linear voltage regulator circuit of any one of claims 1 to 11.
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| CN202210339416.0A CN114756083A (en) | 2022-04-01 | 2022-04-01 | Low-dropout linear voltage stabilizing circuit and electronic equipment |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115437444A (en) * | 2022-10-12 | 2022-12-06 | 群联电子股份有限公司 | Voltage stabilizing circuit module, memory storage device and voltage control method |
| CN116505486A (en) * | 2023-06-28 | 2023-07-28 | 深圳市小耳朵电源有限公司 | Overload-preventing net-shaped power supply control circuit and control method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102707754A (en) * | 2012-05-30 | 2012-10-03 | 昆山锐芯微电子有限公司 | Low dropout regulator |
| CN102830742A (en) * | 2012-09-14 | 2012-12-19 | 邹磊 | Linear stabilizer with low pressure difference |
| CN206162234U (en) * | 2016-09-14 | 2017-05-10 | 成都旋极星源信息技术有限公司 | Weighting current feedback's low dropout regulator |
| CN107102671A (en) * | 2017-04-28 | 2017-08-29 | 成都华微电子科技有限公司 | Low-power consumption fast transient response low-voltage difference adjustor |
| CN110488908A (en) * | 2019-09-02 | 2019-11-22 | 中国科学院微电子研究所 | A kind of low pressure difference linear voltage regulator improving transient response |
-
2022
- 2022-04-01 CN CN202210339416.0A patent/CN114756083A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102707754A (en) * | 2012-05-30 | 2012-10-03 | 昆山锐芯微电子有限公司 | Low dropout regulator |
| CN102830742A (en) * | 2012-09-14 | 2012-12-19 | 邹磊 | Linear stabilizer with low pressure difference |
| CN206162234U (en) * | 2016-09-14 | 2017-05-10 | 成都旋极星源信息技术有限公司 | Weighting current feedback's low dropout regulator |
| CN107102671A (en) * | 2017-04-28 | 2017-08-29 | 成都华微电子科技有限公司 | Low-power consumption fast transient response low-voltage difference adjustor |
| CN110488908A (en) * | 2019-09-02 | 2019-11-22 | 中国科学院微电子研究所 | A kind of low pressure difference linear voltage regulator improving transient response |
Non-Patent Citations (1)
| Title |
|---|
| HOI LEE; P.K.T. MOK; KA NANG LEUNG: "Design of Low-Power Analog Drivers Based on Slew-Rate Enhancement Circuits for CMOS Low-Dropout Regulators", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, vol. 52, no. 9, pages 563 - 567 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115437444A (en) * | 2022-10-12 | 2022-12-06 | 群联电子股份有限公司 | Voltage stabilizing circuit module, memory storage device and voltage control method |
| CN115437444B (en) * | 2022-10-12 | 2024-03-12 | 群联电子股份有限公司 | Voltage stabilizing circuit module, memory storage device and voltage control method |
| CN116505486A (en) * | 2023-06-28 | 2023-07-28 | 深圳市小耳朵电源有限公司 | Overload-preventing net-shaped power supply control circuit and control method thereof |
| CN116505486B (en) * | 2023-06-28 | 2024-04-02 | 深圳市小耳朵电源有限公司 | Overload-preventing net-shaped power supply control circuit and control method thereof |
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