CN116225118A - LDO circuit based on PN complementary current compensation power supply ripple feedforward - Google Patents

LDO circuit based on PN complementary current compensation power supply ripple feedforward Download PDF

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CN116225118A
CN116225118A CN202310068819.0A CN202310068819A CN116225118A CN 116225118 A CN116225118 A CN 116225118A CN 202310068819 A CN202310068819 A CN 202310068819A CN 116225118 A CN116225118 A CN 116225118A
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drain electrode
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gate
source
electrode
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刘素娟
葛傲冉
刘堃
辛子丰
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Beijing University of Technology
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/561—Voltage to current converters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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Abstract

The invention designs an LDO circuit based on PN complementary current compensation power supply ripple feedforward, which mainly comprises a reference bias circuit, an error amplifier, a feedforward ripple circuit, an overshoot compensation circuit and a power output stage consisting of a power tube and a voltage division sampling circuit. The reference bias circuit is connected with the error amplifier, the feedforward ripple circuit and the overshoot compensation circuit and provides bias voltage; the error amplifier compares the feedback voltage with the reference voltage, transmits the comparison result to the grid electrode of the power tube, adjusts the change of the grid electrode voltage of the power tube, and also adjusts the output voltage connected with the drain electrode of the power tube; the feedforward ripple circuit is connected with the grid electrode of the power tube and the output voltage, adjusts the overshoot (undervoltage) state of the output voltage, stabilizes the output and enhances the transient state; the overshoot compensation circuit is connected with the output voltage, adjusts the overshoot state of the output voltage, stabilizes the output and enhances the transient state. The invention has better power supply voltage inhibition ratio and better stability.

Description

LDO circuit based on PN complementary current compensation power supply ripple feedforward
Technical Field
The invention designs a low-voltage linear voltage regulator (Low Dropout Regulator, LDO) and provides a feedforward ripple circuit structure which has three functions and can respectively improve the transient response of the low-voltage linear voltage regulator, the power supply voltage rejection ratio and the stability of the whole circuit module to a certain extent. And is used as a power supply to supply power to other circuit modules, and belongs to the technical field of power management modules of integrated circuits.
Background
The low dropout linear regulator (LDO) has smaller chip area, higher power supply voltage suppression and quick time domain response, and is widely applied to a power supply management module of an ultra-large-scale integrated circuit. The invention designs an LDO architecture with higher power supply voltage rejection ratio and high-speed transient response.
It is important for LDOs to be able to suppress power supply ripple, isolate power supply noise, and regulate quickly for different current loads. The common methods for improving the supply voltage suppression ratio of the circuit are as follows: the gain of the loop is improved, a reference circuit with high power supply voltage rejection ratio is adopted, LDO cascading is adopted, a circuit structure for improving the power supply voltage rejection ratio is added, and the like. For high integration LDOs without off-chip capacitance, enhancing the transient response may reduce the transient response time by increasing the bandwidth of the loop, increasing the switching current of the gate node of the power transistor, and so on.
The invention reduces the influence of power supply ripple variation on output voltage through a feedforward ripple circuit. When the ripple wave of the power supply is transmitted to the source electrode of the power tube, the feedforward ripple wave circuit can amplify the voltage ripple wave of the grid electrode of the power tube, and the voltage ripple wave cancel each other out, so that the effect of improving the voltage rejection ratio of the power supply is achieved. When the output voltage generates overshoot (undervoltage), the feedforward ripple circuit can be dynamically regulated quickly, so that the output voltage of the circuit can quickly enter a stable state.
Disclosure of Invention
The invention aims to design a PN-based complementary current compensation power supply ripple feedforward LDO circuit which is used as a power supply management module in a chip of a mobile system and has faster transient response and higher power supply voltage rejection ratio.
In order to achieve the above purpose, the invention adopts the following technical scheme:
an LDO circuit based on PN complementary current compensation power supply ripple feedforward comprises a reference bias circuit, an error amplifier and a power output stage, and is characterized in that: and also comprisesA feedforward ripple circuit and an overshoot compensation circuit; the reference bias circuit is connected with the error amplifier, the feedforward ripple circuit and the overshoot compensation circuit; the positive input end of the error amplifier is connected with a resistor R in a voltage division sampling circuit 1 And R is 2 Feedback voltage V obtained by voltage division FB The reverse input end is connected with the reference voltage V REF The output end is connected with the feedforward ripple circuit and the grid electrode of the power tube; the feedforward ripple circuit, the overshoot compensation circuit, the voltage division sampling circuit and the drain electrode of the power tube are connected with the output voltage V OUT The method comprises the steps of carrying out a first treatment on the surface of the The source electrode of the power tube and the feedforward ripple circuit are connected with a power supply signal VDD; the feedforward ripple circuit, the overshoot compensation circuit and the partial pressure sampling circuit are connected with the power supply signal GND.
Wherein the reference bias circuit provides a reference current independent of the supply voltage to the circuit and provides a bias voltage to the remaining circuits.
Wherein the error amplifier is realized by a rail-to-rail complementary operational amplifier, and feeds back the voltage V FB And reference voltage V REF The result of the comparison is passed to the power output stage.
Wherein the feedforward ripple circuit is composed of PN-type complementary structure and Low Pass Filter (LPF), when outputting voltage V out When in fluctuation, the PN complementary structure can rapidly adjust current, stabilize output and enhance transient; meanwhile, the ripple of the grid voltage of the power tube is amplified to offset the ripple generated by the power voltage of the source electrode of the power tube, so that the power voltage suppression ratio is improved.
Wherein the overshoot compensation circuit adjusts the overshoot state of the output voltage through a Low Pass Filter (LPF).
The power output stage consists of a power tube and a partial pressure sampling circuit. Wherein the voltage division sampling circuit is composed of a resistor R 1 And R is 2 Composition of output voltage V out And performing sampling set partial pressure. The grid electrode of the power tube is controlled by the output of the error amplifier in the feedback loop and rapidly adjusts the output current to stabilize the output voltage V out 。
The voltage stabilizing process of the low dropout linear voltage regulator of the invention specifically comprises the following steps:
step 1, LDO provides power for other circuit modules, and stably provides power supply voltage of 1.8V and required load current.
Step 2, when the load size is changed, the feedback circuit starts to work, and the changed voltage is fed back to the error amplifier and the reference voltage V REF The comparison generates an error voltage value which is transmitted to the grid electrode of the power tube for adjustment.
Step 3, when the load current becomes smaller, the output voltage V is caused out The increase is in an overshoot state, where the overshoot compensation circuit and the feedforward ripple circuit are acting simultaneously. In overshoot compensation circuit with output voltage V out M linked to 37 The source voltage increases, but the voltage of the gate of the tube is unchanged due to the connection of the gate of the tube to the LPF, so that the flowing current increases; promote M 40 The gate voltage of the power tube is changed from the cut-off state to the conducting state, a current to the ground is generated, and the power tube can be rapidly discharged, so that the influence of overshoot is reduced. Playing a role in stabilizing voltage. Simultaneously the feedforward ripple circuit is connected with the output voltage V out The connected capacitor C4 is conducted to make M in PN type complementary structure 27 And the grid voltage is locked into VB3 by LPF3, so that drain-source current is generated, the grid voltage of the power tube is increased, the current flowing through the power tube is reduced, the output voltage is reduced, and the effect of stabilizing the voltage is achieved.
Step 4, when the load current becomes large, the output voltage V is caused out The voltage under-voltage state is reduced, only the feedforward ripple circuit acts, and the feedforward ripple circuit is connected with the output voltage V out The connected capacitor C2 is conducted to make M in PN type complementary structure 26 At the same time, the grid voltage is locked to the bias voltage VB2 by the LPF2, so that drain-source current is generated, the grid voltage of the power tube is reduced, the current flowing through the power tube is increased, the output voltage is increased, and the effect of stabilizing the voltage is achieved.
Step 5, when the ripple of the power supply voltage affects the output of the power tube at high frequency, M is used in the feedforward ripple circuit 25 And M 26 The common grid electrode has a certain gain and is used for the electricity of the grid electrode of the power tubeThe ripple wave is amplified and counteracted with the ripple wave generated by the power supply voltage at the source electrode, so that the power supply voltage inhibition ratio of the circuit at high frequency is improved.
Compared with the existing LDO structure, the low dropout linear voltage regulator system designed by the invention has the following beneficial effects:
1. the feedforward ripple circuit is adopted to improve the performance of the circuit in various aspects, firstly, the feedforward circuit can improve the power supply voltage rejection ratio of the circuit structure, and under the combined transformation of a process, a power supply and a temperature (PVT), the minimum value of the power supply voltage rejection ratio (PSRR: power Supply Rejection Ratio) of the circuit under low frequency is-98.3 dB, the minimum value of the power supply voltage rejection ratio under high frequency is-38.9 dB, and the feedforward circuit has relatively good power supply ripple rejection performance. Secondly, the stability of the circuit is enhanced, and the minimum value of the phase margin of the circuit is 74.35 degrees under the combined transformation of the process, the power supply and the temperature (PVT); in general, the phase margin is over 90 degrees, and the whole circuit has good stability. Finally, the feedforward circuit enhances the transient response of the LDO circuit, and the time for the output voltage to return to the stable voltage is within 100 ns.
2. The reference bias circuit provides proper bias voltage for an error amplifier, a feedforward ripple circuit and an overshoot compensation circuit in the LDO circuit, so that static power consumption is relatively small; simultaneously using resistors R of different temperature coefficients in reference bias circuits 5 And R is 11 The output current is enabled to be very small along with the temperature change, so that the temperature drift of the whole circuit is smaller within the temperature change range of-40 ℃ to 125 ℃.
Drawings
FIG. 1 is a block diagram of an LDO system according to the present invention
FIG. 2 shows a feedforward ripple circuit diagram according to the present invention
Fig. 3 overshoot compensation circuit in the present invention
FIG. 4 is a circuit diagram of an LDO system according to the present invention
FIG. 5 shows the quiescent current of the LDO according to the present invention at load currents of 0A and 20mA
FIG. 6 is a transient simulation of overshoot and undervoltage for the LDO standard condition proposed by the present invention
FIG. 7 is a graph of gain versus amplitude-frequency for LDO with and without a feedforward ripple circuit at load currents of 0A and 20mA, respectively
FIG. 8 is a graph showing the supply voltage rejection ratio of LDO with load current of 0A and 20mA, respectively, for a feedforward ripple circuit
Detailed Description
The circuit modules and simulation test results of the PN-based complementary current compensation power supply ripple feedforward LDO circuit design are further described in detail below with reference to the embodiments and the drawings.
Example 1
The invention is introduced by combining the actual design and test result of designing an LDO circuit based on a TSMC180nm process library. The integral structure of the LDO comprises a reference bias circuit, an error amplifier, a feedforward ripple circuit, an overshoot compensation circuit and a power output stage; under the TSMC180nm technology, the input voltage is 3.2-5V, the output voltage is 1.8V, the load capacitance is 100pF, the load current of 0-20 mA can be output, and the LDO area is about 0.087mm 2 The layout area is smaller.
The overall LDO system architecture and circuit diagram is shown in fig. 1 and 4.
1. Connection mode
In the LDO system architecture diagram shown in FIG. 1, the input power supply signals of the LDO system are VDD and GND, and the output voltage is V OUT . The reference bias circuit is connected with the error amplifier, the feedforward ripple circuit and the overshoot compensation circuit. The reverse input end of the error amplifier is connected with the reference voltage V REF The positive input end is connected with the feedback voltage V of the circuit FB . The feedforward ripple circuit is connected with the output of the error amplifier and the grid electrode of the power tube. Output voltage V OUT With feedforward ripple circuit, overshoot compensation circuit, drain electrode of power tube and R 1 And R is 2 The partial pressure sampling circuit is connected. Resistor R 1 And R is 2 Is connected with the circuit feedback voltage V FB Is connected with each other. The power tube and the voltage division sampling circuit form a power output stage. The power supply signal VDD is connected with the source electrode of the power tube and the feedforward ripple circuit; power signal GNDResistor R 2 The feedforward ripple circuit is connected with the overshoot compensation circuit.
In the feedforward ripple circuit shown in fig. 2, the input power supply signals are VDD and GND, and the output voltage is V OUT ；M 25 And M 26 Is PMOS tube, M 27 And M 28 NMOS tubes which form PN-type complementary structures together; m is M 25 Drain electrode of (C) and M 26 Is connected to one end of a capacitor C2, M 27 Source electrode of (C) and M 28 The drain electrode of the capacitor C4 is connected with one end of the capacitor C2 and the other end of the capacitor C4 are commonly connected with the output voltage V OUT ；M 25 Is connected by a resistor R 7 And C5 LPF1, M 26 Is connected by a resistor R 8 And C6 LPF2, M 27 Is connected by a resistor R 9 And C7 LPF3, M 28 Is connected by a resistor R 10 And LPF4 composed of C8; LPF1, LPF2, LPF3, and LPF4 are connected to bias voltages VB1, VB2, VB3, and VB4 generated by the reference bias circuit, respectively; m is M 26 Drain electrode of (C) and M 27 The drain electrode of the power tube is connected with the grid electrode of the power tube; m is M 25 Is connected with the power supply signal VDD, M 28 One end of the source and the capacitors C5, C6, C7 and C8 are connected to the power supply signal GND.
In the overshoot compensation circuit shown in fig. 3, the input power supply signal is GND, and the output voltage is V OUT ，M 36 Source, M of (2) 37 Source and M of (2) 40 Is connected with the output voltage V OUT ；M 36 Is short-circuited with the gate and drain of R 6 And C9 LPF and M 38 Drain electrode connection of M 37 Is connected with LPF, M 37 Drain electrode of (C) and M 39 Drain electrode of (C) and M 40 Is connected with the grid electrode; m is M 38 Gate and M of (2) 39 Is connected with a bias voltage VB4 generated by a reference bias circuit; m is M 38 Source, M of (2) 39 Source, M of (2) 40 One ends of the source and C9 of (C) are connected to the power supply signal GND.
In the LDO system circuit diagram shown in FIG. 4, the LDO circuit is composed of a reference bias circuit, an error amplifier, a feedforward ripple circuit, an overshoot compensation circuit and a power output stage, and isThe input power supply signals of the system circuit are VDD and GND, and the input reference voltage is formed by V REF Representing the output signal by V OUT And (3) representing. The abbreviations for all transistors and their representative meanings in fig. 4 are summarized in table 1, the abbreviations for all resistors are summarized in table 2, and the abbreviations for all capacitors are summarized in table 3. The number of transistors, resistors and capacitors is large, and these will be referred to as short.
In FIG. 4, M 1 、M 2 、M 3 、M 4 、M 7 、M 8 、M 9 、M 13 、M 14 、M 15 、M 16 、M 21 、M 24 、M 25 、M 26 、M 29 、M 34 、M 35 、M 36 、M 37 、M 41 、M P Is a PMOS transistor; m is M 5 、M 6 、M 10 、M 11 、M 12 、M 17 、M 18 、M 19 、M 20 、M 22 、M 23 、M 27 、M 28 、M 30 、M 31 、M 32 、M 33 、M 38 、M 39 、M 40 、M 42 Is an NMOS transistor. Wherein M is 1 、M 2 、M 9 、M 13 、M 14 、M 21 、M 24 、M 25 、M 29 、M 34 、M P Is connected to VDD; m is M 5 、M 12 、M 19 、M 20 、M 22 、M 23 、M 28 、M 32 、M 33 、M 38 、M 39 、M 40 Is connected to GND. All PMOS substrates are connected with VDD, and all NMOS substrates are connected with GND.
M 1 Is short-circuited with the drain and gate of M 2 Gate, M of (2) 3 Source and M of (2) 29 Is connected to the gate of (c). M is M 2 Drain electrode of (C) and M 4 Is connected with the source electrode of the transistor; m is M 4 Is short-circuited with the drain and is M 3 Gate, M of (2) 6 Is connected with the drain electrode of the transistor; m is M 5 Is short-circuited with the drain and is M 3 A drain electrode of (C),M 6 Is connected with the grid electrode of the power supply; r is R 5 And M 6 The other end is connected with R 11 R is one end of 11 The other end is connected with GND. M is M 9 Gate electrode of VB1, M 9 Drain electrode is respectively connected with M 7 Source, M of (2) 8 Source, M of (2) 41 Is connected with the drain electrode; m is M 41 The grid electrode of the power supply is connected with the power supply VDD; m is M 7 Gate and M of (2) 10 The grid electrode of (C) is all equal to V FB Are connected; m is M 8 Gate and M of (2) 11 The grid electrode of (C) is all equal to V REF Are connected; m is M 12 Gate electrode of VB4, M 12 Drain electrode of (a) is respectively with M 10 Source, M of (2) 11 Source, M of (2) 42 Is connected with the drain electrode; m is M 42 Is connected to GND. M is M 13 Gate and M of (2) 14 Gate, M of (2) 15 Drain electrode of M 17 Drain electrode of (C) and M 24 Is connected with the grid electrode of the power supply; m is M 13 Drain electrode of (C) and M 15 Source and M of (2) 10 Is connected with the drain electrode of the transistor; m is M 14 Drain electrode of (C) and M 16 Source and M of (2) 11 Is connected with the drain electrode of the transistor; m is M 15 Gate and M of (2) 16 The gates of the (C) are connected with VB2; m is M 16 Drain electrode of (C) and M 18 Drain electrode of (C) and M 21 Is connected with the grid electrode of the power supply; m is M 17 Gate and M of (2) 18 The grid electrodes of the (C) are connected with VB3; m is M 17 Source electrode of (C) and M 19 Drain electrode of (C) and M 7 Is connected with the drain electrode of the transistor; m is M 18 Source electrode of (C) and M 8 Drain electrode of (C) and M 20 Is connected with the drain electrode of the transistor; m is M 19 Gate and M of (2) 20 And the gates of (2) are all connected with VB4.M is M 22 Is short-circuited with the gate and drain of M 23 Gate, M of (2) 21 Is connected with the drain electrode of the transistor; m is M 23 Drain electrode of (C) and M 24 Is connected to the drain of the transistor. M is M 30 Gate, M of (2) 31 Gate, M of (2) 29 Drain electrode and R of (2) 3 Is connected with VB3 at one end; r is R 3 And M at the other end of (2) 31 Drain electrode of M 32 Gate and M of (2) 33 The gates of the (C) are connected with VB4; m is M 31 Source and M of (2) 32 Is connected with the drain electrode of the transistor; m is M 30 Source and M of (2) 33 Is connected with the drain electrode of the transistor; m is M 34 Drain electrode of (C) and M 35 Is connected with the source electrode of the transistor; m is M 34 Gate, M of (2) 35 Drain electrode and R of (2) 4 Is connected with VB1 at one end; r is R 4 Is the other end of M 30 Drain electrode of (C) and M 35 And the gates of (2) are connected with VB2.
M 25 Gate and resistor R of (2) 7 Is connected to one end of capacitor C5, R 7 The other end of (C) is connected with VB1 and the other end of C5 is connected with GND. M is M 26 Gate and resistor R of (2) 8 Is connected to one end of a capacitor C6, R 8 The other end of (2) is connected with VB2 and the other end of C6 is connected with GND. M is M 27 Gate and resistor R of (2) 9 Is connected to one end of capacitor C7, R 9 And VB3, and C7, respectively. M is M 28 Gate and resistor R of (2) 10 Is connected with one end of a capacitor C8, R 10 And VB4, and C8, respectively. M is M 36 Is short-circuited with the gate and drain of M 38 Drain of (d) and resistance R 6 Is connected with one end of the connecting rod; r is R 6 And M at the other end of (2) 37 Is connected with one end of a capacitor C9; the other end of the capacitor C9 is connected with GND; m is M 37 Source of (V) and V OUT Are connected; m is M 38 Gate and M of (2) 39 The gates of (2) are connected with VB4; m is M 37 Drain electrode of (C) and M 39 Drain electrode of (C) and M 40 Is connected to the gate of (c). M is M 40 Drain electrode of M 36 Source, M of (2) P Are all connected with V OUT The method comprises the steps of carrying out a first treatment on the surface of the One end of C1 is connected with M 13 The other end of C1 is connected with V OUT ；M 25 Drain electrode of (C) and M 26 Is connected with one end of a capacitor C2, and the other end of the capacitor C2 is connected with V OUT ；M 26 Drain electrode of (C) and M 27 Drain electrode of M P Gate, M of (2) 24 Is connected with one end of a capacitor C3, and the other end of the capacitor C3 is connected with V OUT ；M 27 Source electrode of (C) and M 28 Is connected with one end of a capacitor C4, and the other end of the capacitor C4 is connected with V OUT The method comprises the steps of carrying out a first treatment on the surface of the Resistor R 1 One end of (2) is connected with V OUT ，R 1 And V at the other end of (2) FB And R is 2 Is connected with one end of the connecting rod; r is R 2 The other end of (2) is connected with GND.
2. Engineering design
Based on a TSMC180nm process library, an input voltage of 3.2V to 5V, an output voltage of 1.8V and a load current range of 0A to 20mA are designed. Tables 1, 2 and 3 summarize the design parameters for all devices.
3. Test results
The change in quiescent power consumption with temperature for LDOs at load currents of 0A and 20mA is shown by fig. 5. At a load current of 0A in the standard state (tt, 4.2V,40 ℃), the static power consumption was 38.18uA. The maximum quiescent current was 67.9uA at different process corners (tt, ss, ff) and at different temperatures (-40 ℃ C. To 125 ℃ C.).
As shown in fig. 6, under the standard process corner condition (i.e., tt process corner), the output voltage reaches 1.8V (±5%) when the load current rises, and 61ns is simulated later; the output voltage reached 1.8V (+ -5%) when the load current was dropped, and 49ns when it was used later. Overall, the time domain performance is better. The worst supply voltage regulation rate under the standard state is simulated to be 1.339uV/V. The worst load adjustment rate under the standard state is-0.638%.
FIG. 7 shows the amplitude frequency angle of the LDO system circuit when the gain is 0dB when the load current is 0A and 20mA respectively under the two conditions of the feedforward ripple circuit or not. The amplitude-frequency angle is approximately 0 degrees when the load current is 0A under the condition of no feedforward ripple circuit, and the circuit has no phase margin at the moment, so that the circuit is unstable; when the load current is 20mA, the amplitude frequency angle is 153 °, in which case the circuit output has oscillated. When the feedforward ripple circuit exists, when the load current is 0A and 20mA respectively, the amplitude frequency angle is 93 degrees and 98 degrees respectively, the phase margin of the circuit is more than 90 degrees, and the whole circuit is stable.
In fig. 8, the power supply voltage rejection ratio of the LDO system circuit at high frequency and low frequency is shown when the load current is 0A and 20mA, respectively, in both cases of the presence or absence of the feedforward ripple circuit. The worst 7.7dB of supply voltage rejection ratio can be obtained when the load current is 0A without the feedforward ripple circuit; and with the feedforward ripple circuit, the worst-5.5 dB of supply voltage rejection ratio is when the load current is 0A. At high frequencies, the supply voltage rejection ratio is close to-41 dB, both with and without the feed-forward ripple circuit.
Table 4 shows more fully the summary of the technical indexes imitated before and after the invention, which covers the performance parameters of each index under different temperatures, different power supply voltages and different process angles, and marks the process angle at which the performance index is the worst.
Table 1 summary of transistor design parameters
Figure BDA0004063212410000071
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Figure BDA0004063212410000081
TABLE 2 resistance design parameters
W(μm) L(μm) Fingers Multiplier Resistance value (KΩ)
R 1 0.42 10 1 1 100.232
R 2 0.42 10 2 1 200.465
R 3 2 20 15 1 150.463
R 4 2 20 15 1 150.463
R 5 0.43 20 23 1 8.212
R 6 0.42 10 6 1 601.395
R 7 0.42 10 20 1 2004.65
R 8 0.42 10 20 1 2004.65
R 9 0.42 10 20 1 2004.65
R 10 0.42 10 20 1 2004.65
R 11 2 2 3 1 3.475
TABLE 3 capacitance design parameters
Figure BDA0004063212410000082
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Figure BDA0004063212410000091
TABLE 4 design metrics for front and back simulation of circuits
Figure BDA0004063212410000092
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Claims (4)

1. An LDO circuit based on PN complementary current compensation power supply ripple feedforward comprises a reference bias circuit, an error amplifier and a power output stage, and is characterized in that: the device also comprises a feedforward ripple circuit and an overshoot compensation circuit; the reference bias circuit is connected with the error amplifier, the feedforward ripple circuit and the overshoot compensation circuit; the positive input end of the error amplifier is connected with a resistor R in a voltage division sampling circuit 1 And R is 2 Feedback voltage V obtained by voltage division FB The reverse input end is connected with the reference voltage V REF The output end is connected with the feedforward ripple circuit and the grid electrode of the power tube; the feedforward ripple circuit, the overshoot compensation circuit, the voltage division sampling circuit and the drain electrode of the power tube are connected with the output voltage V OUT The method comprises the steps of carrying out a first treatment on the surface of the The source electrode of the power tube and the feedforward ripple circuit are connected with a power supply signal VDD; the feedforward ripple circuit, the overshoot compensation circuit and the partial pressure sampling circuit are connected with the power supply signal GND.
2. The LDO circuit of claim 1, wherein the LDO circuit is configured to provide a PN-complementary current-compensated supply ripple feedforward: in the feedforward ripple circuit, the input power supply signals are VDD and GND, and the output voltage is V OUT ；M 25 And M 26 Is PMOS tube, M 27 And M 28 NMOS tubes which form PN-type complementary structures together; m is M 25 Drain electrode of (C) and M 26 Is connected to one end of a capacitor C2, M 27 Is a source of (2)And M is as follows 28 The drain electrode of the capacitor C4 is connected with one end of the capacitor C2 and the other end of the capacitor C4 are commonly connected with the output voltage V OUT ；M 25 Is connected by a resistor R 7 And C5 LPF1, M 26 Is connected by a resistor R 8 And C6 LPF2, M 27 Is connected by a resistor R 9 And C7 LPF3, M 28 Is connected by a resistor R 10 And LPF4 composed of C8; LPF1, LPF2, LPF3, and LPF4 are connected to bias voltages VB1, VB2, VB3, and VB4 generated by the reference bias circuit, respectively; m is M 26 Drain electrode of (C) and M 27 The drain electrode of the power tube is connected with the grid electrode of the power tube; m is M 25 Is connected with the power supply signal VDD, M 28 One end of the source and the capacitors C5, C6, C7 and C8 are connected to the power supply signal GND.
3. The LDO circuit of claim 1, wherein the LDO circuit is configured to provide a PN-complementary current-compensated supply ripple feedforward: in the overshoot compensation circuit, the input power supply signal is GND, and the output voltage is V OUT ，M 36 Source, M of (2) 37 Source and M of (2) 40 Is connected with the output voltage V OUT ；M 36 Is short-circuited with the gate and drain of R 6 And C9 LPF and M 38 Drain electrode connection of M 37 Is connected with LPF, M 37 Drain electrode of (C) and M 39 Drain electrode of (C) and M 40 Is connected with the grid electrode; m is M 38 And M 39 Is connected with a bias voltage VB4 generated by a reference bias circuit; m is M 38 Source, M of (2) 39 Source, M of (2) 40 One ends of the source and C9 of (C) are connected to the power supply signal GND.
4. The LDO circuit of claim 1, wherein the LDO circuit is configured to provide a PN-complementary current-compensated supply ripple feedforward:
M 1 、M 2 、M 3 、M 4 、M 7 、M 8 、M 9 、M 13 、M 14 、M 15 、M 16 、M 21 、M 24 、M 25 、M 26 、M 29 、M 34 、M 35 、M 36 、M 37 、M 41 、M P is a PMOS transistor; m is M 5 、M 6 、M 10 、M 11 、M 12 、M 17 、M 18 、M 19 、M 20 、M 22 、M 23 、M 27 、M 28 、M 30 、M 31 、M 32 、M 33 、M 38 、M 39 、M 40 、M 42 Is an NMOS transistor; wherein M is 1 、M 2 、M 9 、M 13 、M 14 、M 21 、M 24 、M 25 、M 29 、M 34 、M P Is connected to VDD; m is M 5 、M 12 、M 19 、M 20 、M 22 、M 23 、M 28 、M 32 、M 33 、M 38 、M 39 、M 40 Is connected with GND; all PMOS substrates are connected with VDD, and all NMOS substrates are connected with GND;
M 1 is short-circuited with the drain and gate of M 2 Gate, M of (2) 3 Source and M of (2) 29 Is connected with the grid electrode of the power supply; m is M 2 Drain electrode of (C) and M 4 Is connected with the source electrode of the transistor; m is M 4 Is short-circuited with the drain and is M 3 Gate, M of (2) 6 Is connected with the drain electrode of the transistor; m is M 5 Is short-circuited with the drain and is M 3 Drain electrode of M 6 Is connected with the grid electrode of the power supply; r is R 5 And M 6 The other end is connected with R 11 R is one end of 11 The other end is connected with GND; m is M 9 Gate electrode of VB1, M 9 Drain electrode is respectively connected with M 7 Source, M of (2) 8 Source, M of (2) 41 Is connected with the drain electrode; m is M 41 The grid electrode of the power supply is connected with the power supply VDD; m is M 7 Gate and M of (2) 10 The grid electrode of (C) is all equal to V FB Are connected; m is M 8 Gate and M of (2) 11 The grid electrode of (C) is all equal to V REF Are connected; m is M 12 Gate electrode of VB4, M 12 Drain electrode of (a) is respectively with M 10 Source, M of (2) 11 Source, M of (2) 42 Is connected with the drain electrode; m is M 42 Is connected with GND; m is M 13 Gate and M of (2) 14 Gate, M of (2) 15 Drain electrode of M 17 Drain electrode of (C) and M 24 Is connected with the grid electrode of the power supply; m is M 13 Drain electrode of (C) and M 15 Source and M of (2) 10 Is connected with the drain electrode of the transistor; m is M 14 Drain electrode of (C) and M 16 Source and M of (2) 11 Is connected with the drain electrode of the transistor; m is M 15 Gate and M of (2) 16 The gates of the (C) are connected with VB2; m is M 16 Drain electrode of (C) and M 18 Drain electrode of (C) and M 21 Is connected with the grid electrode of the power supply; m is M 17 Gate and M of (2) 18 The grid electrodes of the (C) are connected with VB3; m is M 17 Source electrode of (C) and M 19 Drain electrode of (C) and M 7 Is connected with the drain electrode of the transistor; m is M 18 Source electrode of (C) and M 8 Drain electrode of (C) and M 20 Is connected with the drain electrode of the transistor; m is M 19 Gate and M of (2) 20 The gates of the (C) are connected with VB4; m is M 22 Is short-circuited with the gate and drain of M 23 Gate, M of (2) 21 Is connected with the drain electrode of the transistor; m is M 23 Drain electrode of (C) and M 24 Is connected with the drain electrode of the transistor; m is M 30 Gate, M of (2) 31 Gate, M of (2) 29 Drain electrode and R of (2) 3 Is connected with VB3 at one end; r is R 3 And M at the other end of (2) 31 Drain electrode of M 32 Gate and M of (2) 33 The gates of the (C) are connected with VB4; m is M 31 Source and M of (2) 32 Is connected with the drain electrode of the transistor; m is M 30 Source and M of (2) 33 Is connected with the drain electrode of the transistor; m is M 34 Drain electrode of (C) and M 35 Is connected with the source electrode of the transistor; m is M 34 Gate, M of (2) 35 Drain electrode and R of (2) 4 Is connected with VB1 at one end; r is R 4 Is the other end of M 30 Drain electrode of (C) and M 35 The gates of the (C) are connected with VB2;
M 25 gate and resistor R of (2) 7 Is connected to one end of capacitor C5, R 7 The other end of (2) is connected with VB1, and the other end of C5 is connected with GND; m is M 26 Gate and resistor R of (2) 8 Is connected to one end of a capacitor C6, R 8 The other end of the C6 is connected with VB2 and the other end of the C6 is connected with GND; m is M 27 Gate and resistor R of (2) 9 Is connected to one end of capacitor C7, R 9 The other end of C7 is connected with VB3 and the other end is connected with GND; m is M 28 Gate and resistor R of (2) 10 One end of (2)Connected with one end of a capacitor C8, R 10 The other end of the C8 is connected with VB4 and the other end of the C8 is connected with GND; m is M 36 Is short-circuited with the gate and drain of M 38 Drain of (d) and resistance R 6 Is connected with one end of the connecting rod; r is R 6 And M at the other end of (2) 37 Is connected with one end of a capacitor C9; the other end of the capacitor C9 is connected with GND; m is M 37 Source of (V) and V OUT Are connected; m is M 38 Gate and M of (2) 39 The gates of (2) are connected with VB4; m is M 37 Drain electrode of (C) and M 39 Drain electrode of (C) and M 40 Is connected with the grid electrode of the power supply; m is M 40 Drain electrode of M 36 Source, M of (2) P Are all connected with V OUT The method comprises the steps of carrying out a first treatment on the surface of the One end of C1 is connected with M 13 The other end of C1 is connected with V OUT ；M 25 Drain electrode of (C) and M 26 Is connected with one end of a capacitor C2, and the other end of the capacitor C2 is connected with V OUT ；M 26 Drain electrode of (C) and M 27 Drain electrode of M P Gate, M of (2) 24 Is connected with one end of a capacitor C3, and the other end of the capacitor C3 is connected with V OUT ；M 27 Source electrode of (C) and M 28 Is connected with one end of a capacitor C4, and the other end of the capacitor C4 is connected with V OUT The method comprises the steps of carrying out a first treatment on the surface of the Resistor R 1 One end of (2) is connected with V OUT ，R 1 And V at the other end of (2) FB And R is 2 Is connected with one end of the connecting rod; r is R 2 The other end of (2) is connected with GND.
CN202310068819.0A 2023-01-18 2023-01-18 LDO circuit based on PN complementary current compensation power supply ripple feedforward Pending CN116225118A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116719382A (en) * 2023-08-09 2023-09-08 成都通量科技有限公司 High PSR's off-chip capacitor LDO circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116719382A (en) * 2023-08-09 2023-09-08 成都通量科技有限公司 High PSR's off-chip capacitor LDO circuit
CN116719382B (en) * 2023-08-09 2023-11-03 成都通量科技有限公司 High PSR's off-chip capacitor LDO circuit

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