CN116560446A - Full-integrated LDO circuit for high-current application and working method thereof - Google Patents
Full-integrated LDO circuit for high-current application and working method thereof Download PDFInfo
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- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
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- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
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Abstract
A full-integrated LDO circuit for high-current application and a working method thereof are provided, wherein the full-integrated LDO circuit comprises a main loop and an auxiliary loop; the main loop comprises a first operational amplifier, a second power tube, a feedback module and a load resistor, and the auxiliary loop comprises the second operational amplifier and the first power tube; the negative input end of the first operational amplifier is connected with feedback voltage, the output ends of the first operational amplifier and the second operational amplifier are both connected to the grid end of the second power tube, the grid ends of the first power tube and the second power tube are connected, and the drain ends of the first power tube and the second power tube are connected and then input voltage; the negative input end of the second operational amplifier is connected with the source end of the first power tube; the source end of the second power tube is an output end of the LDO circuit; based on the superposition principle, the main loop and the auxiliary loop respond simultaneously in frequency; when the main loop gain is greater than the auxiliary loop, the LDO circuit gain characteristic is consistent with the main loop gain characteristic; otherwise, the LDO circuit gain characteristic is consistent with the auxiliary loop gain characteristic. The invention improves the stability and transient response capability of the circuit.
Description
Technical Field
The invention belongs to the technical field of analog integrated circuit power management, and particularly relates to a full-integrated LDO (low dropout regulator) circuit for high-current application and a working method thereof.
Background
With the development of the current society and technology level, the demand of portable terminal devices is continuously increased, and the portable terminal devices are widely applied to the production work and daily life of people. In the field of electronic systems, products in the power management chip market are not only developed toward miniaturization, low power consumption and intelligence, but also pay more attention to stability and high drivability. In various power management chips, low dropout regulators (low dropout regulator, LDOs) are widely used in various integrated circuits to provide stable voltages by virtue of their simple structure, low cost, high power ripple rejection capability, low output noise, and fast transient response.
In the prior art, the LDO needs to be externally connected with a larger output capacitor to play roles in filtering and voltage stabilization, and the equivalent series resistance of the capacitor can provide a zero point for the circuit to compensate the circuit. However, since the large output capacitor occupies a large area, additional pins are designed for the off-chip output capacitor even if the off-chip output capacitor is not placed in the chip, and the design cost is increased. With the development of integrated circuits, the requirements on the output current capability of a power management chip are higher and higher, the requirements on the output large current capability are met, a power tube with a larger size is required by an LDO, the capacitance of the grid end of the power tube is hundreds of pF, and the combination of not using an off-chip capacitor provides higher challenges for the stability and transient response capability of the LDO.
Disclosure of Invention
In order to solve the defects in the prior art, the invention provides a fully integrated LDO circuit for high-current application and a working method thereof, an auxiliary loop is added to compensate the frequency response of the circuit, and the transient response capability of the circuit is enhanced by using an adaptive bias technology, so that the circuit has better stability and transient response capability.
The invention adopts the following technical scheme.
The invention provides a full-integrated LDO circuit for high-current application, which comprises a main loop, wherein the main loop comprises an error amplifier, a second power tube, a feedback module and a load resistor, and when the output voltage of the LDO circuit fluctuates due to the change of the load resistor, the main loop reduces the gate end voltage of the second power tube according to the feedback voltage output by the feedback module;
the LDO circuit includes: an auxiliary loop; the error amplifier comprises a first operational amplifier, and the auxiliary loop comprises a second operational amplifier and a first power tube;
the positive input end of the first operational amplifier is connected with a reference voltage, the negative input end of the first operational amplifier is connected with a feedback voltage, the output ends of the first operational amplifier and the second operational amplifier are both connected to the gate end of the second power tube, the first power tube is connected with the gate end of the second power tube, and the drain ends of the first power tube and the second power tube are connected with each other to input the voltage; the positive input end of the second operational amplifier is grounded, and the negative input end of the second operational amplifier is connected with the source end of the first power tube; the source end of the second power tube is the output end of the LDO circuit;
based on the superposition principle, the main loop and the auxiliary loop simultaneously perform frequency response; when the gain of the main loop is larger than that of the auxiliary loop, the gain characteristic of the LDO circuit is consistent with that of the main loop; when the main loop gain is not greater than the auxiliary loop gain, the gain characteristic of the LDO circuit is consistent with the gain characteristic of the auxiliary loop.
The main loop further includes: an adaptive bias module; the error amplifier further includes a bias current source;
the input end of the detection module is connected with the output end of the first operational amplifier, and the output end of the detection module is connected with the control end of the bias current source; the detection module increases the current of the bias current source when detecting the output voltage decrease, and the bandwidth of the first operational amplifier increases.
The first power tube is used for duplicating the gate terminal voltage of the second power tube.
The auxiliary loop also comprises an auxiliary resistor, an auxiliary capacitor and a current source;
the negative input end of the second operational amplifier is connected with one end of the auxiliary resistor and one end of the auxiliary capacitor, the other end of the auxiliary resistor is connected with the ground, and the source end of the first power tube is connected with the other end of the auxiliary capacitor and the current source.
The first operational amplifier comprises first to eleventh MOS transistors M 1 、M 2 、M 3 、M 4 、M 5 、M 6 、M 7 、M 8 、M 9 、M 10 、M 11 First capacitor C 1 Wherein M is 1 Gate terminal reference voltage V REF ，M 1 Source terminal and M 2 The source ends are all connected with M 11 Drain terminal, M 1 Drain terminal and M 5 The drain ends are all connected with M 3 Source end, M 2 Gate end feedback voltage V FB ，M 2 Drain terminal and M 6 The drain ends are all connected with M 4 Source end, M 3 Gate terminal and M 4 The gate terminals are all connected with the first bias voltage V b1 ，M 5 Gate terminal and M 6 The gate terminals are all connected with a third bias voltage V b3 ，M 5 Source terminal and M 6 The source ends are all grounded, M 3 Drain terminal and M 7 Drain terminal, M 9 Gate end, M 10 Gate ends are all connected with each other, M 4 Drain terminal and M 8 The drain terminal is connected with the output terminal of the first operational amplifier EA1, and the output voltage is V OUT，EA ，M 7 Gate end, M 8 Gate terminal and M 11 The gate terminals are all connected with the second bias voltage V b2 ，M 7 Source terminal M 9 Drain terminal, M 8 Source terminal M 10 Drain terminal, M 9 Source terminal and M 10 Source terminal and M 11 The source terminals are connected with a power supply voltage VDD; c (C) 1 Is connected with M 6 Drain terminal, C 1 Is connected with the other end M 4 And a drain terminal.
The auxiliary loop includes: second operational amplifier, fifteenth MOS tube M 15 Sixteenth MOS tube M 16 The method comprises the steps of carrying out a first treatment on the surface of the Wherein the second operational amplifier comprises third to tenth MOS transistors M 3 、M 4 、M 5 、M 6 、M 7 、M 8 、M 9 、M 10 Twelfth to fourteenth MOS transistor M 12 、M 13 、M 14 Auxiliary resistor R F Auxiliary capacitor C F The method comprises the steps of carrying out a first treatment on the surface of the Wherein M is 12 Gate terminal and auxiliary capacitor C F One end of (2) auxiliary resistor R F Is connected with one end of M 12 Drain terminal M 6 Drain terminal, M 12 Source terminal and M 13 The source ends are all connected with M 14 Drain terminal, M 13 Drain terminal and auxiliary resistor R F Is the other end of M 15 The source ends are all grounded, M 15 Drain terminal M 5 Drain terminal, M 14 Source terminal and M 16 The drain terminals are connected with the power supply voltage VDD, M 14 The gate terminal is connected with a second bias voltage V b2 ，M 15 Drain terminal connection auxiliary capacitor C F And M at the other end of (2) 16 Source end, M 15 The gate terminal is connected with a first bias voltage Vb1, M 16 The gate terminal is connected with the output terminal of the first operational amplifier EA 1.
The first operational amplifier and the second operational amplifier share the third to tenth MOS transistors to form a folding common-source common-gate structure.
The self-adaptive bias module comprises seventeenth to twenty-first MOS tubes M 17 、M 18 、M 19 、M 20 、M ab Wherein M is 17 Gate and drain and M 19 Drain terminal, M 18 Gate end is connected with M 17 Source terminal and M 18 Source terminal and M ab The source terminals are connected with the power supply voltage VDD, M 18 Drain terminal, M 20 Gate end, M 20 Source terminal and M ab Gate end is connected with M 19 The gate end is connected with the output end of the first operational amplifier EA1, M 19 Source terminal and M 20 The source ends are all grounded, M ab M in drain and first operational amplifier EA1 1 The source ends are connected.
M 19 The gate terminal is connected with the gate terminal of the second power tube, and when the load current becomes smaller, the first operational amplifier outputs the voltage V OUT，EA Decline, M 19 The voltage at the gate terminal drops by M 17 And M 18 The composed current mirror responds to changes in voltage to M 20 Is the drain voltage V of (2) ab ，V ab With V OUT，EA Descending to decrease when V ab Decline, M ab The gate terminal voltage drops and the bias current source current increases.
The auxiliary resistor and the auxiliary capacitor form an RC high-pass loop, M is static 16 The voltage at the gate terminal is constant, and the current passes through M 15 The RC high-pass loop does not pass current, and the voltage of the input end of the second operational amplifier is 0; when the voltage of the gate terminal of the second power tube changes, M 16 The voltage of the gate terminal changes with the change, and current flows through the RC high-pass loop, M 12 The voltage at the gate terminal fluctuates, and the first operational amplifier is changed by folding the common-source common-gate structureOutput voltage V of the amplifier OUT，EA 。
The second power tube is an NMOS power tube.
The invention also provides a working method of the full-integrated LDO circuit facing the heavy current application, which comprises the following steps: when the output voltage is increased, in the main loop, the feedback voltage output by the feedback module is increased, the voltage of the negative input end of the first operational amplifier is increased, the output voltage of the first operational amplifier is reduced, the voltage of the gate end of the second power tube is reduced, and the output voltage is reduced; meanwhile, in the auxiliary loop, under the action of the parasitic capacitance of the gate end of the second power tube, the gate end voltage of the second power tube rises along with the increase of the output voltage, the first power tube replicates the gate end voltage of the second power tube, the source end voltage of the first power tube rises, so that the negative input end voltage of the second operational amplifier rises, the output voltage of the second operational amplifier decreases, and the gate end voltage of the second power tube decreases along with the increase of the output voltage; the detection module increases the current of the bias current source when detecting a decrease in the output voltage.
Compared with the prior art, the LDO circuit has the advantages that the auxiliary loop is constructed, the auxiliary loop and the main loop are used for processing voltage fluctuation together, the frequency response of the circuit is compensated, and particularly when the gain of the main loop is lower than that of the auxiliary loop, the auxiliary loop is used for frequency compensation, so that the phase margin of the whole circuit is improved, and the stability of the circuit is improved. The auxiliary loop circuit provided by the invention is simple and is built together with the error amplifier, so that the use of devices is reduced, and the chip area is saved.
The invention constructs the self-adaptive bias module, when detecting the output voltage V OUT When the output voltage is reduced, the current of the bias current source is increased, so that the bandwidth of the error amplifier is increased, the output voltage fluctuation caused by load switching is processed, the transient response speed during output load switching is increased, and the stability and the accuracy of the output voltage are improved. And the self-adaptive bias module is constructed with the error amplifier, so that the use of devices is reduced, and the area of a chip is saved.
The LDO circuit provided by the invention uses the NMOS power tube with the gate-source voltage not influenced by input voltage ripple, and can improve the power supply rejection ratio of the circuit.
The LDO circuit provided by the invention does not use an off-chip large capacitor, is convenient to integrate, and can provide a large load current of up to 3A.
Drawings
FIG. 1 is a schematic diagram of a fully integrated LDO circuit for high current applications according to the present invention;
the reference numerals in fig. 1 are explained as follows:
the system comprises a 1-error amplifier, a 2-self-adaptive bias module, a 3-auxiliary loop, a 4 a-first power tube, a 4 b-second power tube, a 5-feedback module and a 6-detection module;
FIG. 2 is a schematic circuit diagram of an error amplifier in a fully integrated LDO circuit for high current applications according to the present invention;
FIG. 3 is a schematic circuit diagram of an auxiliary loop in a fully integrated LDO circuit for high current applications according to the present invention;
FIG. 4 is a schematic circuit diagram of an adaptive bias module and a feedback module in a fully integrated LDO circuit for high current application according to the present invention;
fig. 5 is a schematic diagram of a frequency response of a fully integrated LDO circuit for high current applications according to an embodiment of the present invention.
FIG. 6 is a transient response simulation curve of a fully integrated LDO circuit for high current applications in an embodiment of the present invention.
FIG. 7 is a frequency response simulation curve of a fully integrated LDO circuit for high current applications in an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. The embodiments described herein are merely some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art without inventive faculty, are within the scope of the invention, based on the spirit of the invention.
The invention provides a full-integrated LDO circuit for high-current application, as shown in FIG. 1, comprising: main loop, auxiliary loop 3, second power tube 4b, load resistor R L The method comprises the steps of carrying out a first treatment on the surface of the The main loop includes: error amplifier 1, adaptive bias module 2, second power tube 4b, feedback module 5 and load resistance RL.
Wherein the error amplifier 1 comprises a first operational amplifier EA1 and a bias current source S 1 The adaptive bias module 2 comprises a detection module 6, and the auxiliary loop 3 comprises a second operational amplifier EA2 and an auxiliary resistor R F Auxiliary capacitor C F Current source S 2 And a first power tube 4a, the feedback module 5 comprises a first resistor R 1 And a second resistor R2. When the output voltage of the LDO circuit fluctuates due to the change of the load resistance, the main loop reduces the gate end voltage of the second power tube according to the feedback voltage output by the feedback module.
Specifically, as shown in FIG. 1, the positive input of the first operational amplifier EA1 is connected to the reference voltage V REF The output end A of the first operational amplifier EA1 and the output end B of the second operational amplifier EA2 are both connected to the gate end of the second power tube 4B, the gate ends of the first power tube 4a and the second power tube 4B are connected, and the drain ends of the first power tube 4a and the second power tube 4B are connected and then input with the voltage V IN The method comprises the steps of carrying out a first treatment on the surface of the The source end of the second power tube 4b is connected with the first resistor R 1 One end of the load resistor RL and one end of the first resistor R 1 The other end D of the first operational amplifier EA1 is connected with the negative input end and the second resistor R 2 One end of (2) a second resistor R 2 And a load resistor R L The other ends of the two electrodes are grounded; the input end of the detection module 6 is connected with the output end A of the first operational amplifier EA1, and the output end of the detection module 6 is connected with the bias current source S 1 Is connected with the control end of the control end; the positive input end of the second operational amplifier EA2 is grounded, and the negative input end of the second operational amplifier EA2 is connected with the auxiliary resistor R F And auxiliary capacitor C F An auxiliary resistor R F The other end of the first power tube 4a is connected with the auxiliary capacitor C F And the other end of (2) and a current source S 2 The method comprises the steps of carrying out a first treatment on the surface of the The source end of the second power tube 4b is the output end of the fully integrated LDO, and the output end is connected with the load resistor R L Is output voltage V OUT The method comprises the steps of carrying out a first treatment on the surface of the The first power tube 4a is used for duplicating the gate terminal voltage of the second power tube 4 b.
When outputting voltage V OUT The main loop and the auxiliary loop handle the voltage fluctuation together, and the auxiliary loop becomes the main loop of the circuit at high frequency, namely, the auxiliary loop is used for mainly compensating the frequency, and the main loop is used for carrying out auxiliary compensation on the frequency, so that a main loop with high gain needs to be constructed. In the prior art, the gain is high, the bandwidth is small, and the phase margin is low. Therefore, the invention constructs an auxiliary loop with low gain, large bandwidth and high phase margin, and when the gain of the main loop is lower than that of the auxiliary loop, the auxiliary loop is used for frequency compensation, thereby improving the phase margin of the whole circuit. The invention compensates the circuit by using the auxiliary loop, and changes the voltage of the input end of the power tube after the fluctuation is processed to achieve the effect of stabilizing the output voltage of the power tube.
Specifically, when the main loop and the auxiliary loop jointly handle voltage fluctuations, the output voltage V OUT The output voltage of the feedback module is increased, the voltage of the negative input end of the first operational amplifier EA1 is increased, the output voltage of the first operational amplifier EA1 is reduced, the voltage of the gate end of the second power tube is reduced, and the output voltage V OUT And then decrease; meanwhile, in the auxiliary loop, under the action of parasitic capacitance of the gate end of the second power tube, the gate end voltage of the second power tube is along with the output voltage V OUT The voltage of the gate end of the second power tube is copied by the first power tube, so that the voltage of the negative input end of the second operational amplifier EA2 is increased, the output voltage of the second operational amplifier EA2 is reduced, the voltage of the gate end of the second power tube is reduced, and the output voltage V is obtained OUT And consequently decreases.
Further, due to the larger gate-source capacitance of the second power tube and the limited bandwidth of the error amplifier, when the load resistor R L When the voltage is changed, a large output voltage V is caused OUT The detection module detects the fluctuation of the output voltage V OUT When the current is reduced, the current of the bias current source is increased, thereby increasing the bandwidth of the error amplifier, and the load is switchedOutput voltage V of (2) OUT The fluctuation is processed, and transient response capability is improved.
As shown in fig. 2, the first operational amplifier EA1 includes first to eleventh MOS transistors M 1 、M 2 、M 3 、M 4 、M 5 、M 6 、M 7 、M 8 、M 9 、M 10 、M 11 First capacitor C 1 Wherein M is 1 Gate terminal reference voltage V REF ，M 1 Source terminal and M 2 The source ends are all connected with M 11 Drain terminal, M 1 Drain terminal and M 5 The drain ends are all connected with M 3 Source end, M 2 Gate end feedback voltage V FB ，M 2 Drain terminal and M 6 The drain ends are all connected with M 4 Source end, M 3 Gate terminal and M 4 The gate terminals are all connected with the first bias voltage V b1 ，M 5 Gate terminal and M 6 The gate terminals are all connected with a third bias voltage V b3 ，M 5 Source terminal and M 6 The source ends are all grounded, M 3 Drain terminal and M 7 Drain terminal, M 9 Gate end, M 10 Gate ends are all connected with each other, M 4 Drain terminal and M 8 The drain terminal is connected with the output terminal of the first operational amplifier EA1, and the output voltage is V OUT，EA ，M 7 Gate end, M 8 Gate terminal and M 11 The gate terminals are all connected with the second bias voltage V b2 ，M 7 Source terminal M 9 Drain terminal, M 8 Source terminal M 10 Drain terminal, M 9 Source terminal and M 10 Source terminal and M 11 The source terminals are connected with the power supply voltage VDD. C (C) 1 Is connected with M 6 Drain terminal, C 1 Is connected with the other end M 4 And a drain terminal.
As shown in fig. 2 and 3, the auxiliary loop includes: second operational amplifier EA2, fifteenth MOS tube M 15 Sixteenth MOS tube M 16 Wherein the second operational amplifier EA2 comprises third to tenth MOS transistors M 3 、M 4 、M 5 、M 6 、M 7 、M 8 、M 9 、M 10 Twelfth to fourteenth MOS transistor M 12 、M 13 、M 14 Auxiliary resistor R F Auxiliary capacitor C F The method comprises the steps of carrying out a first treatment on the surface of the Wherein M is 12 Gate terminal and assistCapacitor C F One end of (2) auxiliary resistor R F Is connected with one end of M 12 Drain terminal M 6 Drain terminal, M 12 Source terminal and M 13 The source ends are all connected with M 14 Drain terminal, M 13 Drain terminal and auxiliary resistor R F Is the other end of M 15 The source ends are all grounded, M 15 Drain terminal M 5 Drain terminal, M 14 Source terminal and M 16 The drain terminals are connected with the power supply voltage VDD, M 14 The gate terminal is connected with a second bias voltage V b2 ，M 15 Drain terminal connection auxiliary capacitor C F And M at the other end of (2) 16 Source end, M 15 The gate terminal is connected with a first bias voltage Vb1, M 16 The gate terminal is connected with the output terminal of the first operational amplifier EA 1.
Further, the first operational amplifier EA1 and the second operational amplifier EA2 share the third to tenth MOS transistors to form a folded cascode structure.
As shown in fig. 2 and 4, the adaptive bias module includes seventeenth to twenty-first MOS transistors M 17 、M 18 、M 19 、M 20 、M ab Wherein M is 17 Gate and drain and M 19 Drain terminal, M 18 Gate end is connected with M 17 Source terminal and M 18 Source terminal and M ab The source terminals are connected with the power supply voltage VDD, M 18 Drain terminal, M 20 Gate end, M 20 Source terminal and M ab Gate end is connected with M 19 The gate end is connected with the output end of the first operational amplifier EA1, M 19 Source terminal and M 20 The source ends are all grounded, M ab M in drain and first operational amplifier EA1 1 The source ends are connected. Use of I in simulation LOAD The current source characterizes the load current.
M19 is used for detecting output voltage V OUT Whether there is a surge. The invention proposes to add an adaptive bias module to the error amplifier, M 19 The gate terminal is connected with the gate terminal of the second power tube, i.e. with the output terminal of the first operational amplifier, when the load current becomes smaller, the output voltage V of the first operational amplifier OUT，EA Decline, M 19 The voltage at the gate terminal drops by M 17 And M 18 The composed current mirror responds to changes in voltage to M 20 Is connected with the drain terminal of (1)Voltage V ab ，V ab With V OUT，EA Descending to decrease when V ab Decline, M ab The voltage of the gate terminal is reduced, the bias current source current is increased, the bandwidth of the error amplifier is improved, and the transient response capability of the error amplifier is enhanced.
Further, the second power tube 4b is an NMOS power tube. The gate-source voltage of the second power tube is not influenced by input voltage ripple, and the power supply rejection ratio of the circuit can be improved.
As shown in fig. 4, the feedback module includes a first resistor R 1 And a second resistor R 2 Wherein R is 1 Is connected with the source end of the second power tube 4b, R 1 Another termination resistor R of (a) 2 Is output by a feedback module FB Connect M 2 Gate end, R 2 The other end of which is grounded.
The gain of the main loop is the gain A of the first operational amplifier V The following is shown:
A V ＝g m R OUT
g m ≈g m1
R OUT ≈[(g m3 +g mb )r O3 (r O1 ||r O5 )]||[(g m7 +g mb7 )r O7 r O9 ]
in the method, in the process of the invention,
g m for the equivalent transconductance of the first operational amplifier,
R OUT for the equivalent output impedance of the first operational amplifier,
g m1 、g m3 、g m7 respectively MOS tube M 1 、M 3 、M 7 Is used to control the transconductance of the optical fiber,
g mb3 、g mb7 respectively MOS tube M 3 ，M 7 Is a bulk-effect equivalent transconductance of (c),
r O1 、r O3 、r O5 、r O7 、r O9 respectively MOS tube M 1 、M 3 、M 7 、M 9 Is a function of the output impedance of the circuit.
The main loop dominant pole p0 is as follows:
p0＝R OUT C GG
wherein C is GG Parasitic capacitance is formed at the gate end of the second power tube.
When the output end of the fully integrated LDO circuit is connected with a capacitive load or an output capacitor, the secondary pole point p1 is as follows:
p1＝R L C L
wherein R is L For the load resistance, C L Is the load capacitance.
It can be seen that the secondary pole will move with the load at the output of the LDO.
Based on the superposition principle, the main loop and the auxiliary loop simultaneously perform frequency response; when the gain of the main loop is larger than that of the auxiliary loop, the gain characteristic of the LDO circuit is consistent with that of the main loop; when the main loop gain is not greater than the auxiliary loop gain, the gain characteristic of the LDO circuit is consistent with the gain characteristic of the auxiliary loop.
The main loop frequency response is characterized by a high gain and a narrow bandwidth, and the auxiliary loop frequency response is characterized by a low gain and a wide bandwidth.
As shown in fig. 1 and 3, the positive input terminal of the second operational amplifier EA2 is grounded, and the negative input terminal is connected to the auxiliary resistor R F And auxiliary capacitor C F In the RC high-pass loop, M is at rest 16 The voltage at the gate terminal is constant, and the current passes through M 15 In ground, no current passes through the RC high-pass loop, the input (M 12 Gate terminal) voltage is 0; when the voltage of the gate terminal of the second power tube changes, M 16 The voltage of the gate terminal changes with the change, and current flows through the RC high-pass loop, M 12 The voltage at the gate terminal fluctuates, and the output voltage V of the first operational amplifier is changed by folding the cascode structure OUT，EA The output voltage of the LDO circuit is changed through the second operational amplifier
As shown in FIG. 2, at M 4 Drain and source terminal of the capacitor C 1 Increasing the equivalent capacitance C of the output end of the first operational amplifier by the Miller effect OUT So that the loop dominant pole p0 is closer to the origin and farther awayAnd the secondary pole p1 is separated, so that loop stability is improved.
The invention also provides a working method of the full-integrated LDO circuit facing the heavy current application, which comprises the following steps:
when the output voltage is increased, in the main loop, the feedback voltage output by the feedback module is increased, the voltage of the negative input end of the first operational amplifier is increased, the output voltage of the first operational amplifier is reduced, the voltage of the gate end of the second power tube is reduced, and the output voltage is reduced; meanwhile, in the auxiliary loop, under the action of parasitic capacitance of the gate end of the second power tube, the gate end voltage of the second power tube rises along with the increase of the output voltage, and the first power tube replicates the gate end voltage of the second power tube, so that the voltage of the negative input end of the second operational amplifier rises, the output voltage of the second operational amplifier decreases, the gate end voltage of the second power tube decreases, and the output voltage decreases along with the increase of the output voltage;
when the detection module detects that the output voltage fluctuates, the current of the bias current source is increased, so that the bandwidth of the error amplifier is increased, and the output voltage V caused by load switching is increased OUT The fluctuation is processed, and transient response capability is improved.
FIG. 5 is a schematic diagram showing the frequency response of a fully integrated LDO circuit for high current application, wherein the solid line shows the frequency response of the main loop, the dotted line shows the frequency response of the auxiliary loop, the main loop and the auxiliary loop can obtain the overall frequency response of the double loop by using the superposition principle, the main loop is dominant in the low-frequency band, the overall frequency response is mainly the frequency response of the main loop, the main loop gain G is reduced at the speed of 40dB per ten times after the frequency is higher than the frequency of the secondary point p1, and the main loop gain is still higher than the auxiliary loop, so the main loop still occupies the dominant position of the frequency response of the double loop until the main loop and the auxiliary loop gain intersect at the frequency point omega in the graph z At omega z After the point, the auxiliary loop takes over the main loop to conduct overall frequency response of the double loop, the gain reduction speed is returned to 20dB per ten times of frequency from 40dB per ten times of frequency, and finally the point of 0dB is traversed, so that the phase margin and the stability of the circuit are improved.
For the inventionThe proposed full-integrated LDO circuit for high-current application is subjected to simulation test, FIG. 6 is a transient response simulation curve, and it can be seen from FIG. 6 that the load current changes from 100mA to 3A and from 3A to 100mA at a speed of 1A/mu s, and the output voltage V OUT The overshoot voltage was 72mV and the undershoot voltage was 53mV. The frequency response under different load conditions is shown in FIG. 7, where the LDO circuit outputs a maximum output current I OUT The phase margin is 94.41 ° when the LDO circuit is idle, i.e. outputting current I =3a OUT Phase margin=0 is 111.79 °.
The invention provides a full-integrated LDO circuit for high-current application, which adopts a mode of adding an auxiliary loop and a self-adaptive bias module, ensures the stability of a full current range under the condition of outputting the highest 3A load current, and improves the rapid transient response when the load current is rapidly changed.
Finally, it should be noted that the above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the above embodiments, it should be understood by those skilled in the art that: modifications and equivalents may be made to the specific embodiments of the invention without departing from the spirit and scope of the invention, which is intended to be covered by the claims.
Claims (12)
1. The full-integrated LDO circuit for high-current application comprises a main loop, wherein the main loop comprises an error amplifier, a second power tube, a feedback module and a load resistor, when the output voltage of the LDO circuit fluctuates due to the change of the load resistor, the main loop reduces the gate terminal voltage of the second power tube according to the feedback voltage output by the feedback module,
the LDO circuit includes: an auxiliary loop; the error amplifier comprises a first operational amplifier, and the auxiliary loop comprises a second operational amplifier and a first power tube;
the positive input end of the first operational amplifier is connected with a reference voltage, the negative input end of the first operational amplifier is connected with a feedback voltage, the output ends of the first operational amplifier and the second operational amplifier are both connected to the gate end of the second power tube, the first power tube is connected with the gate end of the second power tube, and the drain ends of the first power tube and the second power tube are connected with each other to input the voltage; the positive input end of the second operational amplifier is grounded, and the negative input end of the second operational amplifier is connected with the source end of the first power tube; the source end of the second power tube is the output end of the LDO circuit;
based on the superposition principle, the main loop and the auxiliary loop simultaneously perform frequency response; when the gain of the main loop is larger than that of the auxiliary loop, the gain characteristic of the LDO circuit is consistent with that of the main loop; when the main loop gain is not greater than the auxiliary loop gain, the gain characteristic of the LDO circuit is consistent with the gain characteristic of the auxiliary loop.
2. The high current application oriented fully integrated LDO circuit of claim 1, wherein,
the main loop further includes: an adaptive bias module; the error amplifier further includes a bias current source;
the input end of the detection module is connected with the output end of the first operational amplifier, and the output end of the detection module is connected with the control end of the bias current source; the detection module increases the current of the bias current source when detecting the output voltage decrease, and the bandwidth of the first operational amplifier increases.
3. The high current application oriented fully integrated LDO circuit of claim 1, wherein,
the first power tube is used for duplicating the gate terminal voltage of the second power tube.
4. The high current application oriented fully integrated LDO circuit of claim 1, wherein,
the auxiliary loop also comprises an auxiliary resistor, an auxiliary capacitor and a current source;
the negative input end of the second operational amplifier is connected with one end of the auxiliary resistor and one end of the auxiliary capacitor, the other end of the auxiliary resistor is connected with the ground, and the source end of the first power tube is connected with the other end of the auxiliary capacitor and the current source.
5. The high current application oriented fully integrated LDO circuit of claim 1, wherein,
the first operational amplifier comprises first to eleventh MOS transistors M 1 、M 2 、M 3 、M 4 、M 5 、M 6 、M 7 、M 8 、M 9 、M 10 、M 11 First capacitor C 1 Wherein M is 1 Gate terminal reference voltage V REF ，M 1 Source terminal and M 2 The source ends are all connected with M 11 Drain terminal, M 1 Drain terminal and M 5 The drain ends are all connected with M 3 Source end, M 2 Gate end feedback voltage V FB ，M 2 Drain terminal and M 6 The drain ends are all connected with M 4 Source end, M 3 Gate terminal and M 4 The gate terminals are all connected with the first bias voltage V b1 ，M 5 Gate terminal and M 6 The gate terminals are all connected with a third bias voltage V b3 ，M 5 Source terminal and M 6 The source ends are all grounded, M 3 Drain terminal and M 7 Drain terminal, M 9 Gate end, M 10 Gate ends are all connected with each other, M 4 Drain terminal and M 8 The drain terminal is connected with the output terminal of the first operational amplifier EA1, and the output voltage is V OUT，EA ，M 7 Gate end, M 8 Gate terminal and M 11 The gate terminals are all connected with the second bias voltage V b2 ，M 7 Source terminal M 9 Drain terminal, M 8 Source terminal M 10 Drain terminal, M 9 Source terminal and M 10 Source terminal and M 11 The source terminals are connected with a power supply voltage VDD; c (C) 1 Is connected with M 6 Drain terminal, C 1 Is connected with the other end M 4 And a drain terminal.
6. The high-current-application-oriented fully integrated LDO circuit of claim 5,
the auxiliary loop includes: second operational amplifier, fifteenth MOS tube M 15 Sixteenth MOS tube M 16 The method comprises the steps of carrying out a first treatment on the surface of the Wherein the second operational amplifier comprises third to tenth MOS transistors M 3 、M 4 、M 5 、M 6 、M 7 、M 8 、M 9 、M 10 Twelfth to fourteenth MOS transistor M 12 、M 13 、M 14 Auxiliary resistor R F Auxiliary capacitor C F The method comprises the steps of carrying out a first treatment on the surface of the Wherein M is 12 Gate terminal and auxiliary capacitor C F One end of (2) auxiliary resistor R F Is connected with one end of M 12 Drain terminal M 6 Drain terminal, M 12 Source terminal and M 13 The source ends are all connected with M 14 Drain terminal, M 13 Drain terminal and auxiliary resistor R F Is the other end of M 15 The source ends are all grounded, M 15 Drain terminal M 5 Drain terminal, M 14 Source terminal and M 16 The drain terminals are connected with the power supply voltage VDD, M 14 The gate terminal is connected with a second bias voltage V b2 ，M 15 Drain terminal connection auxiliary capacitor C F And M at the other end of (2) 16 Source end, M 15 The gate terminal is connected with a first bias voltage Vb1, M 16 The gate terminal is connected with the output terminal of the first operational amplifier EA 1.
7. The high-current-application-oriented fully integrated LDO circuit of claim 5,
the first operational amplifier and the second operational amplifier share the third to tenth MOS transistors to form a folding common-source common-gate structure.
8. The high current application oriented fully integrated LDO circuit of claim 6, wherein,
the self-adaptive bias module comprises seventeenth to twenty-first MOS tubes M 17 、M 18 、M 19 、M 20 、M ab Wherein M is 17 Gate and drain and M 19 Drain terminal, M 18 Gate end is connected with M 17 Source terminal and M 18 Source terminal and M ab The source terminals are connected with the power supply voltage VDD, M 18 Drain terminal, M 20 Gate end, M 20 Source terminal and M ab Gate end is connected with M 19 The gate end is connected with the output end of the first operational amplifier EA1, M 19 Source terminal and M 20 The source ends are all grounded, M ab M in drain and first operational amplifier EA1 1 The source ends are connected.
9. The high current application oriented fully integrated LDO circuit of claim 8,
M 19 the gate terminal is connected with the gate terminal of the second power tube, and when the load current becomes smaller, the first operational amplifier outputs the voltage V OUT，EA Decline, M 19 The voltage at the gate terminal drops by M 17 And M 18 The composed current mirror responds to changes in voltage to M 20 Is the drain voltage V of (2) ab ，V ab With V OUT，EA Descending to decrease when V ab Decline, M ab The gate terminal voltage drops and the bias current source current increases.
10. The high current application oriented fully integrated LDO circuit of claim 6, wherein,
the auxiliary resistor and the auxiliary capacitor form an RC high-pass loop, M is static 16 The voltage at the gate terminal is constant, and the current passes through M 15 The RC high-pass loop does not pass current, and the voltage of the input end of the second operational amplifier is 0; when the voltage of the gate terminal of the second power tube changes, M 16 The voltage of the gate terminal changes with the change, and current flows through the RC high-pass loop, M 12 The voltage at the gate terminal fluctuates, and the output voltage V of the first operational amplifier is changed by folding the cascode structure OUT,EA 。
11. The high current application oriented fully integrated LDO circuit of claim 1, wherein,
the second power tube is an NMOS power tube.
12. A method for operating a fully integrated LDO circuit for high current applications, adapted to the apparatus of any of claims 1-11, characterized by:
when the output voltage is increased, in the main loop, the feedback voltage output by the feedback module is increased, the voltage of the negative input end of the first operational amplifier is increased, the output voltage of the first operational amplifier is reduced, the voltage of the gate end of the second power tube is reduced, and the output voltage is reduced; meanwhile, in the auxiliary loop, under the action of the parasitic capacitance of the gate end of the second power tube, the gate end voltage of the second power tube rises along with the increase of the output voltage, the first power tube replicates the gate end voltage of the second power tube, the source end voltage of the first power tube rises, so that the negative input end voltage of the second operational amplifier rises, the output voltage of the second operational amplifier decreases, and the gate end voltage of the second power tube decreases along with the increase of the output voltage;
the detection module increases the current of the bias current source when detecting a decrease in the output voltage.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117970992A (en) * | 2024-04-01 | 2024-05-03 | 青岛元通电子有限公司 | High-precision power reference voltage source control circuit and control method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117970992A (en) * | 2024-04-01 | 2024-05-03 | 青岛元通电子有限公司 | High-precision power reference voltage source control circuit and control method |
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