CN219420790U - Hardware device for intermediate frequency modulation and signal demodulation - Google Patents

Abstract

The utility model discloses a hardware device for intermediate frequency modulation and signal modulation, which comprises an FPGA module, a DSP module and a CPLD module which are mutually connected in pairs; the FPGA module is respectively connected with the BPI flash memory, the two paths of DAC modules and the two paths of ADC modules; the DSP module is respectively connected with the DDR3 memory, the NOR flash memory and the QSPI flash memory; the CPLD module is respectively connected with the EMMC memory and the singlechip. The utility model adopts the design ideas of board card, standardization and serialization, is suitable for modulating and demodulating the intermediate frequency signals, ensures the universality, ensures the good maintainability of the equipment, and finally ensures that the hardware device meets the requirements of 177.5mm multiplied by 135mm multiplied by 2 mm.

Description

Hardware device for intermediate frequency modulation and signal demodulation

Technical Field

The utility model relates to the field of signal processing, in particular to a hardware device for intermediate frequency modulation and signal demodulation.

Background

When the frequency is divided according to the frequency, the intermediate frequency is the frequency from 300KHz to 3000KHz, and most of the frequency is used as an AM radio station; when divided by their position and action in the circuit: the IF intermediate frequency means a signal obtained by frequency-converting a high-frequency signal. In order to enable an amplifier to stably operate and reduce interference, a general receiver converts a high frequency signal into an intermediate frequency signal, and thus modulation and demodulation of the intermediate frequency signal are often used in various communication devices.

The chinese patent application No. 201610962112.4 discloses an intermediate frequency modulator, an intermediate frequency demodulator and a multi-waveform fusion device, which can also perform intermediate frequency modulation and demodulation, but each device of the device is an independent device, and is difficult to perform on-board integration, so that the device has a large volume, and is inconvenient to use in miniaturized equipment.

Disclosure of Invention

Aiming at the defects in the prior art, the hardware device for intermediate frequency modulation and signal modulation solves the problems that the existing intermediate frequency modem is large in size and inconvenient to carry out on-board integration.

In order to achieve the aim of the utility model, the utility model adopts the following technical scheme:

the hardware device for modulating and modulating signals at the intermediate frequency comprises an FPGA module, a DSP module and a CPLD module which are mutually connected in pairs;

the FPGA module is respectively connected with the BPI flash memory, the two paths of DAC modules and the two paths of ADC modules;

the DSP module is respectively connected with the DDR3 memory, the NOR flash memory and the QSPI flash memory;

the CPLD module is respectively connected with the EMMC memory and the singlechip;

the FPGA module comprises a processing chip with the model number of JFM7VX690T 20; the DSP module comprises a processor with the model number of FT-M6678N; the CPLD module comprises a processing chip with the model HWD2210MCFBGA 324;

the FPGA module performs parallel data exchange with the DSP module through a 16-bit EMIF bus; the FPGA module exchanges serial data with the DSP module through a 4-path SRIO x4 bus.

Further, the model of the BPI flash memory is JFM GL256-E56; the model of DDR3 memory is SM41J256M16M; the model of the ADC module is JAD9268; the model of the DAC module is SDA9739K; the model of the NOR flash memory is MT28EW256ABA1LJS-0SIT; the model of the singlechip is GD32E103;

the DDR3 memory is 4 pieces and is respectively connected with DDR3 EMIF interfaces of the DSP module in a hanging mode; the NOR flash memory is hung on an EMIF16 interface of the DSP module;

the ADC module is connected with the FPGA module through an LVDS interface;

the DB0 pin and the DB1 pin of the DAC module are respectively connected with the adjacent HP BANK pins of the FPGA module; the DCO pin and the DCI pin of the DAC module are respectively connected with the MRCC pin or the SRCC pin of the FPGA module; the SYNC pin of the DAC module is connected with the IO pin of the FPGA module.

Further, the system also comprises a clock module with the model of GM4526C, wherein the clock module is respectively connected with the FPGA module, the ADC module and the DAC module.

Further, the digital clock also comprises a 25MHz 1.8V COMS single-ended clock and a 125MHz HCSL differential clock; the 25MHz 1.8V COMS single-ended clock is respectively connected with a CORE CLK pin, a PASS CLK pin and a DDR CLK pin of the DSP module; the 125MHz HCSL differential clock is connected to the SRIO0_CLK pin of the DSP module.

Further, the system also comprises two paths of hundred-mega network interfaces which are respectively connected with the DSP module through an EMIF bus and an SPI interface; the Ethernet protocol stack chip model in the hundred meganet interface is CH395L chip.

Further, the system also comprises an RS422 transmitting chip which is connected with the CPLD module and has the model number of B26LV31 TF; and the RS422 receiving chip is connected with the CPLD module and is of a model B26LV32 TF.

Further, the device also comprises an isolation driver which is connected with the LVTTL pin of the FPGA module and has the model of SM 164245; and the RS232 level conversion chip is connected with the FPGA module debugging pin and has the model number of MAX3232EUE+.

The beneficial effects of the utility model are as follows: the utility model adopts the design thought of board card, standardization and serialization, is suitable for modulating and demodulating the intermediate frequency signal, ensures the universality, ensures the equipment to have good maintainability, and finally ensures that the hardware device meets the requirements of 177.5mm (length) x 135mm (width) x 2mm (plate thickness).

Drawings

FIG. 1 is a block diagram of the present hardware apparatus;

FIG. 2 is a schematic diagram of the connections of a DSP module;

fig. 3 is a schematic connection diagram of the CPLD module;

FIG. 4 is a schematic block diagram of an ADC module;

FIG. 5 is a schematic block diagram of a DAC module;

FIG. 6 is a block diagram of a clock design;

FIG. 7 is a power scheme topology;

FIG. 8 is a schematic diagram of a power-on sequence of a DSP module;

FIG. 9 is a diagram of power-on time requirements of a DSP module.

Detailed Description

The following description of the embodiments of the present utility model is provided to facilitate understanding of the present utility model by those skilled in the art, but it should be understood that the present utility model is not limited to the scope of the embodiments, and all the utility models which make use of the inventive concept are protected by the spirit and scope of the present utility model as defined and defined in the appended claims to those skilled in the art.

As shown in fig. 1, the hardware device for intermediate frequency modulation and signal demodulation comprises an FPGA module, a DSP module and a CPLD module which are connected with each other in pairs;

the FPGA module is respectively connected with the BPI flash memory, the two paths of DAC modules and the two paths of ADC modules;

the DSP module is respectively connected with the DDR3 memory, the NOR flash memory and the QSPI flash memory;

the CPLD module is respectively connected with the EMMC memory and the singlechip.

In the specific implementation process, the FPGA module receives data acquired by the ADC module, performs preprocessing and then sends the data to the DSP module for demodulation calculation, and a demodulation result is output through the network port. The FPGA module outputs intermediate frequency through the DAC module. The hardware device selects a processing chip with the model number of JFM7VX690T20, has rich internal programmable resources, is provided with 3600 multipliers, about 693120 logic units, 52.9Mb Block RAM, configurable logic units, clock management modules, PCIE, GTH and other resources, can realize high-performance digital signal processing, high-capacity logic operation and other applications, and has high-bandwidth data throughput capacity to complete preprocessing of intermediate frequency signals.

JFM7VX690T20 1-chip BPI Flash (BPI Flash memory) with 256M capacity is configured, the bit width is 16bit or 8bit, the model is JFM GL256-E56, and the packaging form is CSOP56.JFM7VX690T20 and the DSP module support a 16-bit EMIF bus for parallel data exchange between the DSP module and the FPGA module. And JFM VX690T20 and the DSP support 4 paths of SRIO x4 buses, and are used for serial high-speed data exchange between the DSP module and the FPGA module.

As shown in FIG. 2, the model number of the DSP module is FT-M6678N. And a group of SRIO x4 high-speed serial interfaces and one path of EMIF bus interfaces are connected between the DSP module and the FPGA module, and the interface is provided with a hundred meganet interface for transmitting the data after the demodulation and adjustment. FT-M6678N contains 8 FT-M66 xDSL cores (called M66x CorePac), each core has a 1GHz working main frequency, a fixed point operation capability of 32GMAC and a floating point operation capability of 16 GFLOPS. 4 DDR3SDRAM with the capacity of 4Gb are hung on the periphery of the DSP, and the memory capacity of each DSP is 2Gb. DDR3SDRAM with model SM41J256M16M is designed and used. Each DDR3SDRAM has a data bit width of 16bits, and a 64bit synchronous access interface is realized through a data bit splicing mode. The highest supported clock of 800MHz is supported by the DSP and DDR3SDRAM. The actual operating clock frequency is 667MHz. DDR3SDRAM uses a 1.5V level standard to connect to the DSP. The DSP provides a seamless DDR3 EMIF interface, so that the DSP can be directly connected with the DDR3 EMIF interface of the DSP in a hanging way. The chip is mature and risk-free.

A piece of 256Mb NOR Flash is hung on the periphery of the DSP as program solidification and parameter storage. A NOR Flash chip with the model MT28EW256ABA1LJS-0SIT (the localization model SM29LV256 MC) is selected. The DSP provides a seamless interface for the NOR Flash device, so that the interface can be directly connected with an EMIF16 interface of the DSP. The NOR Flash is accessed asynchronously by adopting a data bit width of 16bits on the hardware design. The interface level standard of the EMIF16 interface of the DSP and the Flash is 1.8V, so that the DSP can be directly connected.

In order to facilitate debugging, JTAG of the DSP adopts a single debugging mode, and JTAG is led out from a J30J socket. Meanwhile, in order to ensure the driving capability of signals, an isolation driver needs to be added at the interface end.

The boot mode of the DSP is EMIF16 boot. The EMIF16boot of C6678 is a mode that loads core0 directly from Nor Flash (must be suspended in CE0 space: 0x 70000000), the EMIF16 interface is initialized by the DSP internal Romcode, and because the EMIF16 external Nor Flash is an XIP device (i.e. can be executed on chip), execution starts directly jumping to the start address of Nor Flash. In order to move the code in Nor Flash to the L2 SRAM of core0 of C6678, a boot code needs to be written in the project to be loaded of core0, and the boot code has the function of loading the code of core0 into a memory in segments and finally jumping to an entry address to start execution. The boot code is written in assembly language, named bootload segment, placed in the first 1KB space of L2 SRAM, and written to the first 1KB space of Nor Flash, and application code placed in the address space behind 1 KB.

The CPLD functionality mainly includes the following aspects:

1. managing the power-on time sequence and reset of the DSP;

2. 1.8V level conversion to FPGA module.

As shown in FIG. 3, the CPLD module is a model HWD2210MCFBGA324, which is an "Instant-On" non-volatile CPLD. Chip density can reach 2210 logic unit (LE) and 8Kbits memory space. A greater number of I/os, higher performance, and reliable compatibility may be provided than other CPLDs. The product also has the capabilities of multi-core voltage (3.3V/2.5V/1.8V), user FLASH storage (UFM), system programming (ISP) and the like.

HWD2210MCFBGA324 may provide fast transfer delay and clock to output time, four global clocks, two clocks per logic array module (LAB), programmable slew rate per IO, drive strength, bus hold and pull-up resistance capabilities, support hot-plug, built-in JTAG boundary scan circuitry, be compatible with IEEE std.1149.1-1990 protocol, and ISP circuitry be compatible with IEEE std.1532 protocol.

As shown in FIG. 4, the ADC module adopts two JAD9268 chips to realize four-way analog-to-digital conversion, and the JAD9268 is an AD conversion chip with two channels, 16bits and the highest sampling rate of 125MSPS, has higher performance, and extremely low jitter allows undersampling to obtain very good noise performance, and is very suitable for application in the communication field. The chip is powered by a single power supply of 1.8V, the highest power consumption is 750mW, the input range is 1Vp-p or 2Vp-p, the full power bandwidth of 650MHz is selected, and the LFCP package with 64 pins is realized. The SPI of the ADC module is mainly used for configuring the working mode of the ADC module. The clock of the ADC module supports an internal clock mode and an external clock mode, and the hardware device selects the external clock.

The power supplies needed by the JAD9268 and related clock chips are in a secondary voltage stabilizing mode, all power supply chips are of LDO type, and the influence of the power supply on the ADC performance is minimized by utilizing the characteristic of low ripple of the linear power supply. When selecting an LDO chip, an LDO with a low voltage drop is selected, the input voltage value is as low as possible in the required range, and attention is paid to the division of analog and digital regions and the handling of analog power and ground when laying out and wiring.

As shown in fig. 5, the DAC module uses SDA9739K, which can provide sampling frequencies up to 2.5G. The device comprises a Serial Peripheral Interface (SPI) for configuration and status register readback, with single ended LVCMOS signal interfaces for supporting high sampling rates with existing FGPA/ASIC technology. SDA9739K is powered by 1.8V and 3.3V power supplies, with only 1.16W power consumption when 2.5GSPS is in operation.

The interface connection mode between the DAC and the FPGA is as follows:

1. DB0 and DB1 signals of SAD9739A are connected to the HP BANK adjacent to V7, and the Bank voltage is 1.8V;

2. the DCO and DCI signals of SDA9739K are connected to the same Bank of the data signals and connected to the MRCC or SRCC pins;

3. after the SYNC signal of the two-piece SDA9739K is output through the IO of V7, the fan-out is performed to the two-piece DAC chip.

The output transformer model of the two paths of DAC is selected as the RFT-1-1T-F with the Zhenhua, the impedance ratio of the RFT-1-1T-F is 1:1, the frequency range is 0.4-200 MHz, the maximum insertion loss is 1.8dB, the rated current is 30mA, and the maximum device height is 3.0mm; meets the practical use requirement. The output rear end is respectively added with a low-pass filter of one stage 80MHz, the model of which is LFCN3210-80 is selected to be fast reached, the size of the filter is 3.2 x 1.6mm, the insertion loss is 1.5dB when the filter is 80MHz, the voltage standing wave ratio is 1.3, and the stop band loss is less than 20dB. The 70MHz intermediate frequency signal output by the filter is sent to a post-stage unit.

The input clock to the two-chip SDA9739K is provided by a clock distribution chip, fed to the SDA9779MQ via a differential signal clk±pin, which drives the DAC in 8x mode inside the DAC to minimize clock jitter. The power supply required by SDA9739K adopts a secondary voltage stabilizing mode, and all power supply chips are of LDO type.

As shown in FIG. 6, the clock design of the hardware device mainly comprises two parts, wherein one part is a 100M external clock which is used for providing clocks for the FPGA and the ADC/DAC respectively through a GM4526C clock management chip; the second part provides working clocks for DSP, FPGA, CPLD, the singlechip and the PHY chip for other independent crystal oscillators on the board.

The GM4526C maximum CMOS output clock is 250MHz, and the inside is PLL+VCO framework, which has the advantage that phase noise brought by partial reference can be filtered out by using phase-locked loop. The maximum input frequency of the GM4526C PLL is 250MHz, and the internal VCO frequency range is 1.75 GHz-2.25 GHz. The maximum frequency division ratio of the VCO frequency divider is 6, the maximum frequency division ratio of the rear-stage LVPECL channel is 32, and the maximum frequency division ratio of the LVDS channel is 1024.

In the hardware device, the main external interface needed by the DSP comprises 1 path of SRIO x4 interfaces, and is externally connected with the DDR controller, so that the PCIE controller is not needed. According to the actual situation of the hardware device, the interface clock signal not used by the FT-M6678N can be disconnected, so that only the CORE CLK, PASSCLK, DDR CLK and the DSP_SRIO0CLK are needed to be provided for the DSP in the hardware device. CORE CLK, PASS CLK, DDR CLK uses 25MHz 1.8v COMS single ended clock, srio0_clk uses 125MHz HCSL differential clock.

As shown in FIG. 7, the power supply design of the hardware device mainly comprises two parts, wherein the first part is the power supply power consumption analysis and power supply design of each device, and the second part is the power-on sequence control. The device power supply is mainly DSP nuclear power and back-end DC/DC power conversion. Digital part power supplies of the DSP and the FPGA are obtained by converting through a DCDC buck chip; the high-speed port power supplies of the DSP and the FPGA have higher requirements on power supply noise and ripple waves, and are obtained by reducing the voltage by using LDO; the power supply of the ADC and DAC is also obtained using LDO to obtain better signal metrics.

The power-on management and reset of the hardware device select the CPLD to perform unified management, and the HWD2210 needs to be independently powered on and provide an independent clock. After the HWD2210 program is loaded, the power-on sequence and time delay (the power-on slope is configured by the SS soft start pin of the device) of each power supply of the single-board DSP are controlled, and the reset or state control is carried out on the DSP and the peripheral equipment.

The main chips of the hardware device for controlling the power-on time sequence are an FPGA and a DSP, and the power-on time sequence of the FPGA is as follows:

1)VCCINT/VCCBRAM>VCCAUX/VCCAUX_IO>VCCO

2) VCCINT > VCCMGTAVCC > VCCAVTT, VCCMGTAUX has no power up timing requirements.

As shown in fig. 8 and 9, the power-on time sequence requirement on the DSP is more strict, and when the singlechip controls the power-on time sequence and the power-off time sequence of the power supply, each power supply needs to be started in a delayed manner according to the power-on time sequence requirement, so as to realize the management of the power supply.

In the specific implementation process, the DSP is connected with two paths of hundred meganetwork interfaces through an EMIF bus and an SPI interface respectively, and is used for realizing data interaction with the back-end equipment. The Ethernet protocol stack chip uses a CH395L chip, the CH395L chip is provided with a 10/100M Ethernet medium transmission layer (MAC) and a physical layer (PHY), is completely compatible with IEEE802.3 10/100M protocols, and is internally provided with Ethernet protocol stack firmware such as PPPOE, IP, DHCP, ARP, ICMP, IGMP, UDP, TCP.

CH395L supports three communication interfaces: the controllers such as 8-bit parallel port, SPI interface or asynchronous serial port, singlechip/DSP/MCU/MPU can control CH395 chip to carry out Ethernet communication through any one of the communication interfaces.

The hardware device is provided with an 8-path RS422 transmission interface and is realized by a B26LV31 TF. B26LV31TF is 4 paths of RS422 sending chips, receives 3.3V TTL signals and outputs differential signals meeting RS422 interface level and time sequence requirements.

The hardware device is provided with 17 paths of RS422 receiving channels and is realized by a B26LV32 TF. The B26LV32TF is a 4-path RS422 receiving chip, receives RS422 differential level signals and outputs 3.3V CMOS digital signals.

And the FPGA module is connected with one path of RS232 signal, and the signal is externally used as a debugging serial port of the FPGA through the J30J connector. The RS232 level shift chip selects MAX3232eue+.

In order to protect an interface of an FPGA device, an isolation driver is added between the FPGA and a connector, SM164245 is selected to realize, 16 IO ports of SM16245 are divided into two groups, and each group of 8 GPIO passable DIR pins realize control of a signal receiving and transmitting direction.

When the hardware device is required to be used for intermediate frequency modulation and demodulation of signals, the intermediate frequency modulation and demodulation of signals can be realized only by carrying out corresponding software implantation on the FPGA module and the DSP module according to modulation or demodulation requirements. The application only provides a hardware device for intermediate frequency modulation and demodulation of signals, and does not relate to a specific algorithm in a signal processing process, and the hardware device can realize modulation and demodulation by using a common intermediate frequency modulation and demodulation signal method. The innovation point of the application is that the use and connection mode of each module enable the hardware device to have good maintainability on the basis of guaranteeing universality, and meet the requirements of 177.5mm (length) x 135mm (width) x 2mm (plate thickness).

In summary, the utility model adopts the design ideas of board card, standardization and serialization, is suitable for modulating and demodulating the intermediate frequency signals, ensures the universality, ensures the good maintainability of the equipment, and finally ensures that the hardware device meets the requirements of 177.5mm (length) x 135mm (width) x 2mm (plate thickness).

Claims (7)

1. The hardware device for intermediate frequency modulation and signal modulation is characterized by comprising an FPGA module, a DSP module and a CPLD module which are connected with each other in pairs;

the FPGA module is respectively connected with the BPI flash memory, the two paths of DAC modules and the two paths of ADC modules;

the DSP module is respectively connected with the DDR3 memory, the NOR flash memory and the QSPI flash memory;

the CPLD module is respectively connected with the EMMC memory and the singlechip;

the FPGA module comprises a processing chip with the model number of JFM7VX690T 20; the DSP module comprises a processor with the model number of FT-M6678N; the CPLD module comprises a processing chip with the model HWD2210MCFBGA 324;

the FPGA module performs parallel data exchange with the DSP module through a 16-bit EMIF bus; the FPGA module exchanges serial data with the DSP module through a 4-path SRIO x4 bus.

2. The hardware apparatus for intermediate frequency modulation and demodulation of signals according to claim 1, wherein the BPI flash memory is model JFM29GL256-E56; the model of DDR3 memory is SM41J256M16M; the model of the ADC module is JAD9268; the model of the DAC module is SDA9739K; the model of the NOR flash memory is MT28EW256ABA1LJS-0SIT; the model of the singlechip is GD32E103;

the DDR3 memory is 4 pieces and is respectively connected with DDR3 EMIF interfaces of the DSP module in a hanging mode; the NOR flash memory is hung on an EMIF16 interface of the DSP module;

the ADC module is connected with the FPGA module through an LVDS interface;

the DB0 pin and the DB1 pin of the DAC module are respectively connected with the adjacent HP BANK pins of the FPGA module; the DCO pin and the DCI pin of the DAC module are respectively connected with the MRCC pin or the SRCC pin of the FPGA module; the SYNC pin of the DAC module is connected with the IO pin of the FPGA module.

3. The hardware apparatus for intermediate frequency modulation and demodulation of signals according to claim 1, further comprising a clock module of model GM4526C, the clock module being connected to the FPGA module, the ADC module and the DAC module, respectively.

4. The hardware apparatus for intermediate frequency modulation and demodulation of signals according to claim 1, further comprising a 25MHz 1.8v COMS single ended clock and a 125MHz HCSL differential clock; the 25MHz 1.8VCOMS single-ended clock is respectively connected with the CORE CLK pin, the PASS CLK pin and the DDR CLK pin of the DSP module; the 125MHz HCSL differential clock is connected to the SRIO0_CLK pin of the DSP module.

5. The hardware device for intermediate frequency modulation and demodulation of signals according to claim 1, further comprising two hundred meganetwork interfaces, the two hundred meganetwork interfaces being connected to the DSP module through the EMIF bus and the SPI interface, respectively; the Ethernet protocol stack chip model in the hundred meganet interface is CH395L chip.

6. The hardware apparatus for intermediate frequency modulation and demodulation of signals according to claim 1, further comprising an RS422 transmitter chip of model B26LV31TF connected to the CPLD module; and the RS422 receiving chip is connected with the CPLD module and is of a model B26LV32 TF.

7. The hardware apparatus for intermediate frequency modulation and demodulation of signals according to claim 1, further comprising an isolation driver of model SM164245 connected to the LVTTL pins of the FPGA module; and the RS232 level conversion chip is connected with the FPGA module debugging pin and has the model number of MAX3232EUE+.