CN108156099A - Srio switching system - Google Patents
Srio switching system Download PDFInfo
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- CN108156099A CN108156099A CN201711131865.1A CN201711131865A CN108156099A CN 108156099 A CN108156099 A CN 108156099A CN 201711131865 A CN201711131865 A CN 201711131865A CN 108156099 A CN108156099 A CN 108156099A
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- 230000005540 biological transmission Effects 0.000 claims abstract description 7
- 230000002093 peripheral effect Effects 0.000 claims abstract description 5
- 239000013307 optical fiber Substances 0.000 claims abstract description 3
- 238000006243 chemical reaction Methods 0.000 claims abstract 2
- 238000013461 design Methods 0.000 claims description 20
- 238000012544 monitoring process Methods 0.000 claims description 2
- 238000003860 storage Methods 0.000 claims description 2
- 230000005611 electricity Effects 0.000 claims 1
- 238000012545 processing Methods 0.000 abstract description 4
- 238000007781 pre-processing Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 10
- 230000006870 function Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 210000004602 germ cell Anatomy 0.000 description 1
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- 230000006855 networking Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000005622 photoelectricity Effects 0.000 description 1
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- 230000003014 reinforcing effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The invention discloses an SRIO switching system, which is characterized by comprising a PowerPC microprocessor, a RapidIO switching chip and a peripheral circuit, wherein the RapidIO switching chip is interconnected with the PowerPC microprocessor through a high-speed SerDes interface to realize single-path configurable transmission rates of 1.25, 2.5, 3.125, 5.0 and 6.25Gbaud, and 5 switching chips are combined to realize 48-path serial channels and the highest internal switching bandwidth of 240 Gbps; the PowerPC microprocessor converts the electric signal into an optical fiber signal through the photoelectric conversion module and exchanges data with the outside of the exchange system; the peripheral circuit comprises a power supply module, a clock module, a reset module and an interrupt management logic module. The invention realizes the data exchange with large capacity, thereby meeting the data exchange between the front-end preprocessing unit and the signal processing unit device of the task electronic system.
Description
Technical field
The present invention relates to field of data exchange, specifically a kind of SRIO exchange systems.
Background technology
With the fast development of network technology, SRIO proposes highly reliable, high as a kind of exploitation of embedded system
Performance, the high speed interconnection technique of new generation based on packet switch, are commercially widely applied, however are led in space flight and aviation
Domain, the SRIO switching technologies with autonomous controllable hardware and software platform are still in infancy, therefore military most evil to meet
Bad application environment needs, and it is a kind of inexorable trend to study the SRIO switching technologies based on production domesticization hardware and software platform.
To meet the requirement of sky, sea, arms and services' equipment preparation such as plate armour, the message capacity, real-time of the network platform is promoted
Property, it is intelligent, adapt to the autonomous controllable demand for development of equipment, it is imperative to build military reinforcing SRIO trade-to product platforms.
General SRIO switch designs technology designs and develops SRIO friendships using standardization, unified software and hardware architecture
It changes planes product, by using for reference, absorbing ripe, advanced switch platform technical system, with reference to autonomous controlling technology basis, if
Meter adapts to the SRIO switch technology systems of production domesticization hardware and software platform.
SRIO signals have the characteristics that frequency is high, signal overturning is fast, and the CML of the low amplitude of oscillation of SERDES drivings using simulation
Buffer so being characteristically similar to simulation and radiofrequency signal, requires signal integrity strictly, just reasonable cloth is wanted in design
Office will do signal integrity simulation, and need to use novel pcb substrate, and be equipped with high-end test equipment and tested in the process
Card.
The exchange system based on SRIO interfaces is developed, at present there are many solution, but or because of bandwidth deficiency or because unreal
The problems such as now domesticizing and military field most evil bad application environment can not be adapted to and can not use.
Realize data exchange, there are many solutions at present, such as select processor bus, PCIe buses and ten thousand mbit ethernets
Wait interconnection modes.The shortcomings that processor bus and PCIe bus schemes, is that speed is slow and can not realize that the data of large capacity are handed over
It changes.Although ten thousand mbit ethernet schemes can realize the data exchange of relatively high speed large capacity, it is higher to be limited by transmission delay.
The interconnection of Rapid I/O technologies towards high performance embedded system communicates, and ten thousand mbit ethernets that compare, PCI express possess more
High efficiency of transmission.Rapid I/O technologies have software overhead is low, the transmission of hardware error correction retransmission, point-to-point peerings, parcel,
The features such as low transmission time delay.Rapid IO are the ideal choses for connecting embeded processor cluster in a peer-to-peer network.This germline
System needs multiple processors, and mass data must be exchanged between processor, has reliable low latency performance.
Invention content
For solve it is above-mentioned in the prior art the defects of, the present invention provides a kind of SRIO exchange systems, realize large capacity
Data exchange, so as to meet the data between task electronic system front end pretreatment unit and signal processing unit equipment
It exchanges.
The purpose of the present invention is achieved through the following technical solutions：A kind of USB, serial port and security isolation system, should
System external interface is USB, and serial ports pattern is USB serial ports, including：
USB, serial port and control unit are used to implement intelligence or manually USB and serial port function switching, control；
USB, serial port and control security algorithm, are used to implement handoff functionality unlatching, closing and security control.
Wherein, the USB, serial port and control unit include multiplexing control unit, USB switching controls module, serial ports
Modular converter and CPU, the data line USB_DM and USB_DP of 5 line USB OTG outputs are respectively connected to the USB in multiplexing control unit
Two inputs of switching control module, the data line USBO_DM and USBO_DP of USB switching control modules are respectively connected to CPU, and USB is cut
Change data line USB_S_DM and USB_S_DP the access serial ports modular converter of control module, the data line S_RX of serial ports modular converter
CPU is accessed with S_TX, switch selection is made by the control line USB_CTL that CPU comes out, control output is thrown to USB functions or string
Mouth function.
Wherein, the USB_ID lines access CPU of the 5 line USB OTG.
Wherein, the USB, serial port and control security algorithm include the following steps：
Step 1：Power-up starts, and into bootloader, default configuration USB_CTL is thrown to serial ports pattern, can under this environment
USB, serial ports pattern switching are realized by Macintosh or order control USB_CTL；
Step 2：After bootloader start completions, can whether output into fastboot patterns be automatically configured according to user
Pattern, if into fastboot patterns USB_CTL is configured throws to USB mode, restarts system after doing subsequent processing；
Step 3：If not entering fastboot patterns, start to start kernel, automatically configure USB_CTL and throw to serial ports mould
Formula, also switchable combination key configuration USB_CTL force switch mode；
Step 4：Start system, after adb function start completions, automatically configure USB_CTL and throw to USB mode, also may be used
Switching combining key or specific command configuration USB_CTL switch modes.
Compared with prior art, the invention has the advantages that：
The present invention is that an autonomous serial RapidIO optical fiber interface in controllable 48 road of production domesticization based on SRIO agreements exchanges
System realizes the data exchange of large capacity, so as to meet task electronic system front end pretreatment unit and signal processing
Data exchange between unit.
Description of the drawings
Fig. 1 is SRIO exchange system hardware block diagrams in the embodiment of the present invention.
Fig. 2 is microprocessor clock topological diagram in the embodiment of the present invention.
Fig. 3 is RapidIO exchange chip clock topology figures in the embodiment of the present invention.
Fig. 4 is system reset design topology figure in the embodiment of the present invention
Fig. 5 is system break design topology figure in the embodiment of the present invention
Specific embodiment
With reference to specific embodiment, the present invention is described in detail.Following embodiment will be helpful to the technology of this field
Personnel further understand the present invention, but the invention is not limited in any way.It should be pointed out that the ordinary skill to this field
For personnel, without departing from the inventive concept of the premise, various modifications and improvements can be made.These belong to the present invention
Protection domain.
As shown in Figure 1, an embodiment of the present invention provides a kind of SRIO exchange systems, including PowerPC,
RapidIO exchange chips and peripheral circuit, the RapidIO exchange chips are micro- by high speed SerDes interfaces and PowerPC
Processor interconnects, and realizes the transmission rate that 1.25,2.5,3.125,5.0 and 6.25Gbaud of single channel can configure, 5 exchange chips
The inner exchanging bandwidth of totally 48 road serial-ports, highest 240Gbps are realized in combination；The PowerPC passes through photoelectricity
Modular converter converts electrical signals to fiber-optic signal with realizing data exchange outside exchange system；The peripheral circuit includes power supply
Module, clock module, reseting module and interrupt management logic module.
As shown in Fig. 2, the PowerPC has double Power Architecture e500 kernels, 32KB
L1 is cached, and dominant frequency is up to 1.2GHz；64 DDR3SDRAM storage controls support ECC；High speed SerDes interfaces support multichannel
Multiplex Option can be configured to Serial Rapid I/O interfaces and be interconnected with exchange chip；Enhanced three fast ethernet controller of 3 tunnels,
Support debugging configuration management of the user to microprocessor, the power module include at least 1.0V, 1.2V, 1.8V, 2.5V and
Five kinds of output voltages of 3.3V, and microprocessor and RapidIO exchange chips have strict demand to the electric sequence of mains voltage,
The Clock management module includes at least two kinds of output clocks of 156.25MHz, 100MHz, referring to attached drawing 2 and attached drawing 3.
The reseting module includes two kinds of reset modes, and one kind is to be carried out manually using touch switch and CPLD reset signals
It resets, another kind is reset chip monitoring 3.3V voltages, when voltage is less than 2.6V, generates reset signal, and restore in voltage
When normal, reset signal can still keep 140ms.Referring to attached drawing 4.
For the interrupt management logic module using CPU as core, all interrupt source is finally all reported to cpu system, and by
The system software run on CPU handles the interruption that each equipment is sent to.Referring to attached drawing 5.
Core CPU of the PowerPC as exchange system, design element includes memory design, Flash is set
Meter, the design of debugging serial ports and debugging serial interface design, memory design need to meet 2GB capacity, 1bank, 5, totally 64, when clock rate
Rate >=200MHz；Flash designs are selected chip S29GL01GP, monolithic 128MB, are done redundancy using two panels and set using Redundancy Design
Meter ensures that system has stronger reliability.Flash is articulated on the Local Bus of processor, by address latch come real
Existing address latch is debugged and RS232 transceivers is mounted in the UART interface that serial ports passes through processor again through going out before DB9 sockets.Debugging
Network interface mounts out two 1 tunnel gigabit PHY by the SGMII interfaces of processor, then through coupler (GST5009), RJ45 sockets before
Go out.
PowerPC model FreeScale company P2020 in this specific implementation；RapidIO exchange chip types
Number be Integrated Device Technology, Inc. CPS1848；Optical module uses AFBR810 the and AFBR820 optic modules of Avago companies；Memory grain type
Number be Micron companies MT41J256M16HA-107IT；The S29GL01GP of Flash chip model Spansion companies；Thousand
Million network PHY chip models are the BCM54616S of Broadcom companies；Gigabit networking coupler model is GST5009.
Specific embodiments of the present invention are described above.It is to be appreciated that the invention is not limited in above-mentioned
Particular implementation, those skilled in the art can make various deformations or amendments within the scope of the claims, this not shadow
Ring the substantive content of the present invention.
Claims (7)
1.SRIO exchange systems, which is characterized in that including PowerPC, RapidIO exchange chips and periphery electricity
Road, the RapidIO exchange chips are interconnected by high speed SerDes interfaces and PowerPC, realization single channel 1.25,
2.5th, totally 48 road serial-ports, most are realized in the transmission rate that 3.125,5.0 and 6.25Gbaud can configure, the combination of 5 exchange chips
The inner exchanging bandwidth of high 240Gbps；The PowerPC converts electrical signals to optical fiber by photoelectric conversion module
Signal is with realizing data exchange outside exchange system；The peripheral circuit include power module, clock module, reseting module and
Interrupt management logic module.
2. SRIO exchange systems according to claim 1, which is characterized in that the PowerPC has double
Power Architecture e500 kernels, 32KB L1 cachings, dominant frequency is up to 1.2GHz；64 DDR3SDRAM storage controls
Device supports ECC；High speed SerDes interfaces support multiplexing option, can be configured to Serial Rapid I/O interfaces with exchanging
Chip interconnects；Enhanced three fast ethernet controller of 3 tunnels, supports debugging configuration management of the user to microprocessor.
3. SRIO exchange systems according to claim 1, which is characterized in that the power module include at least 1.0V,
Five kinds of output voltages of 1.2V, 1.8V, 2.5V and 3.3V.
4. SRIO exchange systems according to claim 1, which is characterized in that the Clock management module includes at least
Two kinds of output clocks of 156.25MHz, 100MHz.
5. SRIO exchange systems according to claim 1, which is characterized in that the reseting module includes two kinds of reset sides
Formula, one kind are to be resetted manually using touch switch and CPLD reset signals, and another kind is reset chip monitoring 3.3V voltages,
When voltage is less than 2.6V, reset signal is generated, and when voltage restores normal, reset signal can still keep 140ms.
6. SRIO exchange systems according to claim 1, which is characterized in that the interrupt management logic module using CPU as
Core, all interrupt source is finally all reported to cpu system, and the system software by being run on CPU handles what each equipment was sent to
It interrupts.Referring to attached drawing 5.
7. SRIO exchange systems according to claim 1, which is characterized in that PowerPC is as exchange system
Core CPU, design element includes memory design, Flash designs, the design of debugging serial ports and debugging serial interface design, and memory sets
Meter needs to meet 2GB capacity, 1bank, 5, totally 64, clock rate >=200MHz；Flash designs are using Redundancy Design, choosing
With chip S29GL01GP, monolithic 128MB, Redundancy Design is done using two panels, ensures that system has stronger reliability；Flash is hung
It is connected on the Local Bus of processor, address latch, UART of the debugging serial ports by processor is realized by address latch
RS232 transceivers are mounted on interface again through going out before DB9 sockets；Debugging serial interface mounts out two 1 by the SGMII interfaces of processor
Road gigabit PHY, then through going out before coupler (GST5009), RJ45 sockets.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711131865.1A CN108156099A (en) | 2017-11-15 | 2017-11-15 | Srio switching system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711131865.1A CN108156099A (en) | 2017-11-15 | 2017-11-15 | Srio switching system |
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| CN108156099A true CN108156099A (en) | 2018-06-12 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109672634A (en) * | 2018-12-03 | 2019-04-23 | 天津津航计算技术研究所 | The clog-free SRIO network topology structure in 18 tunnels and method based on exchange chip |
| CN110691044A (en) * | 2019-10-12 | 2020-01-14 | 四川赛狄信息技术股份公司 | Data exchange system based on SRIO exchange chip |
| CN113326227A (en) * | 2021-08-03 | 2021-08-31 | 上海国微思尔芯技术股份有限公司 | Link multiplexing method, system and prototype verification method |
| CN113485875A (en) * | 2021-05-20 | 2021-10-08 | 新华三半导体技术有限公司 | Chip verification system and verification method |
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| CN107181702A (en) * | 2017-06-15 | 2017-09-19 | 济南浪潮高新科技投资发展有限公司 | It is a kind of to realize the device that RapidIO and Ethernet fusion are exchanged |
| CN107332841A (en) * | 2017-06-30 | 2017-11-07 | 山东超越数控电子有限公司 | Multi-protocols hybrid switching module based on PowerPC |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109672634A (en) * | 2018-12-03 | 2019-04-23 | 天津津航计算技术研究所 | The clog-free SRIO network topology structure in 18 tunnels and method based on exchange chip |
| CN109672634B (en) * | 2018-12-03 | 2020-11-06 | 天津津航计算技术研究所 | 18-path non-blocking SRIO network topology device and method based on switching chip |
| CN110691044A (en) * | 2019-10-12 | 2020-01-14 | 四川赛狄信息技术股份公司 | Data exchange system based on SRIO exchange chip |
| CN113485875A (en) * | 2021-05-20 | 2021-10-08 | 新华三半导体技术有限公司 | Chip verification system and verification method |
| CN113326227A (en) * | 2021-08-03 | 2021-08-31 | 上海国微思尔芯技术股份有限公司 | Link multiplexing method, system and prototype verification method |
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Application publication date: 20180612 |
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