CN215896410U

CN215896410U - Schottky-integrated shielding gate groove power semiconductor structure

Info

Publication number: CN215896410U
Application number: CN202122260919.2U
Authority: CN
Inventors: 朱袁正; 叶鹏; 杨卓; 周锦程; 刘晶晶
Original assignee: Wuxi NCE Power Co Ltd
Current assignee: Wuxi NCE Power Co Ltd
Priority date: 2021-09-17
Filing date: 2021-09-17
Publication date: 2022-02-22
Anticipated expiration: 2031-09-17

Abstract

The utility model relates to a power semiconductor structure, in particular to a Schottky integrated shielding grid groove power semiconductor structure, wherein six grooves are arranged on the surface of a chip, the first grooves are mutually parallel and uniformly distributed, the second grooves are arranged around the first grooves, the fifth grooves are positioned at the inner sides of the second grooves, at least one pair of adjacent first grooves is replaced by a fifth groove, the sixth grooves are arranged between the adjacent fifth grooves, two ends of the sixth grooves are respectively and vertically communicated with the adjacent fifth grooves, the sixth grooves are mutually parallel, a source metal is in ohmic contact with second conductive polycrystalline silicon in the sixth grooves through a fourth through hole, an epitaxial layer area between the adjacent sixth grooves is a Schottky contact area, and the source metal is in ohmic contact with an epitaxial layer in the Schottky contact area through the fifth through hole, reverse recovery can be accelerated, and energy loss is reduced.

Description

Schottky-integrated shielding gate groove power semiconductor structure

Technical Field

The utility model relates to a power semiconductor structure, in particular to a Schottky integrated shielding grid groove power semiconductor structure.

Background

A shielded gate metal oxide semiconductor field effect transistor (SGT MOSFET for short) inherently has a parasitic diode connected in parallel with it, with the anode of the parasitic diode connected to the source of the MOSFET and the cathode connected to the drain of the MOSFET, so that the SGT MOSFET also serves to freewheel. The parasitic diode is conductive by minority carriers like a common diode, so that the parasitic diode has reverse recovery time, thereby reducing the switching speed and increasing the switching loss. Schottky diodes have the advantage of lower forward diode voltage drop, and are usually connected in parallel with MOSFET devices to improve the diode recovery time of the switching operation of the devices and to suppress the power loss of the non-switching part of the devices during operation.

However, the schottky diode generally has a high reverse bias leakage current, which adversely affects the performance of the device, and meanwhile, in the prior art, an independent schottky diode chip is generally arranged outside the SGT MOSFET chip, and the schottky diode chip and the SGT MOSFET chip are sealed, which greatly increases the chip cost and the packaging cost.

In order to reduce the chip cost and the packaging cost and simultaneously reduce the reverse bias leakage current, the utility model provides a new design scheme.

Disclosure of Invention

The utility model aims to provide a Schottky-integrated shielding gate trench power semiconductor structure aiming at the defects of the prior art, and the Schottky-integrated shielding gate trench power semiconductor structure can solve the problems of overlarge chip cost and packaging cost and high reverse bias leakage current in the prior art.

In order to achieve the technical purpose, the utility model adopts the following technical scheme: a Schottky-integrated shielding grid groove power semiconductor structure comprises a first conduction type substrate, wherein a first conduction type epitaxial layer is arranged above the first conduction type substrate, six types of grooves are formed in the surface of the first conduction type epitaxial layer in a overlooking angle, and the first type of grooves are mutually parallel and uniformly distributed; second grooves are arranged around the first grooves in a surrounding mode and comprise second parallel grooves and second vertical grooves, and the second vertical grooves comprise first vertical grooves and second vertical grooves which are vertically arranged at the left end and the right end of the first grooves; a third groove perpendicular to the first vertical groove is formed in the outer side of the second groove, and one end of the third groove is communicated with the first vertical groove; a fourth groove perpendicular to the second vertical groove is formed in the outer side of the second groove, and one end of the fourth groove is communicated with the second vertical groove; a fifth groove is arranged on the inner side of the second groove, at least one pair of adjacent first grooves is replaced by a corresponding pair of fifth grooves, the fifth grooves are perpendicular to the second vertical grooves, one end of each fifth groove is communicated with the second vertical groove, and the other end of each fifth groove is not communicated with the first vertical groove; a plurality of parallel sixth grooves are arranged between every two adjacent fifth grooves, and two ends of each sixth groove are perpendicular to and communicated with the two adjacent fifth grooves;

a second conductive type body region is arranged on the surface of the first conductive type epitaxial layer between the adjacent first type grooves, a first conductive type source region is arranged on the surface of the second conductive type body region, the first type grooves penetrate through the second conductive type body region to enter the first conductive type epitaxial layer, the lower half sections of the first type grooves are provided with first type conductive polycrystalline silicon, the upper half sections of the first type grooves are provided with second type conductive polycrystalline silicon, the first type conductive polycrystalline silicon and the second type conductive polycrystalline silicon are insulated through a first type insulating medium, the first type conductive polycrystalline silicon is insulated from the first conductive type epitaxial layer through a field oxide layer, the second type conductive polycrystalline silicon is insulated from the first conductive type epitaxial layer through a gate oxide layer, a second type insulating medium is arranged above the first type grooves and the first conductive type source region, and a source electrode metal is arranged above the second type insulating medium, the source metal is in ohmic contact with the first conduction type source region and the second conduction type body region through the first through hole;

a second conductive type body region is arranged on the surface of the first conductive type epitaxial layer between the second parallel groove and the adjacent first groove or fifth groove, the second parallel groove penetrates through the second conductive type body region to enter the first conductive type epitaxial layer, the first conductive polycrystalline silicon is arranged at the lower half section of the second parallel groove, the second conductive polycrystalline silicon is arranged at the position, close to the inner side, of the upper half section, a third insulating medium is arranged at the position, close to the outer side, of the upper half section, the first conductive polycrystalline silicon and the second conductive polycrystalline silicon are insulated through the first insulating medium, the first conductive polycrystalline silicon is insulated from the first conductive type epitaxial layer through a field oxide layer, the second conductive polycrystalline silicon is insulated from the first conductive type epitaxial layer through a gate oxide layer, and a second insulating medium is arranged above the second parallel groove and the second conductive type body region, a source electrode metal is arranged above the second type of insulating medium and is in ohmic contact with the second conductive type body region through the first type of through hole;

the lower half section of the first vertical groove is provided with first-type conductive polycrystalline silicon, the position, close to the inner side, of the upper half section is provided with second-type conductive polycrystalline silicon, the position, close to the outer side, of the upper half section is provided with a third-type insulating medium, the first-type conductive polycrystalline silicon is insulated from the first conductive type epitaxial layer through a field oxide layer, and the second-type conductive polycrystalline silicon is insulated from the first conductive type epitaxial layer through a gate oxide layer;

the second vertical groove is filled with first conductive polycrystalline silicon, and the first conductive polycrystalline silicon is insulated from the first conductive epitaxial layer through the field oxide layer;

the lower half section of the third groove is provided with first conductive polycrystalline silicon, the middle position of the upper half section is provided with second conductive polycrystalline silicon, two sides of the second conductive polycrystalline silicon are provided with third insulating media, and the first conductive polycrystalline silicon is insulated from the first conductive epitaxial layer through the field oxide layer; a second type of insulating medium is arranged above the third type of groove and the first conductive type epitaxial layer, and gate metal is arranged above the second type of insulating medium and in ohmic contact with the second type of conductive polycrystalline silicon through a second type of through hole;

the fourth type of groove is filled with first type of conductive polysilicon, and the first type of conductive polysilicon is insulated from the first conductive type epitaxial layer through the field oxide layer; a second type of insulating medium is arranged above the fourth type of groove and the first conductive type epitaxial layer, source metal is arranged above the second type of insulating medium, and the source metal is in ohmic contact with the first type of conductive polycrystalline silicon through a third type of through hole;

the lower half sections of the sixth type groove and the fifth type groove are provided with first type conductive polycrystalline silicon, the upper half sections are provided with second type conductive polycrystalline silicon, the first type conductive polycrystalline silicon and the second type conductive polycrystalline silicon are insulated through a first type insulating medium, the first type conductive polycrystalline silicon is insulated with the first conductive type epitaxial layer through a field oxide layer, the second type conductive polycrystalline silicon is insulated with the first conductive type epitaxial layer through a gate oxide layer, a second type of insulating medium is arranged above the fifth type of groove, the sixth type of groove and the epitaxial layer, a source electrode metal is arranged above the second type of insulating medium, the source metal is in ohmic contact with the second conductive polycrystalline silicon in the sixth type of grooves through the fourth type of through holes, an epitaxial layer region between the adjacent sixth type of grooves is a Schottky contact region, the source electrode metal is in Schottky contact with the epitaxial layer in the Schottky contact region through the fifth type of through holes;

the first conductive polycrystalline silicon in the six types of grooves is electrically connected with the potential of the source metal; the second type of conductive polysilicon in the first type of groove, the second type of groove and the third type of groove is electrically connected with the potential of the grid metal; and the second type of conductive polysilicon in the fifth type of groove and the sixth type of groove is electrically connected with the potential of the source metal.

Further, the length of the first conduction type epitaxial layer between the adjacent sixth type trenches in the direction parallel to the fifth type trenches is 0.5-100 micrometers.

Furthermore, the lower half section of the fourth type groove is provided with a first type of conductive polysilicon, the upper half section of the fourth type groove is provided with a third type of insulating medium, the first type of conductive polysilicon is insulated from the epitaxial layer through the field oxide layer, a second type of insulating medium is arranged above the fourth type groove and the first type of conductive epitaxial layer, a source electrode metal is arranged above the second type of insulating medium, and the source electrode metal penetrates through the second type of insulating medium and the third type of insulating medium through a third type of through hole and is electrically connected with the first type of conductive polysilicon.

Furthermore, the lower half section of the second vertical groove is provided with a first type of conductive polysilicon, the upper half section of the second vertical groove is provided with a third type of insulating medium, and the first type of conductive polysilicon is insulated from the first conductive type epitaxial layer through the field oxide layer.

Furthermore, the second parallel grooves are filled with first conductive polysilicon, and the first conductive polysilicon is insulated from the epitaxial layer by the field oxide layer.

Further, the field oxide layer, the gate oxide layer, the first type of insulating medium, the second type of insulating medium and the third type of insulating medium are all made of silicon dioxide or silicon nitride.

Further, the power semiconductor device is an N-type power semiconductor device or a P-type power semiconductor device;

when the power semiconductor device is an N-type power semiconductor device, the first conduction type is an N type, and the second conduction type is a P type;

when the power semiconductor device is a P-type semiconductor device, the first conductivity type is P-type, and the second conductivity type is N-type.

Compared with the prior art, the utility model has the following advantages:

in the prior art, an external independent Schottky diode is generally connected in parallel with a semiconductor power device, so that the area of a printed circuit board is increased, an epitaxial layer region between adjacent sixth grooves is a Schottky contact region, and source metal is in Schottky contact with the epitaxial layer in the Schottky contact region through a fifth through hole; the Schottky diode can fully utilize the epitaxial layer, reduce the resistance and improve the current capability of the Schottky diode, and the Schottky diode can inhibit the increase of reverse bias leakage current by the auxiliary depletion principle of the shielding gate structure; the utility model can save the cost of customers and save the space for design.

Drawings

Fig. 1 is a top view of the contact holes, trenches and metal distribution of the power device of the present invention.

Fig. 2 is a top view of a first type conductive polysilicon distribution of the power device of the present invention.

Fig. 3 is a top view of a second type of conductive polysilicon distribution for a power device of the present invention.

Fig. 4 is a schematic sectional view taken along a broken line AA' in fig. 1.

Fig. 5 is a schematic sectional view taken along a broken line BB' in fig. 1.

Fig. 6 is a schematic sectional structure view taken along a dotted line CC' in fig. 1.

Fig. 7 is a schematic sectional view taken along a broken line DD' in fig. 1.

Fig. 8 is a schematic sectional structure view taken along a broken line EE' in fig. 1.

Description of reference numerals: 1-a first conductivity type substrate; 2-a first conductivity type epitaxial layer; 3-first type trenches; 4-second type trenches; 5-fifth type grooves; 6-third type of trench; 7-fourth type trenches; 8-first type conductive polysilicon; 9-second type conductive polysilicon; a 10-field oxygen layer; 11-a gate oxide layer; 12-a first type of insulating medium; 13-insulating media of a third type; 14-insulating media of a second type; 15-a second conductivity type body region; 16-a source region of the first conductivity type; 17-a first type of via; 18-a fifth type of via; 19-source metal; 20-gate metal; 21-a second type of via; 22-a third type of via; 23-a fourth type of via; 24-type six grooves; 41-parallel trenches of the second type; 42-vertical trenches of the second type; 42A-first vertical trench; 42B-second vertical trench.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings. In which like parts are designated by like reference numerals. It should be noted that the words "left", "right", "upper" and "lower" used in the following description refer to directions in the drawings. The terms "inner" and "outer" are used to refer to directions toward and away from, respectively, the geometric center of a particular component.

The utility model includes the following three embodiments, which are described by taking an N-type power semiconductor device as an example.

Example 1

As shown in fig. 1, a schottky-integrated shielded gate trench power semiconductor structure includes a first conductive type substrate 1, the first conductive type substrate 1 is an N-type substrate, a first conductive type epitaxial layer 2 is disposed above the first conductive type substrate 1, the first conductive type epitaxial layer 2 is an N-type epitaxial layer, six types of trenches are disposed on the surface of the first conductive type epitaxial layer 2 in a top view, first type trenches 3 are parallel and uniformly distributed, second type trenches 4 are disposed around the first type trenches 3, wherein a second type parallel trench 41 is disposed parallel to the first type trenches 3, a second type vertical trench 42 is disposed perpendicular to the first type trenches 3 and communicated with two ends of the first type trenches 3, a first vertical trench 42A and a second vertical trench 42B are disposed at the left and right ends of the first type trenches 3, one side of the second type trenches 4 close to the first type trenches 3 is an inner side of the second type trenches 4, the other corresponding side is the outer side of the second type groove 4, the third type groove 6 is distributed on the outer side of the second type groove 4 and is vertical to the first vertical groove 42A, one end of the third type groove 6 is communicated with the first vertical groove 42A, the fourth type groove 7 is distributed on the outer side of the second type groove 4 and is vertical to the second vertical groove 42B, one end of the fourth type groove 7 is communicated with the second vertical groove 42B, the fifth type groove 5 is positioned on the inner side of the second type groove 4, at least one pair of adjacent first type grooves 3 is replaced by a fifth type groove 5, the fifth type groove 5 is vertical to the second vertical groove 42B, one end of the fifth type groove 5 is communicated with the second vertical groove 42B, but the other end of the fifth type groove 5 is not communicated with the first vertical groove 42A, the sixth type groove 24 is arranged between the adjacent fifth type grooves 5, and two ends of the sixth grooves 24 are respectively perpendicular to and communicated with two adjacent fifth grooves 5, and the sixth grooves 24 are parallel to each other.

As shown in fig. 4, which is a schematic cross-sectional structure view taken along a dashed line AA' in fig. 1, a second conductive type body region 15 is disposed on the surface of the first conductive type epitaxial layer 2 between adjacent first type trenches 3, the second conductive type body region 15 is a P-type body region, a first conductive type source region 16 is disposed on the surface of the second conductive type body region 15, the first conductive type source region 16 is an N-type source region, the first type trenches 3 penetrate through the second conductive type body region 15 into the first conductive type epitaxial layer 2, a first conductive polysilicon 8 is disposed on a lower half section of the first type trenches 3, a second conductive polysilicon 9 is disposed on an upper half section of the first type trenches 3, the first conductive polysilicon 8 and the second conductive polysilicon 9 are insulated by a first insulating medium 12, the first conductive polysilicon 8 is insulated from the epitaxial layer by a field oxide layer 10, the second conductive polysilicon 9 is insulated from the epitaxial layer by a gate oxide layer 11, a second type of insulating medium 14 is arranged above the first type of trench 3 and the first conductivity type source region 16, a source metal 19 is arranged above the second type of insulating medium 14, and the source metal 19 is in ohmic contact with the first conductivity type source region 16 and the second conductivity type body region 15 through the first type of via hole 17.

A second conductive type body area 15 is arranged on the surface of the first conductive type epitaxial layer 2 between the second type parallel groove 41 and the adjacent first type groove 3, the second type parallel groove 41 penetrates through the second conductive type body area 15 to enter the first conductive type epitaxial layer 2, the first type conductive polycrystalline silicon 8 is arranged at the lower half section of the second type parallel groove 41, the second type conductive polycrystalline silicon 9 is arranged at the position of the upper half section close to the inner side, the third type insulating medium 13 is arranged at the position of the upper half section close to the outer side, the first type conductive polycrystalline silicon 8 and the second type conductive polycrystalline silicon 9 are insulated through the first type insulating medium 12, the first type conductive polycrystalline silicon 8 is insulated from the epitaxial layer through the field oxide layer 10, the second type conductive polycrystalline silicon 9 is insulated from the epitaxial layer through the gate oxide layer 11, and a second type insulating medium 14 is arranged above the second type parallel groove 41 and the second conductive type body area 15, a source metal 19 is provided above the second type of insulating medium 14, which source metal 19 is in ohmic contact with the second conductivity type body region 15 through the first type of via 17.

The lower half section of the first vertical groove 42A is provided with a first type of conductive polysilicon 8, the position of the upper half section close to the inner side is provided with a second type of conductive polysilicon 9, the position of the upper half section close to the outer side is provided with a third type of insulating medium 13, the first type of conductive polysilicon 8 is insulated from the epitaxial layer through a field oxide layer 10, and the second type of conductive polysilicon 9 is insulated from the epitaxial layer through a gate oxide layer 11.

The second vertical trench 42B is filled with a first type of conductive polysilicon 8, said first type of conductive polysilicon 8 being insulated from the epitaxial layer by the field oxide layer 10.

As shown in fig. 6, which is a schematic cross-sectional structure view taken along a dashed line CC' in fig. 1, a lower half section of the third-type trench 6 is provided with a first-type conductive polysilicon 8, a middle position of an upper half section is provided with a second-type conductive polysilicon 9, two sides of the second-type conductive polysilicon 9 are provided with third-type insulating media 13, and the first-type conductive polysilicon 8 is insulated from the epitaxial layer by a field oxide layer 10; a second insulating medium 14 is arranged above the third trench 6 and the epitaxial layer, a gate metal 20 is arranged above the second insulating medium 14, and the gate metal 20 is in ohmic contact with the second conductive polysilicon 9 through a second through hole 21.

As shown in fig. 7, which is a schematic cross-sectional view taken along a dashed line DD' in fig. 1, the fourth-type trench 7 is filled with a first-type conductive polysilicon 8, and the first-type conductive polysilicon 8 is insulated from the epitaxial layer by a field oxide layer 10; a second insulating medium 14 is arranged above the fourth trench 7 and the epitaxial layer, a source metal 19 is arranged above the second insulating medium 14, and the source metal 19 is in ohmic contact with the first conductive polysilicon 8 through a third through hole 22.

As shown in fig. 4, the first type of conductive polysilicon 8 is disposed in the lower half of the sixth type of trench 24 and the fifth type of trench 5, the second type of conductive polysilicon 9 is disposed in the upper half, the first type of conductive polysilicon 8 and the second type of conductive polysilicon 9 are insulated by the first type of insulating medium 12, the first type of conductive polysilicon 8 is insulated from the epitaxial layer by the field oxide layer 10, the second type of conductive polysilicon 9 is insulated from the epitaxial layer by the gate oxide layer 11, the second type of insulating medium 14 is disposed above the fifth type of trench 5, the sixth type of trench 24 and the epitaxial layer, the source metal 19 is disposed above the second type of insulating medium 14, and the source metal 19 is in ohmic contact with the second type of conductive polysilicon 9 in the sixth type of trench 24 through the fourth type of via 23.

As shown in fig. 8, which is a schematic cross-sectional view taken along the dashed line EE' in fig. 1, the epitaxial layer region between the adjacent sixth-type trenches 24 is a schottky contact region, and the source metal 19 is in schottky contact with the epitaxial layer in the schottky contact region through the fifth-type via 18.

As shown in fig. 2, which is a schematic top view of the distribution of the first type of conductive polysilicon of the chip provided by the present invention, the first type of conductive polysilicon 8 in the six types of trenches are electrically connected to the potential of the source metal 19; as shown in fig. 3, which is a schematic top view of the distribution of the second type of conductive polysilicon of the chip provided by the present invention, the second type of conductive polysilicon 9 in the first type of trench 3, the second type of trench 4, and the third type of trench 6 are electrically connected to the potential of the gate metal 20; the fifth trench 5 is electrically connected to the second conductive polysilicon 9 in the sixth trench 24 and is connected to the potential of the source metal 19.

The length of the epitaxial layer between the adjacent sixth type trenches 24 in the direction parallel to the fifth type trenches 5 is 1 micron.

The field oxide layer 10, the gate oxide layer 11, the first insulating dielectric 12, the second insulating dielectric 14 and the third insulating dielectric 13 are all made of silicon dioxide.

Example 2

A Schottky integrated shielding grid groove power semiconductor structure comprises a first conduction type substrate 1, wherein the first conduction type substrate 1 is an N-type substrate, a first conduction type epitaxial layer 2 is arranged above the first conduction type substrate 1, the first conduction type epitaxial layer 2 is an N-type epitaxial layer, six types of grooves are arranged on the surface of the first conduction type epitaxial layer 2 in a overlooking angle, first type grooves 3 are mutually parallel and uniformly distributed, second type grooves 4 are arranged around the first type grooves 3, second type parallel grooves 41 are arranged parallel to the first type grooves 3, second type vertical grooves 42 are arranged perpendicular to the first type grooves 3 and communicated with two ends of the first type grooves 3, first vertical grooves 42A and second vertical grooves 42B are arranged at the left end and the right end of the first type grooves 3, one side of the second type grooves 4, which surrounds the first type grooves 3, is the inner side of the second type grooves 4, the other corresponding side is the outer side of the second type groove 4, the third type groove 6 is distributed on the outer side of the second type groove 4 and is vertical to the first vertical groove 42A, one end of the third type groove 6 is communicated with the first vertical groove 42A, the fourth type groove 7 is distributed on the outer side of the second type groove 4 and is vertical to the second vertical groove 42B, one end of the fourth type groove 7 is communicated with the second vertical groove 42B, the fifth type groove 5 is positioned on the inner side of the second type groove 4, at least one pair of adjacent first type grooves 3 is replaced by a fifth type groove 5, the fifth type groove 5 is vertical to the second vertical groove 42B, one end of the fifth type groove 5 is communicated with the second vertical groove 42B, but the other end of the fifth type groove 5 is not communicated with the first vertical groove 42A, the sixth type groove 24 is arranged between the adjacent fifth type grooves 5, and two ends of the sixth grooves 24 are respectively perpendicular to and communicated with two adjacent fifth grooves 5, and the sixth grooves 24 are parallel to each other.

A second conductive type body region 15 is arranged on the surface of the first conductive type epitaxial layer 2 between the adjacent first type grooves 3, the second conductive type body region 15 is a P-type body region, a first conductive type source region 16 is arranged on the surface of the second conductive type body region 15, the first conductive type source region 16 is an N-type source region, the first type grooves 3 penetrate through the second conductive type body region 15 to enter the first conductive type epitaxial layer 2, first type conductive polysilicon 8 is arranged on the lower half section of the first type grooves 3, second type conductive polysilicon 9 is arranged on the upper half section of the first type grooves 3, the first type conductive polysilicon 8 and the second type conductive polysilicon 9 are insulated through a first type insulating medium 12, the first type conductive polysilicon 8 is insulated from the epitaxial layer through a field oxide layer 10, the second type conductive polysilicon 9 is insulated from the epitaxial layer through a gate oxide layer 11, a second type insulating medium 14 is arranged above the first type grooves 3 and the first conductive type source region 16, a source metal 19 is disposed above the second type insulating medium 14, and the source metal 19 is in ohmic contact with the first conductivity type source region 16 and the second conductivity type body region 15 through the first type via 17.

A second conductive type body region 15 is arranged on the surface of the first conductive type epitaxial layer 2 between the second type parallel groove 41 and the adjacent first type groove 3, the second type parallel groove 41 penetrates through the second conductive type body region 15 to enter the first conductive type epitaxial layer 2, the second type parallel groove 41 is filled with first type conductive polysilicon 8, the first type conductive polysilicon 8 is insulated from the first conductive type epitaxial layer 2 through a field oxide layer 10, a second type insulating medium 14 is arranged above the second type parallel groove 41 and the second conductive type body region 15, a source metal 19 is arranged above the second type insulating medium 14, and the source metal 19 is in ohmic contact with the second conductive type body region 15 through a first type through hole 17.

The lower half section of the first vertical groove 42A is provided with a first type of conductive polysilicon 8, the middle position of the upper half section is provided with a second type of conductive polysilicon 9, the two sides of the second type of conductive polysilicon 9 are provided with a third type of insulating medium 13, the first type of conductive polysilicon 8 is insulated from the epitaxial layer by a field oxide layer 10, and the second type of conductive polysilicon 9 is insulated from the first type of conductive polysilicon 8 by a first type of insulating medium 12.

The lower half section of the third-type groove 6 is provided with first-type conductive polycrystalline silicon 8, the middle position of the upper half section is provided with second-type conductive polycrystalline silicon 9, the two sides of the second-type conductive polycrystalline silicon 9 are provided with third-type insulating media 13, and the first-type conductive polycrystalline silicon 8 is insulated from the epitaxial layer through a field oxide layer 10; a second insulating medium 14 is arranged above the third trench 6 and the epitaxial layer, a gate metal 20 is arranged above the second insulating medium 14, and the gate metal 20 is in ohmic contact with the second conductive polysilicon 9 through a second through hole 21.

The fourth-type groove 7 is filled with first-type conductive polysilicon 8, and the first-type conductive polysilicon 8 is insulated from the epitaxial layer through a field oxide layer 10; a second insulating medium 14 is arranged above the fourth trench 7 and the epitaxial layer, a source metal 19 is arranged above the second insulating medium 14, and the source metal 19 is in ohmic contact with the first conductive polysilicon 8 through a third through hole 22.

The lower half sections of the sixth type groove 24 and the fifth type groove 5 are provided with first type conductive polysilicon 8, the upper half sections are provided with second type conductive polysilicon 9, the first type conductive polysilicon 8 and the second type conductive polysilicon 9 are insulated by a first type insulating medium 12, the first type conductive polysilicon 8 is insulated from the epitaxial layer by a field oxide layer 10, the second type conductive polysilicon 9 is insulated from the epitaxial layer by a gate oxide layer 11, a second type insulating medium 14 is arranged above the fifth type trenches 5, the sixth type trenches 24 and the epitaxial layer, a source metal 19 is arranged above the second type insulating medium 14, the source metal 19 is in ohmic contact with the second type conducting polysilicon 9 in the sixth type groove 24 through a fourth type through hole 23, the epitaxial layer region between the adjacent sixth-type trenches 24 is a schottky contact region, and the source metal 19 is in schottky contact with the epitaxial layer in the schottky contact region through the fifth-type through holes 18.

The first conductive polysilicon 8 in the six types of grooves is electrically connected and connected with the potential of the source metal 19; the second conductive polysilicon 9 in the first trench 3, the second trench 4 and the third trench 6 are electrically connected and connected with the potential of the gate metal 20; the fifth trench 5 is electrically connected to the second conductive polysilicon 9 in the sixth trench 24 and is connected to the potential of the source metal 19.

The lower half section of the fourth type groove 7 is provided with a first type conductive polysilicon 8, the upper half section is provided with a third type insulating medium 13, the first type conductive polysilicon 8 is insulated from the epitaxial layer through a field oxide layer 10, a second type insulating medium 14 is arranged above the fourth type groove 7 and the epitaxial layer, a source electrode metal 19 is arranged above the second type insulating medium 14, and the source electrode metal 19 penetrates through the second type insulating medium 14 and the third type insulating medium 13 through a third type through hole 22 and is electrically connected with the first type conductive polysilicon 8.

The field oxide layer 10, the gate oxide layer 11, the first type insulating medium 12, the second type insulating medium 14 and the third type insulating medium 13 are all made of silicon dioxide.

Example 3

A Schottky integrated shielding grid groove power semiconductor structure comprises a first conductive type substrate 1, wherein the first conductive type substrate 1 is an N-type substrate, a first conductive type epitaxial layer 2 is arranged above the first conductive type substrate 1, the first conductive type epitaxial layer 2 is an N-type epitaxial layer, six types of grooves are arranged on the surface of the N-type epitaxial layer 2 from the overlooking angle of a chip, first type grooves 3 are mutually parallel and uniformly distributed, second type grooves 4 are arranged around the first type grooves 3, second type parallel grooves 41 are arranged parallel to the first type grooves 3, second type vertical grooves 42 are arranged perpendicular to the first type grooves 3 and communicated with two ends of the first type grooves 3, first vertical grooves 42A and second vertical grooves 42B are arranged at the left end and the right end of the first type grooves 3, one side of the second type grooves 4, which is surrounded by the first type grooves 3, is the inner side of the second type grooves 4, the other corresponding side is the outer side of the second type groove 4, the third type groove 6 is distributed on the outer side of the second type groove 4 and is vertical to the first vertical groove 42A, one end of the third type groove 6 is communicated with the first vertical groove 42A, the fourth type groove 7 is distributed on the outer side of the second type groove 4 and is vertical to the second vertical groove 42B, one end of the fourth type groove 7 is communicated with the second vertical groove 42B, the fifth type groove 5 is positioned on the inner side of the second type groove 4, a pair of adjacent first type grooves 3 is replaced by a fifth type groove 5, the fifth type groove 5 is vertical to the second vertical groove 42B, one end of the fifth type groove 5 is communicated with the second vertical groove 42B, but the other end of the fifth type groove 5 is not communicated with the first vertical groove 42A, the sixth type groove 24 is arranged between the adjacent fifth type grooves 5, and two ends of the sixth grooves 24 are respectively perpendicular to and communicated with two adjacent fifth grooves 5, and the sixth grooves 24 are parallel to each other.

A second conductive type body region 15 is arranged on the surface of the first conductive type epitaxial layer 2 between the adjacent first type trenches 3, the second conductive type body region 15 is a P-type body region, a first conductive type source region 16 is arranged on the surface of the second conductive type body region 15, the first type trenches 3 penetrate through the second conductive type body region 15 to enter the first conductive type epitaxial layer 2, first type conductive polysilicon 8 is arranged on the lower half section of the first type trenches 3, second type conductive polysilicon 9 is arranged on the upper half section of the first type trenches 3, the first type conductive polysilicon 8 and the second type conductive polysilicon 9 are insulated through a first type insulating medium 12, the first type conductive polysilicon 8 is insulated from the epitaxial layer through a field oxide layer 10, the second type conductive polysilicon 9 is insulated from the epitaxial layer through a gate oxide layer 11, and a second type insulating medium 14 is arranged above the first type trenches 3 and the first conductive type source region 16, a source metal 19 is disposed above the second type insulating medium 14, and the source metal 19 is in ohmic contact with the first conductivity type source region 16 and the second conductivity type body region 15 through the first type via 17.

A second conductive type body region 15 is arranged on the surface of the first conductive type epitaxial layer 2 between the second type parallel groove 41 and the adjacent fifth type groove 5, the second type parallel groove 41 penetrates through the second conductive type body region 15 to enter the first conductive type epitaxial layer 2, a first type conductive polysilicon 8 is arranged at the lower half section of the second type parallel groove 41, a second type conductive polysilicon 9 is arranged at the position of the upper half section close to the inner side, a third type insulating medium 13 is arranged at the position of the upper half section close to the outer side, the first type conductive polysilicon 8 and the second type conductive polysilicon 9 are insulated by a first type insulating medium 12, the first type conductive polysilicon 8 is insulated from the epitaxial layer by a field oxide layer 10, the second type conductive polysilicon 9 is insulated from the epitaxial layer by a gate oxide layer 11, a second type insulating medium 14 is arranged above the second type parallel groove 41 and the second conductive type body region 15, a source metal 19 is provided above the second type of insulating medium 14, which source metal 19 is in ohmic contact with the second conductivity type body region 15 through the first type of via 17.

The lower half section of the second vertical trench 42B is provided with a first type of conductive polysilicon 8, the upper half section is filled with a third type of insulating medium 13, and the first type of conductive polysilicon 8 is insulated from the epitaxial layer by a field oxide layer 10.

The lower half section in the fourth type groove 7 is provided with a first type of conductive polysilicon 8, the upper half section is filled with a third type of insulating medium 13, and the first type of conductive polysilicon 8 is insulated from the epitaxial layer through a field oxide layer 10; a second type of insulating medium 14 is arranged above the fourth type of groove 7 and the epitaxial layer, a source metal 19 is arranged above the second type of insulating medium 14, and the source metal 19 is in ohmic contact with the first type of conductive polysilicon 8 through a third type of through hole 22;

The field oxide layer 10, the gate oxide layer 11, the first insulating dielectric 12, the second insulating dielectric 14 and the third insulating dielectric 13 are made of silicon dioxide.

Those of ordinary skill in the art will understand that: the above description is only exemplary of the present invention and should not be construed as limiting the present invention, and any modifications, equivalents, improvements and the like made within the spirit of the present invention should be included in the scope of the present invention.

Claims

1. A Schottky-integrated shielding grid groove power semiconductor structure comprises a first conduction type substrate (1), wherein a first conduction type epitaxial layer (2) is arranged above the first conduction type substrate (1), and the Schottky-integrated shielding grid groove power semiconductor structure is characterized in that six types of grooves are formed in the surface of the first conduction type epitaxial layer (2) in a overlooking angle, and first type grooves (3) are mutually parallel and uniformly distributed; second grooves (4) are arranged around the first grooves (3) in a surrounding mode and comprise second parallel grooves (41) and second vertical grooves (42), and the second vertical grooves (42) comprise first vertical grooves (42A) and second vertical grooves (42B) which are vertically arranged at the left end and the right end of the first grooves (3); a third groove (6) which is perpendicular to the first vertical groove (42A) is arranged on the outer side of the second groove (4), and one end of the third groove (6) is communicated with the first vertical groove (42A); a fourth groove (7) perpendicular to the second vertical groove (42B) is arranged on the outer side of the second groove (4), and one end of the fourth groove (7) is communicated with the second vertical groove (42B); a fifth groove (5) is arranged on the inner side of the second groove (4), at least one pair of adjacent first grooves (3) is replaced by a corresponding pair of fifth grooves (5), the fifth grooves (5) are perpendicular to the second vertical grooves (42B), one end of each fifth groove (5) is communicated with the second vertical groove (42B), and the other end of each fifth groove (5) is not communicated with the first vertical groove (42A); a plurality of parallel sixth grooves (24) are arranged between the adjacent fifth grooves (5), and two ends of each sixth groove (24) are respectively perpendicular to and communicated with the two adjacent fifth grooves (5);

a second conductive type body region (15) is arranged on the surface of the first conductive type epitaxial layer (2) between the adjacent first type grooves (3), a first conductive type source region (16) is arranged on the surface of the second conductive type body region (15), the first type grooves (3) penetrate through the second conductive type body region (15) to enter the first conductive type epitaxial layer (2), first type conductive polycrystalline silicon (8) is arranged on the lower half section of the first type grooves (3), second type conductive polycrystalline silicon (9) is arranged on the upper half section of the first type grooves (3), the first type conductive polycrystalline silicon (8) and the second type conductive polycrystalline silicon (9) are insulated through a first type insulating medium (12), the first type conductive polycrystalline silicon (8) is insulated from the first conductive type epitaxial layer (2) through a field oxide layer (10), and the second type conductive polycrystalline silicon (9) is insulated from the first conductive type epitaxial layer (2) through a gate oxide layer (11), a second type of insulating medium (14) is arranged above the first type of groove (3) and the first conductive type source region (16), a source metal (19) is arranged above the second type of insulating medium (14), and the source metal (19) is in ohmic contact with the first conductive type source region (16) and the second conductive type body region (15) through a first type of through hole (17);

a second conductive type body region (15) is arranged on the surface of the first conductive type epitaxial layer (2) between the second parallel groove (41) and the adjacent first groove (3) or fifth groove (5), the second parallel groove (41) penetrates through the second conductive type body region (15) to enter the first conductive type epitaxial layer (2), a first conductive polycrystalline silicon (8) is arranged at the lower half section of the second parallel groove (41), a second conductive polycrystalline silicon (9) is arranged at the position, close to the inner side, of the upper half section, a third insulating medium (13) is arranged at the position, close to the outer side, of the upper half section, the first conductive polycrystalline silicon (8) and the second conductive polycrystalline silicon (9) are insulated through a first insulating medium (12), and the first conductive polycrystalline silicon (8) is insulated from the first conductive type epitaxial layer (2) through a field oxide layer (10), the second type of conductive polysilicon (9) is insulated from the first conductive type epitaxial layer (2) through a gate oxide layer (11), a second type of insulating medium (14) is arranged above the second type of parallel groove (41) and the second conductive type body region (15), source metal (19) is arranged above the second type of insulating medium (14), and the source metal (19) is in ohmic contact with the second conductive type body region (15) through a first type of through hole (17);

the lower half section of the first vertical groove (42A) is provided with first type conductive polycrystalline silicon (8), the position of the upper half section close to the inner side is provided with second type conductive polycrystalline silicon (9), the position of the upper half section close to the outer side is provided with a third type insulating medium (13), the first type conductive polycrystalline silicon (8) is insulated from the first conductive type epitaxial layer (2) through a field oxide layer (10), and the second type conductive polycrystalline silicon (9) is insulated from the first conductive type epitaxial layer (2) through a gate oxide layer (11);

the second vertical groove (42B) is filled with first conductive polysilicon (8), and the first conductive polysilicon (8) is insulated from the first conductive epitaxial layer (2) through the field oxide layer (10);

the lower half section of the third type groove (6) is provided with first type conductive polycrystalline silicon (8), the middle position of the upper half section is provided with second type conductive polycrystalline silicon (9), two sides of the second type conductive polycrystalline silicon (9) are provided with third type insulating mediums (13), and the first type conductive polycrystalline silicon (8) is insulated from the first conductive type epitaxial layer (2) through a field oxide layer (10); a second type of insulating medium (14) is arranged above the third type of groove (6) and the first conductive type epitaxial layer (2), a gate metal (20) is arranged above the second type of insulating medium (14), and the gate metal (20) is in ohmic contact with the second type of conductive polysilicon (9) through a second type of through hole (21);

the fourth type of groove (7) is filled with first type of conductive polysilicon (8), and the first type of conductive polysilicon (8) is insulated from the first conductive type epitaxial layer (2) through a field oxide layer (10); a second type of insulating medium (14) is arranged above the fourth type of groove (7) and the first conductive type epitaxial layer (2), a source metal (19) is arranged above the second type of insulating medium (14), and the source metal (19) is in ohmic contact with the first type of conductive polycrystalline silicon (8) through a third type of through hole (22);

the lower half sections of the sixth type groove (24) and the fifth type groove (5) are provided with first type conductive polycrystalline silicon (8), the upper half section is provided with second type conductive polycrystalline silicon (9), the first type conductive polycrystalline silicon (8) and the second type conductive polycrystalline silicon (9) are insulated through a first type insulating medium (12), the first type conductive polycrystalline silicon (8) is insulated from the first conductive type epitaxial layer (2) through a field oxide layer (10), the second type conductive polycrystalline silicon (9) is insulated from the first conductive type epitaxial layer (2) through a gate oxide layer (11), a second type insulating medium (14) is arranged above the fifth type groove (5), the sixth type groove (24) and the epitaxial layer, a source electrode metal (19) is arranged above the second type insulating medium (14), and the source electrode metal (19) is in ohmic contact with the second type conductive polycrystalline silicon (9) in the sixth type groove (24) through a fourth type through hole (23), the epitaxial layer region between the adjacent sixth type grooves (24) is a Schottky contact region, and the source metal (19) is in Schottky contact with the epitaxial layer in the Schottky contact region through a fifth type through hole (18);

the first conductive polycrystalline silicon (8) in the six types of grooves is electrically connected with the potential of the source metal (19); the second conductive polysilicon (9) in the first trench (3), the second trench (4) and the third trench (6) is electrically connected with the potential of the gate metal (20); the fifth type of groove (5) and the second type of conductive polysilicon (9) in the sixth type of groove (24) are electrically connected with the potential of the source metal (19).

2. The schottky-integrated shielded gate trench power semiconductor structure of claim 1, wherein the length of the epitaxial layer (2) of the first conductivity type between adjacent trenches (24) of the sixth type in a direction parallel to the trenches (5) of the fifth type is 0.5 to 100 μm.

3. The schottky barrier trench power semiconductor structure of claim 1, wherein the lower half of the fourth trench (7) is provided with a first conductive polysilicon (8), the upper half of the fourth trench is provided with a third insulating medium (13), the first conductive polysilicon (8) is insulated from the epitaxial layer by a field oxide layer (10), the fourth trench (7) and the first conductive epitaxial layer (2) are provided with a second insulating medium (14), a source metal (19) is arranged above the second insulating medium (14), and the source metal (19) penetrates through the second insulating medium (14) and the third insulating medium (13) through a third through hole (22) and is electrically connected with the first conductive polysilicon (8).

4. The schottky-integrated shielded gate trench power semiconductor structure as claimed in claim 1, wherein the second vertical trench (42B) is provided with a first type of conductive polysilicon (8) in the lower half and a third type of insulating dielectric (13) in the upper half, the first type of conductive polysilicon (8) being insulated from the first conductivity type epitaxial layer (2) by a field oxide layer (10).

5. The schottky-integrated shielded gate trench power semiconductor structure of claim 1 wherein the second-type parallel trenches (41) are filled with a first-type conductive polysilicon (8), the first-type conductive polysilicon (8) being insulated from the epitaxial layer by a field oxide layer (10).

6. The schottky-integrated shielded gate trench power semiconductor structure of claim 1, wherein the field oxide layer (10), the gate oxide layer (11), the first type of insulating dielectric (12), the second type of insulating dielectric (14), and the third type of insulating dielectric (13) are made of silicon dioxide or silicon nitride.

7. The schottky-integrated shielded gate trench power semiconductor structure of any of claims 1-6, wherein the power semiconductor structure is an N-type power semiconductor device or a P-type power semiconductor device;

when the power semiconductor structure is an N-type power semiconductor device, the first conduction type is an N type, and the second conduction type is a P type;

when the power semiconductor structure is a P-type semiconductor device, the first conduction type is a P-type, and the second conduction type is an N-type.