CN218160391U - Solar cell based on N-type silicon substrate - Google Patents

Abstract

The application provides a solar cell based on N type silicon substrate relates to the solar cell field, solves the problem of how to promote the photoelectric conversion efficiency of solar cell based on N type silicon substrate. The solar cell includes: the N-type silicon chip comprises an N-type silicon chip, a first passivation anti-reflection layer, a second passivation anti-reflection layer, a first tunneling layer, a first polycrystalline silicon layer and a first electrode, wherein the first tunneling layer, the first polycrystalline silicon layer and the first electrode are sequentially stacked on a first surface of the N-type silicon chip; the p-type emitter layer, the second tunneling layer, the second polycrystalline silicon layer and the second electrode are sequentially stacked on the second surface of the N-type silicon wafer; wherein the first passivation anti-reflection layer surrounds the first tunneling layer, the first polysilicon layer and a portion of the first electrode; a second passivation anti-reflection layer surrounds the second tunneling layer, the second polysilicon layer and a part of the second electrode; the first tunneling layer is in contact with a part of the first surface of the N-type silicon wafer; the second tunneling layer is in contact with a portion of the p-type emitter layer.

Description

Solar cell based on N-type silicon substrate

Technical Field

The application relates to the field of solar cells, in particular to a solar cell based on an N-type silicon substrate.

Background

Solar cells based on N-type silicon substrates tend to have few carriers (minority carriers). Due to the fact that minority carriers are long in service life and the light-induced attenuation is reduced, the solar cell based on the N-type silicon substrate has a larger efficiency improvement space, and becomes a mainstream research direction in the field of solar cells.

However, in the prior art, an electrode arranged on the surface of the solar cell based on the N-type silicon substrate is directly contacted with the p-type emitter layer, so that a part of minority carriers (for example, holes) in the solar cell can migrate to an electrode region and be combined with a part of majority carriers (electrons), that is, there is severe recombination in the contact region of the electrode and the p-type emitter layer, so that the photoelectric conversion efficiency of the solar cell is reduced because the electron and hole pairs are combined before being effectively utilized.

Therefore, a solution for improving the photoelectric conversion efficiency of the N-type silicon substrate based solar cell is needed.

SUMMERY OF THE UTILITY MODEL

The utility model provides a solar cell based on N type silicon substrate can be used for solving the technical problem who how to promote solar cell's photoelectric conversion efficiency based on N type silicon substrate.

The embodiment of the utility model provides a solar cell based on N type silicon substrate, include: the device comprises an N-type silicon wafer, a first passivation anti-reflection layer, a second passivation anti-reflection layer, a first tunneling layer, a first polycrystalline silicon layer and a first electrode, wherein the first tunneling layer, the first polycrystalline silicon layer and the first electrode are sequentially stacked on a first surface of the N-type silicon wafer; the p-type emitter layer, the second tunneling layer, the second polycrystalline silicon layer and the second electrode are sequentially stacked on the second surface of the N-type silicon wafer;

the first passivation anti-reflection layer is arranged on the first surface of the N-type silicon wafer and is in contact with the first surface of the N-type silicon wafer, and the first passivation anti-reflection layer surrounds the first tunneling layer, the first polycrystalline silicon layer and a part of the first electrode;

the second passivation anti-reflection layer is arranged on the second surface of the N-type silicon wafer and is in contact with the p-type emitter layer, and the second passivation anti-reflection layer surrounds the second tunneling layer, the second polycrystalline silicon layer and a part of the second electrode;

the first tunneling layer is in contact with a part of the first surface of the N-type silicon wafer; the p-type emitter layer is in contact with the second surface of the N-type silicon wafer, and the second tunneling layer is in contact with a part of the p-type emitter layer.

Optionally, in one embodiment, a first surface of the first electrode is in contact with the first polysilicon layer, and the first passivation anti-reflective layer surrounds the first surface of the first electrode;

and/or a second surface of the second electrode is in contact with the second polysilicon layer, and the second passivation anti-reflection layer surrounds the second surface of the second electrode.

Optionally, in one embodiment, the first target surface of the first polysilicon layer is in contact with the first surface of the first electrode, and the first surface of the first electrode is equal in area to the first target surface of the first polysilicon layer;

and/or a second target surface of the second polysilicon layer is in contact with a second surface of the second electrode, and the second surface of the second electrode and the second target surface of the second polysilicon layer are equal in area.

Optionally, in one embodiment, the first passivation anti-reflective layer is in contact with all of the first tunneling layer, the first polysilicon layer, and a portion of the first electrode;

and/or the second passivation anti-reflection layer is in contact with the p-type emitter layer, the second tunneling layer, the second polysilicon layer, and a portion of the second electrode.

Optionally, in one embodiment, the first electrode includes a first portion in contact with the first polysilicon layer and the first passivation anti-reflective layer, respectively, and a second portion extending with respect to the first passivation anti-reflective layer;

and/or the second electrode comprises a third part and a fourth part, the third part is respectively contacted with the second polycrystalline silicon layer and the second passivation anti-reflection layer, and the fourth part extends relative to the second passivation anti-reflection layer.

Optionally, in an embodiment, vertical projections of the first tunneling layer, the first polysilicon layer, and the first electrode on the N-type silicon wafer coincide; and/or the vertical projections of the second tunneling layer, the second polycrystalline silicon layer and the second electrode on the N-type silicon wafer are superposed.

Optionally, in one embodiment, the thickness of the first tunneling layer and the thickness of the second tunneling layer are equal; the thickness of the first polycrystalline silicon layer is equal to that of the second polycrystalline silicon layer; the thickness of the first passivation anti-reflective layer and the thickness of the second passivation anti-reflective layer are equal.

Optionally, in one embodiment, the thickness of the first tunneling layer and the thickness of the second tunneling layer are both 1-3nm; the thickness of the first polycrystalline silicon layer and the thickness of the second polycrystalline silicon layer are both 100-150nm; the thickness of the first passivation antireflection layer and the thickness of the second passivation antireflection layer are both 160-200nm.

Optionally, in one embodiment, the first tunneling layer and the first polysilicon layer form a TOPCon structure and the second tunneling layer and the second polysilicon layer form a TOPCon structure.

Optionally, in an embodiment, the material of the first passivation anti-reflection layer is silicon nitride or silicon oxynitride; the second passivation anti-reflection layer is made of silicon nitride or silicon oxynitride.

The utility model discloses the beneficial effect who brings as follows:

the solar cell based on N type silicon substrate that this application embodiment provided includes: the device comprises an N-type silicon wafer, a first passivation anti-reflection layer, a second passivation anti-reflection layer, a first tunneling layer, a first polycrystalline silicon layer and a first electrode, wherein the first tunneling layer, the first polycrystalline silicon layer and the first electrode are sequentially stacked on a first surface of the N-type silicon wafer; the p-type emitter layer, the second tunneling layer, the second polycrystalline silicon layer and the second electrode are sequentially stacked on the second surface of the N-type silicon wafer; wherein the first passivation anti-reflective layer is disposed on and in contact with the first surface, the first passivation anti-reflective layer surrounding the first tunneling layer, the first polysilicon layer, and a portion of the first electrode; the second passivation anti-reflection layer is arranged on the second surface and is in contact with the p-type emitter layer, and the second passivation anti-reflection layer surrounds the second tunneling layer, the second polycrystalline silicon layer and a part of the second electrode; the first tunneling layer is in contact with a part of the first surface of the N-type silicon wafer; the p-type emitter layer is in contact with the second surface of the N-type silicon wafer, and the second tunneling layer is in contact with a part of the p-type emitter layer. Therefore, the p-type emitter layer, the second tunneling layer, the second polycrystalline silicon layer and the second electrode are sequentially stacked on the second surface of the N-type silicon wafer, the electrodes can be prevented from being directly contacted with the p-type emitter layer, on one hand, good interface passivation can be formed through the tunneling layer, different carrier tunneling potential barriers are provided, on the other hand, the transfer rate of minority carriers (holes) can be inhibited through the polycrystalline silicon layer, the recombination rate of an electrode area is reduced, meanwhile, the transfer rate of the majority carriers (electrons) is increased, the conductivity of the majority carriers is obviously improved, and the photoelectric conversion efficiency of the solar cell is improved. And because the first tunneling layer only contacts with a part of the first surface of the N-type silicon wafer, and the second tunneling layer only contacts with a part of the p-type emitter layer, the incidence efficiency of visible light can be improved to a certain extent compared with the tunneling layer covered in the whole area, thereby further improving the photoelectric conversion efficiency of the solar cell.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts. In the drawings:

fig. 1 is a schematic structural diagram of an N-type silicon substrate-based solar cell in the related art;

fig. 2 is a schematic structural diagram of a solar cell based on an N-type silicon substrate according to an embodiment of the present disclosure.

Reference numerals:

100-target N-type silicon wafer; 101-a tunneling layer; 102-a polysilicon layer; 103-an antireflection layer; 104 — back electrode; 105-target p-type emitter layer; 106-a passivation layer; 107-an antireflective layer; 108 — front electrode; 200-N type silicon chip; 201-first passivation antireflective layer; 202-second passivation anti-reflective layer; 203 — a first tunneling layer; 204 — a first polysilicon layer; 205 — a first electrode; 206-p-type emitter layer; 207 — a second tunneling layer; 208 — a second polysilicon layer; 209 — second electrode.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be described in detail and completely with reference to the following specific embodiments of the present application and the accompanying drawings. It should be apparent that the described embodiments are only some of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The features of the terms first and second in the description and in the claims of the present application may explicitly or implicitly include one or more of such features. In the description of the present application, "a plurality" means two or more unless otherwise specified. In addition, "and/or" in the specification and claims means at least one of connected objects, a character "/" generally means that a preceding and succeeding related objects are in an "or" relationship.

In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the present application.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in this application will be understood to be a specific case for those of ordinary skill in the art.

Fig. 1 is a schematic structural diagram of a solar cell based on an N-type silicon substrate in the related art. As shown in fig. 1, a solar cell based on an N-type silicon substrate in the related art includes a target N-type silicon wafer 100, and a tunneling layer 101, a polysilicon layer 102, an anti-reflection layer 103, and a back electrode 104 sequentially disposed on a back surface of the target N-type silicon wafer 100; and a target p-type emitter layer 105, a passivation layer 106, an anti-reflection layer 107, and a front electrode 108 sequentially disposed on the front surface of the target N-type silicon wafer 100. The front electrode 108 is in direct contact with the target p-type emitter layer 105. As described in the background of the present application, since the front electrode 108 is directly in contact with the target p-type emitter layer 105, a part of minority carriers (holes) in the solar cell will migrate to the electrode region and recombine with a part of majority carriers (electrons), so that the electron and hole pairs recombine before being effectively utilized, and the photoelectric conversion efficiency of the solar cell is low.

Based on this, the embodiment of the application provides a solar cell based on an N-type silicon substrate, which is used for solving the technical problem of how to improve the photoelectric conversion efficiency of the solar cell.

Fig. 2 is a schematic structural diagram of a solar cell based on an N-type silicon substrate according to an embodiment of the present disclosure. As shown in fig. 2, an N-type silicon substrate-based solar cell provided in an embodiment of the present application includes: the passivation structure comprises an N-type silicon wafer 200, a first passivation anti-reflection layer 201, a second passivation anti-reflection layer 202, a first tunneling layer 203, a first polycrystalline silicon layer 204 and a first electrode 205, wherein the first tunneling layer 203, the first polycrystalline silicon layer 204 and the first electrode 205 are sequentially stacked on a first surface of the N-type silicon wafer 200; a p-type emitter layer 206, a second tunneling layer 207, a second polysilicon layer 208 and a second electrode 209 which are sequentially stacked on the second surface of the N-type silicon wafer 200; wherein the first passivation anti-reflection layer 201 is disposed on the first surface of the N-type silicon wafer 200 and is in contact with the first surface of the N-type silicon wafer 200, and the first passivation anti-reflection layer 201 surrounds the first tunneling layer, the first polysilicon layer 204, and a portion of the first electrode 205; the second passivation anti-reflective layer 202 is disposed on the second surface of the N-type silicon wafer 200 and contacts the p-type emitter layer 206, and the second passivation anti-reflective layer 202 surrounds the second tunneling layer 207, the second polysilicon layer 208, and a portion of the second electrode 209; the first tunneling layer is in contact with a part of the first surface of the N-type silicon wafer; the p-type emitter layer is in contact with the second surface of the N-type silicon wafer, and the second tunneling layer is in contact with a part of the p-type emitter layer.

The embodiment of the application provides a solar cell based on N type silicon substrate, through the second surface at N type silicon chip stacks gradually and sets up p type emitter layer, the second tunnel layer, second polycrystalline silicon layer and second electrode, can avoid the electrode direct with the contact of p type emitter layer, thereby on the one hand can form good interface passivation through the tunnel layer, provide different carrier tunneling potential barriers, on the other hand can restrain the migration rate of minority carrier (hole) through the polycrystalline silicon layer, reduce the recombination rate of electrode area, increase the migration rate of majority carrier (electron) simultaneously, show the conductivity of improving the majority carrier, promote solar cell's photoelectric conversion efficiency. And because the first tunneling layer only contacts with a part of the first surface of the N-type silicon wafer, and the second tunneling layer only contacts with a part of the p-type emitter layer, the incidence efficiency of visible light can be improved to a certain extent compared with the tunneling layer covered in the whole area, thereby further improving the photoelectric conversion efficiency of the solar cell.

In addition, because the tunneling layer and the polycrystalline silicon layer have good contact performance, compared with a structure that the electrode is in direct contact with the p-type emitter layer, the solar cell based on the N-type silicon substrate provided by the embodiment of the application can reduce the contact resistance of the electrode contact area by arranging the tunneling layer and the polycrystalline silicon layer between the electrode and the p-type emitter layer, and further improves the photoelectric conversion efficiency of the solar cell.

In the embodiment of the application, the first passivation anti-reflection layer 201 and the second passivation anti-reflection layer 202 can increase the transmittance of visible light on the surface of the solar cell, reduce reflection loss, and improve the photoelectric conversion efficiency of the solar cell. The p-type emitter layer 206 may form a PN junction with the N-type silicon wafer 200. The first electrode 205 and the second electrode 209 may both be metal electrodes.

The p-type emitter layer 206 may be prepared by performing front-side boron diffusion on the second surface of the textured N-type silicon wafer 200. The first tunneling layer 203 and the second tunneling layer 207 can be prepared by depositing a tunneling oxide layer on the surface of the N-type silicon wafer 200. After the first tunneling layer 203 is disposed on the first surface of the N-type silicon wafer 200, a first polysilicon layer 204 may be deposited on a single surface by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, and phosphorus is doped into the first polysilicon layer 204 to form a phosphosilicate Glass (PSG) layer, so that the doped first polysilicon layer 204 and the first tunneling layer 203 form a Tunnel Oxide passive Contact (TOPCon) structure of the first surface based on the selective carrier principle. Similarly, after the second tunneling layer 207 is disposed on the second surface of the N-type silicon wafer 200, a second polysilicon layer 208 may be deposited on a single surface by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, and phosphorus is doped into the second polysilicon layer 208 to form a phosphosilicate Glass (PSG) layer, so that the doped second polysilicon layer 208 and the second tunneling layer 207 form a Tunnel Oxide passivation Contact (TOPCon) structure based on the selective carrier principle on the second surface.

The coverage areas of the first tunneling layer 203, the first polysilicon layer 204, the second tunneling layer 207, and the second polysilicon layer 208 can be set according to actual requirements. Specifically, taking the second tunneling layer 207 and the second polysilicon layer 208 as an example, the p-type emitter layer 206, the second tunneling layer 207, and the second polysilicon layer 208 are sequentially stacked on the second surface of the N-type silicon wafer 200, an acid-resistant mask having a desired grid line pattern may be screen-printed on the second surface of the N-type silicon wafer 200, the second tunneling layer 207 and the second polysilicon layer 208 outside the region covered by the mask may be removed by a potassium hydroxide solution, and then the mask may be removed by a trench-type machine with hydrogen fluoride having a concentration of 5%, so that the second tunneling layer 207 and the second polysilicon layer 208 are formed in a selected region on the second surface of the N-type silicon wafer 200. In the same way, the first tunneling layer 203 and the first polysilicon layer 204 may be disposed on the first surface of the N-type silicon wafer 200 in the selected region. Of course, it can be understood that if the second tunneling layer 207 and the second polysilicon layer 208 of the selection region are disposed on the second surface of the N-type silicon wafer 200, and then the first surface of the N-type silicon wafer 200 is processed, the second surface of the N-type silicon wafer 200 may be protected by a water film before the potassium hydroxide solution is used.

After the tunneling layer and the polysilicon layer of the selection region are disposed on the first surface and/or the second surface of the N-type silicon wafer 200, the first passivation anti-reflective layer 201 and/or the second passivation anti-reflective layer 202 may be prepared by using a PECVD method. Finally, screen printing and sintering are carried out on the corresponding pattern areas on the first surface and the second surface of the N-type silicon wafer 200 to form a first electrode 205 and a second electrode 209.

It should be noted that fig. 1 is only an example of the present application, and should not be construed as limiting the present application. In practice, the first passivation anti-reflective layer 201 may surround only a portion of the first tunneling layer 203, the first polysilicon layer 204, and the first electrode 205, but not contact the first tunneling layer 203, the first polysilicon layer 204, or the first electrode 205. Of course, the first passivation anti-reflective layer 201 may also be in contact with at least one of the first tunneling layer 203, the first polysilicon layer 204, and the first electrode 205. Similarly, the second passivation anti-reflective layer 202 may not contact the second tunneling layer 207, the second polysilicon layer 208, and the second electrode 209, or the second passivation anti-reflective layer 202 may contact at least one of the second tunneling layer 207, the second polysilicon layer 208, and the second electrode 209.

Referring to the orientation shown in fig. 1, in the case where the upper surface of the first polysilicon layer 204 is in contact with the lower surface of the first tunneling layer 203 and the lower surface of the first polysilicon layer 204 is in contact with the upper surface of the first electrode 205, the area of the lower surface of the first polysilicon layer 204 may be greater than or equal to the area of the upper surface of the first electrode 205. The area of the lower surface of the first tunneling layer 203 may also be greater than or equal to the area of the upper surface of the first polysilicon layer 204. The first polysilicon layer 204 may be stacked in the middle region of the first tunneling layer 203, or stacked in the edge region of the first tunneling layer 203. In the case where the lower surface of the second polysilicon layer 208 is in contact with the upper surface of the second tunneling layer 207 and the upper surface of the second polysilicon layer 208 is in contact with the lower surface of the second electrode 209, the area of the upper surface of the second polysilicon layer 208 may be greater than or equal to the area of the lower surface of the second electrode 209. The area of the upper surface of the second tunneling layer 207 may be greater than or equal to the area of the lower surface of the second polysilicon layer 208. The second polysilicon layer 208 may be stacked in the middle region of the second tunneling layer 207, or stacked in the edge region of the second tunneling layer 207.

Of course, the structures (e.g., thickness, surface area) of the first tunneling layer 203 and the second tunneling layer 207 may be the same or different. The first polysilicon layer 204 and the second polysilicon layer 208 may also have the same or different structures (e.g., thickness, surface area).

In one embodiment, a first surface of the first electrode 205 is in contact with the first polysilicon layer 204, and the first passivation anti-reflective layer 201 surrounds the first surface of the first electrode 205; and/or a second surface of the second electrode 209 is in contact with the second polysilicon layer 208, and the second passivation anti-reflective layer 202 surrounds the second surface of the second electrode 209.

In the embodiment of the present application, the first surface of the first electrode 205 may be in contact with the first polysilicon layer 204, and the first polysilicon layer 204 may cover the first surface of the first electrode 205. A second surface of the second electrode 209 may be in contact with the second polysilicon layer 208, and the second polysilicon layer 208 may cover the second surface of the second electrode 209. The area covered by the first polysilicon layer 204 may be greater than or equal to the area of the first surface. The area covered by the second polysilicon layer 208 may be greater than or equal to the area of the second surface.

In one embodiment, a first target surface of the first polysilicon layer 204 is in contact with a first surface of the first electrode 205, the first surface of the first electrode 205 being equal in area to the first target surface of the first polysilicon layer 204; and/or a second target surface of the second polysilicon layer 208 is in contact with a second surface of the second electrode 209, the second surface of the second electrode 209 being equal in area to the second target surface of the second polysilicon layer 208.

In one embodiment, the first passivation anti-reflective layer 201 is in contact with all of the first tunneling layer 203, the first polysilicon layer 204, and a portion of the first electrode 205; and/or the second passivation anti-reflective layer 202 is in contact with all of the p-type emitter layer 206, the second tunneling layer 207, the second polysilicon layer 208, and a portion of the second electrode 209.

In one embodiment, the first electrode 205 includes a first portion in contact with the first polysilicon layer 204 and the first passivation anti-reflective layer 201, respectively, and a second portion extending with respect to the first passivation anti-reflective layer 201; and/or the second electrode 209 comprises a third portion in contact with the second polysilicon layer 208 and the second passivation anti-reflective layer 202, respectively, and a fourth portion extending with respect to the second passivation anti-reflective layer 202.

In one embodiment, the vertical projections of the first tunneling layer 203, the first polysilicon layer 204 and the first electrode 205 on the N-type silicon wafer 200 coincide; and/or the vertical projections of the second tunneling layer 207, the second polysilicon layer 208 and the second electrode 209 on the N-type silicon wafer 200 coincide. So, can only set up tunneling layer and polycrystalline silicon layer on first electrode and/or second electrode vertical projection area on N type silicon chip, compare in setting up tunneling layer and the polycrystalline silicon layer that covers the whole surfaces of N type silicon chip, this kind of mode of setting up tunneling layer and polycrystalline silicon layer in the selection area can avoid causing the photo-generated current loss because of tunneling layer and polycrystalline silicon layer have great light absorption, further promotes solar cell's photoelectric conversion efficiency.

In one embodiment, the thickness of the first tunneling layer 203 and the thickness of the second tunneling layer 207 are equal; the thickness of the first polysilicon layer 204 is equal to the thickness of the second polysilicon layer 208; the thickness of the first passivation anti-reflective layer 201 and the thickness of the second passivation anti-reflective layer 202 are equal.

In one embodiment, the thickness of the first tunneling layer 203 and the thickness of the second tunneling layer 207 are both 1-3nm; the thickness of the first polysilicon layer 204 and the thickness of the second polysilicon layer 208 are both 100-150nm; the thickness of the first passivation anti-reflection layer 201 and the thickness of the second passivation anti-reflection layer 202 are both 160-200nm.

In one embodiment, the first tunneling layer 203 and the first polysilicon layer 204 form a TOPCon structure, and the second tunneling layer 207 and the second polysilicon layer 208 form a TOPCon structure; the first passivation anti-reflection layer 201 is made of silicon nitride or silicon oxynitride; the material of the second passivation anti-reflective layer 202 is silicon nitride or silicon oxynitride. Therefore, the recombination rate of the electrode area can be reduced through the TOPCon structure, the contact resistance of the electrode contact area is reduced, and the photoelectric conversion efficiency of the solar cell is improved.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising one of 8230; \8230;" 8230; "does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises that element.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention in its corresponding aspects.

Claims (10)

1. A solar cell based on an N-type silicon substrate, comprising: the device comprises an N-type silicon chip, a first passivation anti-reflection layer, a second passivation anti-reflection layer, a first tunneling layer, a first polycrystalline silicon layer and a first electrode, wherein the first tunneling layer, the first polycrystalline silicon layer and the first electrode are sequentially stacked on a first surface of the N-type silicon chip; the p-type emitter layer, the second tunneling layer, the second polycrystalline silicon layer and the second electrode are sequentially stacked on the second surface of the N-type silicon wafer;

the first passivation anti-reflection layer is arranged on the first surface of the N-type silicon wafer and is in contact with the first surface of the N-type silicon wafer, and the first passivation anti-reflection layer surrounds the first tunneling layer, the first polycrystalline silicon layer and a part of the first electrode;

the second passivation anti-reflection layer is arranged on the second surface of the N-type silicon wafer and is in contact with the p-type emitter layer, and the second passivation anti-reflection layer surrounds the second tunneling layer, the second polycrystalline silicon layer and a part of the second electrode;

the first tunneling layer is in contact with a part of the first surface of the N-type silicon wafer; the p-type emitter layer is in contact with the second surface of the N-type silicon wafer, and the second tunneling layer is in contact with a part of the p-type emitter layer.

2. The solar cell of claim 1, wherein a first surface of the first electrode is in contact with the first polysilicon layer, the first passivation anti-reflective layer surrounding the first surface of the first electrode;

and/or a second surface of the second electrode is in contact with the second polysilicon layer, the second passivation anti-reflective layer surrounding the second surface of the second electrode.

3. The solar cell of claim 2, wherein the first target surface of the first polysilicon layer is in contact with the first surface of the first electrode, the first surface of the first electrode being equal in area to the first target surface of the first polysilicon layer;

and/or the second target surface of the second polysilicon layer is in contact with the second surface of the second electrode, and the second surface of the second electrode and the second target surface of the second polysilicon layer are equal in area.

4. The solar cell of any of claims 1-3, wherein the first passivated anti-reflection layer is in contact with all of the first tunneling layer, the first polysilicon layer, and a portion of the first electrode;

and/or the second passivation anti-reflection layer is in contact with the p-type emitter layer, the second tunneling layer, the second polysilicon layer and a portion of the second electrode.

5. The solar cell of any of claims 1-3, wherein the first electrode comprises a first portion in contact with the first polysilicon layer and the first passivation anti-reflective layer, respectively, and a second portion extending away from the first passivation anti-reflective layer;

and/or the second electrode comprises a third part and a fourth part, the third part is respectively contacted with the second polycrystalline silicon layer and the second passivation anti-reflection layer, and the fourth part extends relative to the second passivation anti-reflection layer.

6. The solar cell according to any one of claims 1-3, wherein the vertical projections of the first tunneling layer, the first polysilicon layer, and the first electrode on the N-type silicon wafer coincide; and/or the vertical projections of the second tunneling layer, the second polycrystalline silicon layer and the second electrode on the N-type silicon wafer are superposed.

7. The solar cell of claim 1, wherein the thickness of the first tunneling layer and the thickness of the second tunneling layer are equal; the thickness of the first polycrystalline silicon layer is equal to that of the second polycrystalline silicon layer; the thickness of the first passivation anti-reflection layer is equal to that of the second passivation anti-reflection layer.

8. The solar cell of claim 7, wherein the thickness of the first tunneling layer and the thickness of the second tunneling layer are both 1-3nm; the thickness of the first polycrystalline silicon layer and the thickness of the second polycrystalline silicon layer are both 100-150nm; the thickness of the first passivation antireflection layer and the thickness of the second passivation antireflection layer are both 160-200nm.

9. The solar cell of claim 1, wherein the first tunneling layer and the first polysilicon layer form a selective carrier-based tunnel oxide passivation contact structure, and the second tunneling layer and the second polysilicon layer form a selective carrier-based tunnel oxide passivation contact structure.

10. The solar cell of claim 1, wherein the material of the first passivation anti-reflective layer is silicon nitride or silicon oxynitride; the second passivation anti-reflection layer is made of silicon nitride or silicon oxynitride.

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