CN218123414U - Super junction structure - Google Patents
Super junction structure Download PDFInfo
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- CN218123414U CN218123414U CN202222361687.4U CN202222361687U CN218123414U CN 218123414 U CN218123414 U CN 218123414U CN 202222361687 U CN202222361687 U CN 202222361687U CN 218123414 U CN218123414 U CN 218123414U
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Abstract
The utility model provides a super junction structure introduces the doping area that has the same doping type with the second column structure through the second column structure below in the terminal area, can make the total degree of depth that the second column structure combines the doping area be greater than the first column structure in active area to can make the breakdown voltage in terminal area be higher than the active area, fix breakdown voltage in the active area, thereby improve the reliability of device.
Description
Technical Field
The utility model belongs to the semiconductor field relates to a super junction structure.
Background
Power MOSFETs (metal oxide semiconductor field effect transistors) have advantages of high switching speed, low switching loss, low driving loss, and the like, and play an important role in various power conversion, particularly in high-frequency power conversion.
In a terminal structure of a traditional power device, a field limiting ring or a field plate is usually adopted to weaken the curvature effect of a main junction, so that the purpose of improving the voltage resistance of the device is achieved. The existing super junction power device terminal structure adopts the same P column and N column in an active area and a terminal area, but the structure is difficult to well control the breakdown of a power device in a certain area.
SUMMERY OF THE UTILITY MODEL
In view of the above shortcomings of the prior art, the present invention provides a super junction structure for solving the problem that the breakdown of a power device is difficult to be well controlled in an active region in the prior art.
In order to realize the above-mentioned purpose and other relevant purposes, the utility model provides a surpass knot structure, surpass knot structure includes:
a semiconductor substrate of a first conductivity type;
an epitaxial layer of a first conductivity type, the epitaxial layer being located on the semiconductor substrate;
the first column structures are positioned in the epitaxial layer, extend along the thickness direction of the epitaxial layer, are arranged at intervals and are distributed in the active region;
the second column structures are positioned in the epitaxial layer, extend along the thickness direction of the epitaxial layer, are arranged at intervals and are distributed in the terminal area;
and the doping regions of the second conductivity type are positioned in the epitaxial layer and are arranged in one-to-one correspondence with the second column structures.
Optionally, the doped region is located below the second pillar structure and is in contact with the second pillar structure.
Optionally, the total depth of the second pillar structure in combination with the doped region is greater than that of the first pillar structure.
Optionally, the doped regions have the same topography and are arranged at equal intervals in the epitaxial layer.
Optionally, the longitudinal section of the doped region is one or a combination of a rectangle, an ellipse, a trapezoid and a V shape.
Optionally, the first pillar structure and the second pillar structure have the same depth or different depths.
Optionally, the superjunction device further comprises a passivation layer on the epitaxial layer, the passivation layer comprising a silicon dioxide layer, a silicon nitride layer, or a stack of both.
Optionally, a stop ring of the first conductivity type is provided in the termination region at an edge of the epitaxial layer remote from the active region.
Optionally, in the termination region, a body region of a second conductivity type is disposed above the second pillar structure adjacent to the active region.
Optionally, in the termination region, a metal field plate electrically connected to the second pillar structure is disposed on the epitaxial layer adjacent to the active region.
As above, the utility model discloses a super junction structure introduces the doping area that has the same doping type with the second post structure through the second post structure below at the terminal area, can make the total degree of depth that the second post structure combines the doping area be greater than the first post structure in active area to can make the breakdown voltage in terminal area be higher than the active area, fix breakdown voltage in the active area, thereby improve the reliability of device.
Drawings
Fig. 1 shows a schematic structural diagram of a super junction structure in an embodiment of the present invention.
Fig. 2 is a schematic process flow diagram of a method for manufacturing a super junction structure according to an embodiment of the present invention.
Fig. 3 is a schematic structural diagram of the embodiment of the present invention after forming the doped region.
Fig. 4 is a schematic structural diagram of the embodiment of the present invention after forming the first pillar structure and the second pillar structure.
Description of the element reference numerals
100. Semiconductor substrate
200. Epitaxial layer
201. First epitaxial layer
202. A second epitaxial layer
300. Doped region
401. First pillar structure
402. Second column structure
501. Gate oxide layer
502. Grid conducting layer
601. 602 body region
701. Source region
702. Cut-off ring
801. 802 passivation layer
901. 902 metal layer
I active region
II terminal area
S1 to S3
Detailed Description
The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The present invention can be implemented or applied by other different specific embodiments, and various details in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structure are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. Where an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
Expressions such as "between 8230%" \8230, between "may be used herein, both inclusive, and expressions such as" plurality "may be used herein, both inclusive, and expressions such as two or more, unless explicitly specified otherwise. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention in a schematic manner, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, amount and proportion of each component may be changed arbitrarily in actual implementation, and the layout of the components may be more complicated.
As shown in fig. 1, the present embodiment provides a super junction structure, including a semiconductor substrate 100 of a first conductivity type, an epitaxial layer 200 of the first conductivity type, a plurality of first pillar structures 401 of a second conductivity type, a plurality of second pillar structures 402 of the second conductivity type, and a doped region 300 of the second conductivity type; the epitaxial layer 200 is located on the semiconductor substrate 100; the first column structures 401 are located in the epitaxial layer 200, extend along the thickness direction of the epitaxial layer 200, are arranged at intervals, and are distributed in the active region I; the second pillar structures 402 are located in the epitaxial layer 200, extend along the thickness direction of the epitaxial layer 200, are arranged at intervals, and are distributed in the terminal region II; the doped regions 300 are located in the epitaxial layer 200 and are arranged in one-to-one correspondence with the second column structures 402, the doped regions 300 are located below the second column structures 402 and are in contact with the second column structures 402, and the total depth of the second column structures 402 combined with the doped regions 300 is greater than that of the first column structures 401.
Referring to fig. 1, a termination region II and an active region I share a semiconductor substrate 100 and an epitaxial layer 200. The active region I includes: a plurality of independently arranged first pillar structures 401 separated by the epitaxial layer 200 and having a different conductivity type from the epitaxial layer 200, in the epitaxial layer 200; a body region 601 of the second conductivity type located over the first pillar structure 401; source regions 701 of the first conductivity type located within body regions 601; a gate structure located on the epitaxial layer 200, the body region 601 and the source region 701, wherein the gate structure includes a gate oxide layer 501 and a gate conductive layer 502; a passivation layer 801 covering the gate structure, wherein the passivation layer 801 comprises a silicon dioxide layer, a silicon nitride layer or a lamination layer of the silicon dioxide layer and the silicon nitride layer; a metal layer 901 covering the passivation layer 801 and electrically connected to the body 601 and the source 701, wherein the metal layer 901 located in the active region I is a source metal layer.
The termination region II comprises a plurality of second pillar structures 402 separated by the epitaxial layer 200, independently disposed, and having a conductivity type different from that of the epitaxial layer 200, in the epitaxial layer 200; the doping regions 300 of the second conductivity type are located in the epitaxial layer 200, are arranged in one-to-one correspondence with the second column structures 402, are located below the second column structures 402 and are in contact with the second column structures 402, and the total depth of the second column structures 402 combined with the doping regions 300 is greater than that of the first column structures 401; a stop ring 702 located at the edge of the device and above the epitaxial layer 200; a passivation layer 802 and a metal layer 902 located on the epitaxial layer 200, where the passivation layer 802 includes a silicon dioxide layer, a silicon nitride layer, or a stack of the two, and the metal layer 902 located at the termination region II is a metal field plate; a body region 602 of the second conductivity type underlying the passivation layer 802 and overlying the second pillar structure 402 and electrically connected to the metal layer 902. In this embodiment, the doped region 300 having the same doping type as the second pillar structure 402 is introduced below the second pillar structure 402 of the terminal region II, so that the total depth of the second pillar structure 402 combined with the doped region 300 is greater than that of the first pillar structure 401, and thus the breakdown voltage of the terminal region II is higher than that of the active region I, and is fixed in the active region I, thereby improving the reliability of the device.
As an example, the doped regions 300 have the same topography and are equally spaced apart in the epitaxial layer 200.
Specifically, the shape of the doped region 300 may include a longitudinal section in a rectangular shape, an oval shape, a trapezoid shape, a V shape, etc., which may be selected according to the manufacturing process and the requirement, and is not limited herein. In this embodiment, it is preferable that the doped regions 300 have the same profile and are arranged in the epitaxial layer 200 at equal intervals, but not limited thereto, and in another embodiment, the doped regions 300 may have different profiles and/or be arranged at unequal intervals.
As an example, the first pillar structure 401 and the second pillar structure 402 have the same depth or different depths.
Specifically, when the first pillar structure 401 and the second pillar structure 402 are fabricated by the same process step, the first pillar structure 401 and the second pillar structure 402 are generally formed to have the same depth, so that before the second pillar structure 402 is formed, the doped region 300 fabricated in the epitaxial layer 200 can make the difference between the sum of the depths of the second pillar structure 402 and the doped region 300 in the terminal region II and the first pillar structure 401 in the active region I by the depth of one doped region 300, thereby facilitating process control, but not limited thereto, the first pillar structure 401 and the second pillar structure 402 can also have different depths, so that through process control, the sum of the depths of the second pillar structure 402 and the doped region 300 in the terminal region II is greater than the first pillar structure 401, and the size of the difference between the sum of the depths of the second pillar structure 402 and the doped region 300 and the depth of the first pillar structure 401 is not limited herein.
In this embodiment, the first conductive type is n-type and the second conductive type is p-type, but not limited thereto, and in another embodiment, the first conductive type may also be p-type and the corresponding second conductive type is n-type, which is not limited herein.
The present embodiment also provides a superjunction device including a superjunction structure, wherein the superjunction device may include an IGBT device or a MOSFET device.
Referring to fig. 1 and fig. 2, the present embodiment further provides a method for manufacturing a super junction structure, which can be manufactured by the following method, but is not limited thereto.
The method for preparing the super junction structure comprises the following steps:
s1: providing a semiconductor substrate 100 of a first conductivity type;
s2: epitaxially growing an epitaxial layer 200 of a first conductivity type on a semiconductor substrate 100, and forming a doped region 300 in the epitaxial layer 200;
s3: forming a plurality of first pillar structures 401 and a plurality of second pillar structures 402 of a second conductivity type in the epitaxial layer 200, where the first pillar structures 401 extend in the thickness direction of the epitaxial layer 200, are arranged at intervals and are distributed in the active region I, and the second pillar structures 402 extend in the thickness direction of the epitaxial layer 200, are arranged at intervals and are distributed in the terminal region II; the doped regions 300 and the second pillar structures 402 are disposed in a one-to-one correspondence, the second pillar structures 402 are located above the doped regions 300 and contact the doped regions 300, and the total depth of the second pillar structures 402 combined with the doped regions 300 is greater than that of the first pillar structures 401.
Optionally, in this embodiment, the first conductivity type is n-type, the corresponding second conductivity type is p-type, and the semiconductor substrate 100 is an n-type silicon substrate. In other embodiments of the present invention, the semiconductor substrate 100 may also be selected as a p-type silicon substrate or other semiconductor substrate.
As an example, the method of forming the doped region 300 includes an ion implantation method or an etch filling method; the method of forming the first pillar structure 401 and the second pillar structure 402 includes an ion implantation method or an etching filling method.
Referring to fig. 3 and 4, the steps of forming the doped region 300, the first pillar structure 401 and the second pillar structure 402 may include:
epitaxially growing a first epitaxial layer 201 of a first conductivity type on the semiconductor substrate 100;
forming a doped region 300 in the first epitaxial layer 201 by ion implantation;
growing a second epitaxial layer 202 of the first conductivity type on the first epitaxial layer 201, forming a first trench (not shown) in the second epitaxial layer 202 in the active region I by photolithography and etching, and forming a second trench (not shown) on the second epitaxial layer in the termination region II by photolithography and etching, and the second trench exposing the doped region 300;
a filling layer is formed in the first trench and the second trench to fill the trenches, so as to form a first pillar structure 401 and a second pillar structure 402.
Specifically, the method for forming the doped region 300 is not limited to the ion implantation method, and an etching filling method may also be adopted, for example, a trench may be formed in the first epitaxial layer 201 by photolithography and etching, and then deposition filling may be performed; the method for forming the first pillar structure 401 and the second pillar structure 402 may also be a step-and-ion implantation method, for example, by forming an epitaxial layer and an ion implantation region step by step, and then interconnecting the ion implantation regions in the stacked epitaxial layer by annealing, for example, to form the first pillar structure 401 and the second pillar structure 402.
As an example, the doped regions 300 are formed to have the same profile and are arranged at equal intervals in the epitaxial layer 200.
Specifically, the shape of the doped region 300 may include a longitudinal section in a rectangular shape, an oval shape, a trapezoid shape, a V shape, etc., which may be selected according to the manufacturing process and the requirement, and is not limited herein. In this embodiment, it is preferable that the doped regions 300 have the same profile and are arranged in the epitaxial layer 200 at equal intervals, but not limited thereto, and in another embodiment, the doped regions 300 may have different profiles and/or be arranged at unequal intervals.
Wherein the first pillar structure 401 and the second pillar structure 402 may be formed to have the same depth or different depths. In this embodiment, the first pillar structure 401 and the second pillar structure 402 are prepared by the same process step, so that the formed first pillar structure 401 and the second pillar structure 402 have the same depth, and therefore, before the second pillar structure 402 is formed, the depth of one doped region 300 is different between the sum of the depths of the second pillar structure 402 and the doped region 300 in the terminal region II and the first pillar structure 401 in the active region I by the doped region 300 prepared in the epitaxial layer 200, so as to facilitate process control, but not limited thereto, the first pillar structure 401 and the second pillar structure 402 may have different depths, so that the sum of the depths of the second pillar structure 402 and the doped region 300 in the terminal region II is larger than the first pillar structure 401 by process control, and the size of the difference between the sum of the depths of the second pillar structure 402 and the doped region 300 and the depth of the first pillar structure 401 is not limited herein.
To sum up, the utility model discloses a super junction structure introduces the doping area that has the same doping type with the second post structure through the second post structure below at the terminal area, can make the total degree of depth that the second post structure combines the doping area be greater than the first post structure in active area to can make the breakdown voltage in terminal area be higher than the active area, fix breakdown voltage in the active area, thereby improve the reliability of device.
The above embodiments are merely illustrative of the principles and effects of the present invention, and are not to be construed as limiting the invention. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A super junction structure, comprising:
a semiconductor substrate of a first conductivity type;
an epitaxial layer of a first conductivity type, the epitaxial layer being located on the semiconductor substrate;
the first column structures are positioned in the epitaxial layer, extend along the thickness direction of the epitaxial layer, are arranged at intervals and are distributed in the active region;
the second column structures are positioned in the epitaxial layer, extend along the thickness direction of the epitaxial layer, are arranged at intervals and are distributed in the terminal area;
and the doped regions are positioned in the epitaxial layer and are in one-to-one correspondence with the second column structures.
2. The superjunction structure of claim 1, wherein: the doped region is located below the second column structure and is in contact with the second column structure.
3. The superjunction structure of claim 1 or 2, wherein: the total depth of the second pillar structure combined with the doped region is greater than that of the first pillar structure.
4. The superjunction structure of claim 1, wherein: the doped regions have the same morphology and are arranged at equal intervals in the epitaxial layer.
5. The super junction structure of claim 1, wherein: the longitudinal section of the doped region is in one or a combination of a rectangle shape, an oval shape, a trapezoid shape and a V shape.
6. The superjunction structure of claim 1, wherein: the first pillar structure and the second pillar structure have the same depth or different depths.
7. The superjunction structure of claim 1, wherein: the superjunction device further includes a passivation layer on the epitaxial layer, the passivation layer including a silicon dioxide layer, a silicon nitride layer, or a stack of both.
8. The superjunction structure of claim 1, wherein: in the termination region, a stop ring of the first conductivity type is arranged at the edge of the epitaxial layer far away from the active region.
9. The super junction structure of claim 1, wherein: and in the terminal area, a body area of a second conduction type is arranged above the second column structure close to the active area.
10. The superjunction structure of claim 1, wherein: and in the terminal area, a metal field plate electrically connected with the second column structure is arranged on the epitaxial layer close to the active area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222361687.4U CN218123414U (en) | 2022-09-05 | 2022-09-05 | Super junction structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222361687.4U CN218123414U (en) | 2022-09-05 | 2022-09-05 | Super junction structure |
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| CN218123414U true CN218123414U (en) | 2022-12-23 |
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| CN202222361687.4U Active CN218123414U (en) | 2022-09-05 | 2022-09-05 | Super junction structure |
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