CN110137081B - Manufacturing method of silicon trench and manufacturing method of super junction structure - Google Patents
Manufacturing method of silicon trench and manufacturing method of super junction structure Download PDFInfo
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- CN110137081B CN110137081B CN201910419293.XA CN201910419293A CN110137081B CN 110137081 B CN110137081 B CN 110137081B CN 201910419293 A CN201910419293 A CN 201910419293A CN 110137081 B CN110137081 B CN 110137081B
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 211
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 211
- 239000010703 silicon Substances 0.000 title claims abstract description 211
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 36
- 238000009271 trench method Methods 0.000 title description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 48
- 238000005530 etching Methods 0.000 claims abstract description 39
- 238000000034 method Methods 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 238000003475 lamination Methods 0.000 claims abstract description 27
- 229920000642 polymer Polymers 0.000 claims abstract description 22
- 238000001259 photo etching Methods 0.000 claims abstract description 7
- 150000004767 nitrides Chemical class 0.000 claims description 7
- 238000007517 polishing process Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 description 31
- 238000010586 diagram Methods 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 8
- 238000001459 lithography Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 238000000407 epitaxy Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 238000001727 in vivo Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
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Abstract
The invention discloses a manufacturing method of a silicon groove, which comprises the following steps: step one, forming a mask lamination on the surface of a silicon substrate, wherein the mask lamination comprises a medium mask layer and a polycrystalline silicon mask layer; step two, defining a forming area of the silicon groove by photoetching, and etching the mask lamination to form a mask lamination pattern structure for opening the forming area of the silicon groove; and step three, etching the silicon substrate by taking the mask laminated graph structure as a mask to form a silicon groove with a side angle changed, and adjusting the side angle of the silicon groove through the polymer released by the polycrystalline silicon mask layer in the etching process of the silicon substrate. Therefore, the invention also provides a manufacturing method of the super junction structure. The invention can form different angles on the side surface of the groove by adopting one-time etching, and has simple process and low cost.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing a silicon trench; the invention also relates to a manufacturing method of the super junction structure.
Background
As shown in fig. 1, is a schematic diagram of a prior art superjunction device; the super junction device comprises a super junction structure composed of alternately arranged N-type columns, namely N-type thin layers 102 and P-type columns, namely P-type thin layers 103, the super junction structure is usually used as a drift region of the super junction device, the super junction device comprises a plurality of device unit structures, and each device unit structure is usually formed on the surface of the super junction structure.
In fig. 1, the super junction device is shown as a super junction MOSFET, and the device unit structure of the super junction device includes: a P well 104 is formed on the surface of the super junction structure, and a gate structure is formed on the top of the N-type column 102, where the gate structure shown in fig. 1 is a trench gate structure, and the gate structure includes a gate trench, a gate dielectric layer such as a gate oxide layer formed on the inner side surface of the gate trench, and a polysilicon gate 105 filled in the gate trench. A source region 106 is formed on the surface of the P well 104, and the source region 106 is doped with N +. The surface of the P-well 104 that is laterally covered by the polysilicon gate 105 is used to form a channel.
In the prior art, a P-type column 103 is usually formed by a trench filling process, a trench corresponding to the P-type column 103 is a super junction trench, the super junction trench is formed in an N-type epitaxial layer such as an N-type silicon epitaxial layer 102, the super junction trench is usually formed by one-time etching, and for convenience of etching and filling, a side surface of the super junction trench is of an inclined structure. P-type material such as P-type silicon epitaxial layer is filled in the super junction trench to form P-type columns 103, and N-type columns 102 are composed of N-type epitaxial layer 102 between P-type columns 103. An N-type epitaxial layer 102 is formed on the surface of a semiconductor substrate such as a silicon substrate 101. Typically, the drain region is comprised of a back side N + doped region formed by back side thinning of the silicon substrate 101.
The super junction device can utilize a PN charge balance in-vivo reduced surface electric field (Resurf) technology of a super junction structure to improve reverse Breakdown (BV) of the device and keep smaller on-resistance. Because the single trench etching is basically uniform in angle morphology, if a special structure with different angles needs to be etched for multiple times, the multiple etching causes the process to be complicated and the cost to be increased.
Disclosure of Invention
The invention aims to solve the technical problem of providing a manufacturing method of a silicon groove, which can form different angles on the side surface of the groove by adopting one-time etching, and has simple process and low cost. Therefore, the invention also provides a manufacturing method of the super junction structure.
In order to solve the above technical problem, the method for manufacturing a silicon trench provided by the present invention comprises the following steps:
providing a silicon substrate, and forming a mask lamination on the surface of the silicon substrate, wherein the mask lamination comprises a medium mask layer and a polycrystalline silicon mask layer.
And step two, defining a forming area of the silicon groove by photoetching, etching the mask lamination layer according to the photoetching definition to form a mask lamination layer pattern structure, and opening the top of the silicon substrate in the forming area of the silicon groove by the mask lamination layer pattern structure.
And step three, etching the silicon substrate by taking the mask laminated graph structure as a mask to form the silicon groove with the side angle changed, etching the polycrystalline silicon mask layer and releasing Polymer (Polymer) in the etching process of the silicon substrate, and adjusting the side angle of the silicon groove through the Polymer released by the polycrystalline silicon mask layer.
In a further improvement, the polysilicon mask layer is located at the top, the dielectric mask layer is located at the bottom, and the silicon trench is in a shuttle shape with a top side angle greater than 90 degrees and a bottom side angle less than 90 degrees.
The further improvement is that the polysilicon mask layer is positioned at the bottom in the mask lamination, the dielectric mask layer is positioned at the top, and the silicon groove is in a waist-contracting shape with a bottom side angle larger than 90 degrees and a top side angle smaller than 90 degrees.
In a further improvement, the material of the dielectric mask layer is an oxide or a nitride.
The further improvement is that a first silicon epitaxial layer is formed on the surface of the silicon substrate, and the mask lamination is formed on the surface of the first silicon epitaxial layer.
In a further improvement, step three is followed by the step of removing the mask stack.
In a further improvement, a plurality of silicon trenches are included on the same silicon substrate.
In order to solve the above technical problem, the method for manufacturing the super junction structure provided by the invention comprises the following steps:
the method comprises the steps of providing a silicon substrate, forming a first silicon epitaxial layer doped with a first conduction type on the surface of the silicon substrate, and forming a mask lamination layer on the surface of the first silicon epitaxial layer, wherein the mask lamination layer comprises a medium mask layer and a polycrystalline silicon mask layer.
And step two, defining a forming area of the silicon grooves by photoetching, wherein the number of the silicon grooves comprises a plurality of silicon grooves, etching the mask lamination layer according to the photoetching definition to form a mask lamination layer pattern structure, and opening the top of the first silicon epitaxial layer of the forming area of the silicon grooves by the mask lamination layer pattern structure.
And step three, etching the first silicon epitaxial layer by taking the mask laminated graph structure as a mask to form the silicon groove with the side angle changed, etching the polycrystalline silicon mask layer and releasing a polymer in the etching process of the first silicon epitaxial layer, and adjusting the side angle of the silicon groove by the polymer released by the polycrystalline silicon mask layer.
And fourthly, carrying out epitaxial growth, filling a second silicon epitaxial layer doped with a second conduction type in the silicon groove, forming a second conduction type column by the second silicon epitaxial layer filled in the silicon groove, forming a first conduction type column by the first silicon epitaxial layer between the second conduction type columns, and forming a super-junction structure by alternately arranging the first conduction type column and the second conduction type column.
In a further improvement, the polysilicon mask layer is located at the top, the dielectric mask layer is located at the bottom, and the silicon trench is in a shuttle shape with a top side angle greater than 90 degrees and a bottom side angle less than 90 degrees.
The further improvement is that the polysilicon mask layer is positioned at the bottom in the mask lamination, the dielectric mask layer is positioned at the top, and the silicon groove is in a waist-contracting shape with a bottom side angle larger than 90 degrees and a top side angle smaller than 90 degrees.
In a further improvement, the material of the dielectric mask layer is an oxide or a nitride.
In a further improvement, the third step is followed by a step of removing the mask stack, the step of removing the mask stack being placed before or after the filling of the second silicon epitaxial layer in the fourth step.
In a further improvement, the second silicon epitaxial layer is grown using selective epitaxy.
A further improvement is that the second silicon epitaxial layer filled in the fourth step also extends to the outside of the silicon trench, and after the second silicon epitaxial layer is filled, a step of removing the second silicon epitaxial layer outside the silicon trench by using a back etching or chemical mechanical polishing process is further included.
The further improvement is that the first conductive type is N type, and the second conductive type is P type; or the first conduction type is P type, and the second conduction type is N type.
The mask layer structure adopted in the silicon groove etching process is specially designed, the mask lamination formed by overlapping the medium mask layer and the polycrystalline silicon mask layer is mainly adopted as the mask of the final silicon etching, in the silicon etching, the polycrystalline silicon mask layer can be etched, the etched polycrystalline silicon can form more polymers, and the polymers released by the polycrystalline silicon mask layer can be attached to the side surface of the silicon groove so as to adjust the side surface angle of the silicon groove.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
fig. 1 is a schematic diagram of an existing superjunction device;
FIG. 2 is a flow chart of a method for fabricating a silicon trench according to a first embodiment of the present invention;
FIGS. 3A to 3D are device structure diagrams in steps of a method for manufacturing a silicon trench according to a first embodiment of the present invention;
FIGS. 4A to 4D are device structure diagrams in steps of a method for manufacturing a silicon trench according to a second embodiment of the present invention;
fig. 5 is a diagram of a device structure formed by a method of manufacturing a super junction structure according to a third embodiment of the present invention;
fig. 6 is a diagram of a device structure formed by a method of manufacturing a super junction structure according to a fourth embodiment of the present invention.
Detailed Description
The manufacturing method of the silicon trench of the first embodiment of the present invention:
FIG. 2 is a flow chart showing a method for fabricating a silicon trench according to a first embodiment of the present invention; fig. 3A to 3D are device structure diagrams in the steps of the method for manufacturing a silicon trench according to the first embodiment of the present invention; the method for manufacturing a silicon trench according to the first embodiment of the present invention includes the steps of:
step one, as shown in fig. 3A, a silicon substrate 1 is provided. A first silicon epitaxial layer 2 is further formed on the surface of the silicon substrate 1, and the mask stack is formed on the surface of the first silicon epitaxial layer 2.
As shown in fig. 3B, a mask stack is formed on the surface of the silicon substrate 1, wherein the mask stack includes a dielectric mask layer 201a and a polysilicon mask layer 201B. In the first embodiment of the present invention, the polysilicon mask layer 201b is located at the top of the mask stack, and the dielectric mask layer 201a is located at the bottom.
The dielectric mask layer 201a is made of oxide or nitride.
Step two, as shown in fig. 3C, defining a formation region of the silicon trench 202a by lithography, and etching the mask stack according to the definition of lithography to form a mask stack pattern structure, wherein the mask stack pattern structure opens the top of the silicon substrate 1 in the formation region of the silicon trench 202 a.
A plurality of silicon trenches 202a are included in the same silicon substrate 1.
Step three, as shown in fig. 3D, the silicon substrate 1 is etched by using the mask stack pattern structure as a mask to form the silicon trench 202a with a variable side angle, the polysilicon mask layer 201b is also etched and releases a Polymer (Polymer) in the etching process of the silicon substrate 1, and the side angle of the silicon trench is adjusted by the Polymer released by the polysilicon mask layer 201 b.
In the first embodiment of the present invention, since the polysilicon mask layer 201b is located at the top and the dielectric mask layer 201a is located at the bottom in the mask stack, the finally formed silicon trench 202a is in a shuttle shape with a top side angle greater than 90 degrees and a bottom side angle smaller than 90 degrees. Wherein the top side of the silicon trench 202a is shown as 202a2, the bottom side of the silicon trench 202a is shown as 202a1, and the included angle between the corresponding side of the silicon trench 202a and the top side of the silicon trench 202a is shown as the included angle.
And then further comprising the step of removing the mask stack.
The first embodiment of the invention specially designs the mask layer structure adopted in the etching process of the silicon trench 202b, mainly adopts the mask lamination formed by overlapping the dielectric mask layer 201a and the polysilicon mask layer 201b as the mask of the final silicon etching, the polysilicon mask layer 201b can be etched in the silicon etching, the etched polysilicon can form more polymers, the polymers released by the polysilicon mask layer 201b can be attached to the side surface of the silicon trench 202b so as to adjust the side surface angle of the silicon trench 202b, therefore, the first embodiment of the invention can adjust the side surface angle of the silicon trench 202b by arranging the polysilicon mask layer 201b in the mask lamination and can realize that different angles can be formed on the side surface of the trench by adopting one-time etching, the process is simple and the cost is low.
The manufacturing method of the silicon trench of the second embodiment of the present invention:
a flow chart of a method for manufacturing a silicon trench according to a second embodiment of the present invention is also shown with reference to fig. 2; fig. 4A to 4D are device structure diagrams in the steps of the method for manufacturing a silicon trench according to the first embodiment of the present invention; the method for manufacturing a silicon trench according to the first embodiment of the present invention includes the steps of:
step one, as shown in fig. 4A, a silicon substrate 1 is provided. A first silicon epitaxial layer 2 is further formed on the surface of the silicon substrate 1, and the mask stack is formed on the surface of the first silicon epitaxial layer 2.
As shown in fig. 4B, a mask stack is formed on the surface of the silicon substrate 1, wherein the mask stack includes a dielectric mask layer 201a and a polysilicon mask layer 201B. In the second embodiment of the present invention, the polysilicon mask layer 201b is located at the bottom of the mask stack, and the dielectric mask layer 201a is located at the top.
The dielectric mask layer 201a is made of oxide or nitride.
Step two, as shown in fig. 4C, defining a formation region of the silicon trench 202b by lithography, and etching the mask stack according to the definition of lithography to form a mask stack pattern structure, wherein the mask stack pattern structure opens the top of the silicon substrate 1 in the formation region of the silicon trench.
A plurality of silicon trenches 202b are included in the same silicon substrate 1.
Step three, as shown in fig. 4D, the silicon substrate 1 is etched by using the mask stack pattern structure as a mask to form the silicon trench 202b with a side angle varying, in the process of etching the silicon substrate 1, the polysilicon mask layer 201b is also etched and releases a Polymer (Polymer), and the side angle of the silicon trench 202b is adjusted by the Polymer released by the polysilicon mask layer 201 b.
In the second embodiment of the present invention, since the polysilicon mask layer 201b is located at the bottom and the dielectric mask layer 201a is located at the top in the mask stack, the finally formed silicon trench 202b is in a waisted shape with a bottom side angle greater than 90 degrees and a top side angle smaller than 90 degrees. Wherein, the top side of the silicon trench 202b is shown as labeled silicon trench 202b2, the bottom side of the silicon trench 202b is shown as labeled silicon trench 202b1, and the included angle between the corresponding side of the silicon trench 202b is the included angle between the side and the top side of the silicon trench 202 b.
And then further comprising the step of removing the mask stack.
The method for manufacturing the super junction structure of the third embodiment of the invention comprises the following steps:
fig. 3A to 3D show schematic diagrams of forming a silicon trench 202a in a method according to a third embodiment of the present invention, and fig. 5 shows a structure diagram of a device formed by a method for manufacturing a super junction structure according to a third embodiment of the present invention; the method for manufacturing the super junction structure of the third embodiment of the invention comprises the following steps:
step one, as shown in fig. 3A, a silicon substrate 1 is provided, and a first silicon epitaxial layer 2 doped with a first conductivity type is formed on the surface of the silicon substrate 1.
As shown in fig. 3B, a mask stack is formed on the surface of the first silicon epitaxial layer 2, wherein the mask stack includes a dielectric mask layer 201a and a polysilicon mask layer 201B.
In the third embodiment of the present invention, the polysilicon mask layer 201b is located at the top of the mask stack, and the dielectric mask layer 201a is located at the bottom.
The dielectric mask layer 201a is made of oxide or nitride.
Step two, as shown in fig. 3C, defining a formation region of the silicon trench 202a by photolithography, wherein the number of the silicon trenches 202a includes a plurality of silicon trenches, etching the mask stack according to the photolithography definition to form a mask stack pattern structure, and opening the top of the first silicon epitaxial layer 2 in the formation region of the silicon trench 202a by the mask stack pattern structure.
Step three, as shown in fig. 3D, the first silicon epitaxial layer 2 is etched by using the mask stack pattern structure as a mask to form the silicon trench 202a with a variable side angle, the polysilicon mask layer 201b is also etched and releases a polymer in the process of etching the first silicon epitaxial layer 2, and the side angle of the silicon trench 202a is adjusted by the polymer released by the polysilicon mask layer 201 b.
In the first embodiment of the present invention, since the polysilicon mask layer 201b is located at the top and the dielectric mask layer 201a is located at the bottom in the mask stack, the finally formed silicon trench 202a is in a shuttle shape with a top side angle greater than 90 degrees and a bottom side angle smaller than 90 degrees. Wherein the top side of the silicon trench 202a is shown as 202a2, the bottom side of the silicon trench 202a is shown as 202a1, and the included angle between the corresponding side of the silicon trench 202a and the top side of the silicon trench 202a is shown as the included angle.
Step four, as shown in fig. 5, performing epitaxial growth to fill a second silicon epitaxial layer 3a doped with a second conductivity type in the silicon trench 202a, forming a second conductivity type column by the second silicon epitaxial layer 3a filled in the silicon trench 202a, forming a first conductivity type column by the first silicon epitaxial layer 2 between the second conductivity type columns, and forming a super junction structure by the first conductivity type column and the second conductivity type column being alternately arranged.
The third step is followed by a step of removing the mask stack, which is placed before or after the filling of the second silicon epitaxial layer 3a of the fourth step.
The second silicon epitaxial layer 3a is grown by selective epitaxy.
The second silicon epitaxial layer 3a filled in the fourth step also extends to the outside of the silicon trench 202a, and after the second silicon epitaxial layer 3a is filled, a step of removing the second silicon epitaxial layer 3a outside the silicon trench 202a by using a back etching or chemical mechanical polishing process is further included.
In a third embodiment of the present invention, the first conductivity type is N-type and the second conductivity type is P-type. In other embodiments can also be: the first conductivity type is P-type and the second conductivity type is N-type.
The method for manufacturing the super junction structure of the fourth embodiment of the invention comprises the following steps:
fig. 4A to 4D are schematic diagrams of forming a silicon trench 202b in a method according to a fourth embodiment of the present invention, and fig. 6 is a structure diagram of a device formed by a method for manufacturing a super junction structure according to a fourth embodiment of the present invention; the method for manufacturing the super junction structure comprises the following steps:
step one, as shown in fig. 4A, a silicon substrate 1 is provided, and a first silicon epitaxial layer 2 doped with a first conductivity type is formed on the surface of the silicon substrate 1.
As shown in fig. 4B, a mask stack is formed on the surface of the first silicon epitaxial layer 2, wherein the mask stack includes a dielectric mask layer 201a and a polysilicon mask layer 201B.
In the fourth embodiment of the present invention, the polysilicon mask layer 201b is located at the bottom of the mask stack, and the dielectric mask layer 201a is located at the top.
The dielectric mask layer 201a is made of oxide or nitride.
Step two, as shown in fig. 4C, defining a formation region of the silicon trench 202b by photolithography, wherein the number of the silicon trenches 202b includes a plurality of silicon trenches, etching the mask stack according to the photolithography definition to form a mask stack pattern structure, and opening the top of the first silicon epitaxial layer 2 in the formation region of the silicon trench 202b by the mask stack pattern structure.
Step three, as shown in fig. 4D, the first silicon epitaxial layer 2 is etched by using the mask stack pattern structure as a mask to form the silicon trench 202b with a variable side angle, in the process of etching the first silicon epitaxial layer 2, the polysilicon mask layer 201b is also etched and releases a polymer, and the side angle of the silicon trench 202b is adjusted by the polymer released by the polysilicon mask layer 201 b.
In the first embodiment of the present invention, since the polysilicon mask layer 201b is located at the bottom and the dielectric mask layer 201a is located at the top in the mask stack, the finally formed silicon trench 202b is in a waisted shape with a bottom side angle greater than 90 degrees and a top side angle smaller than 90 degrees. Wherein the top side of the silicon trench 202b is shown as 202b2, the bottom side of the silicon trench 202b is shown as 202b1, and the included angle between the corresponding side of the silicon trench 202b and the top side of the silicon trench 202b is shown as the included angle.
Step four, as shown in fig. 6, performing epitaxial growth to fill a second silicon epitaxial layer 3b doped with a second conductivity type in the silicon trench 202b, forming a second conductivity type column by the second silicon epitaxial layer 3b filled in the silicon trench 202b, forming a first conductivity type column by the first silicon epitaxial layer 2 between the second conductivity type columns, and forming a super junction structure by the first conductivity type column and the second conductivity type column in an alternating arrangement.
The third step is followed by a step of removing the mask stack, which is placed before or after the filling of the second silicon epitaxial layer 3b of the fourth step.
The second silicon epitaxial layer 3b is grown by selective epitaxy.
The second silicon epitaxial layer 3b filled in the fourth step also extends to the outside of the silicon trench 202b, and after the second silicon epitaxial layer 3b is filled, a step of removing the second silicon epitaxial layer 3b outside the silicon trench 202b by using a back etching or chemical mechanical polishing process is further included.
In a fourth embodiment of the present invention, the first conductivity type is N-type and the second conductivity type is P-type. In other embodiments can also be: the first conductivity type is P-type and the second conductivity type is N-type.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (6)
1. A method for manufacturing a super junction structure is characterized by comprising the following steps:
providing a silicon substrate, forming a first silicon epitaxial layer doped with a first conduction type on the surface of the silicon substrate, and forming a mask lamination layer on the surface of the first silicon epitaxial layer, wherein the mask lamination layer comprises a medium mask layer and a polycrystalline silicon mask layer;
step two, defining a forming area of a silicon groove by photoetching, wherein the number of the silicon grooves comprises a plurality of silicon grooves, etching the mask lamination layer according to the photoetching definition to form a mask lamination layer pattern structure, and opening the top of the first silicon epitaxial layer of the forming area of the silicon groove by the mask lamination layer pattern structure;
etching the first silicon epitaxial layer by taking the mask laminated graph structure as a mask to form the silicon groove with the side angle changed, wherein the polycrystalline silicon mask layer is also etched and releases a polymer in the etching process of the first silicon epitaxial layer, and the side angle of the silicon groove is adjusted by the polymer released by the polycrystalline silicon mask layer;
the polycrystalline silicon mask layer in the mask lamination layer is positioned at the top, the medium mask layer is positioned at the bottom, and the silicon groove is in a shuttle shape with a top side angle larger than 90 degrees and a bottom side angle smaller than 90 degrees;
or the polycrystalline silicon mask layer in the mask lamination layer is positioned at the bottom, the medium mask layer is positioned at the top, and the silicon groove is in a waist-contracting shape with a bottom side angle larger than 90 degrees and a top side angle smaller than 90 degrees;
and fourthly, carrying out epitaxial growth, filling a second silicon epitaxial layer doped with a second conduction type in the silicon groove, forming a second conduction type column by the second silicon epitaxial layer filled in the silicon groove, forming a first conduction type column by the first silicon epitaxial layer between the second conduction type columns, and forming a super-junction structure by alternately arranging the first conduction type column and the second conduction type column.
2. The method of manufacturing a super junction structure according to claim 1, wherein: the dielectric mask layer is made of oxide or nitride.
3. The method of manufacturing a super junction structure according to claim 1, wherein: and step three, a step of removing the mask stack is further included after the step three, and the step of removing the mask stack is placed before or after the step four of filling the second silicon epitaxial layer.
4. The method of manufacturing a super junction structure according to claim 1, wherein: and the second silicon epitaxial layer adopts selective epitaxial growth.
5. The method of manufacturing a super junction structure according to claim 1, wherein: the second silicon epitaxial layer filled in the fourth step can also extend out of the silicon trench, and the step of removing the second silicon epitaxial layer out of the silicon trench by adopting a back etching or chemical mechanical polishing process is further included after the second silicon epitaxial layer is filled.
6. The method of manufacturing a super junction structure according to any one of claims 1 to 5, wherein: the first conductive type is N type, and the second conductive type is P type; or the first conduction type is P type, and the second conduction type is N type.
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| CN112864219A (en) * | 2019-11-12 | 2021-05-28 | 南通尚阳通集成电路有限公司 | Super junction device and manufacturing method thereof |
| CN111403275B (en) * | 2020-03-12 | 2022-08-16 | 上海华虹宏力半导体制造有限公司 | Etching method of groove |
| CN114613834A (en) * | 2020-12-08 | 2022-06-10 | 上海功成半导体科技有限公司 | Super junction device and manufacturing method |
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| KR20000072838A (en) * | 2000-08-12 | 2000-12-05 | 전해란 | Shallow trench forming method for semiconductor isolation |
| KR20000063964A (en) * | 2000-08-12 | 2000-11-06 | 전해란 | Shallow trench forming method for semiconductor isolation |
| DE102006043389A1 (en) * | 2006-09-06 | 2008-03-27 | Technische Universität Dresden | Plasma etching process for producing positive etch profiles in silicon substrates |
| CN103280407B (en) * | 2013-06-03 | 2016-08-10 | 上海华力微电子有限公司 | The manufacture method of ∑ connected in star |
| CN103730372B (en) * | 2013-12-27 | 2016-06-08 | 西安龙腾新能源科技发展有限公司 | A kind of superjunction manufacture method improving device withstand voltage |
| KR20180077392A (en) * | 2016-12-28 | 2018-07-09 | 삼성전자주식회사 | apparatus for processing plasma and method for manufacturing semiconductor device using the same |
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