CN210866185U - Semiconductor terminal structure and semiconductor structure - Google Patents
Semiconductor terminal structure and semiconductor structure Download PDFInfo
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- CN210866185U CN210866185U CN201921806520.6U CN201921806520U CN210866185U CN 210866185 U CN210866185 U CN 210866185U CN 201921806520 U CN201921806520 U CN 201921806520U CN 210866185 U CN210866185 U CN 210866185U
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- 238000005468 ion implantation Methods 0.000 description 2
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Abstract
The utility model provides a semiconductor terminal structure and semiconductor structure relates to semiconductor technology field. The semiconductor terminal structure comprises a substrate layer and an epitaxial layer arranged on the substrate layer; the epitaxial layer is provided with a plurality of junction terminal expansion structures, the junction terminal expansion structures extend towards the substrate layer, and the extending distance of the junction terminal expansion structures decreases progressively along a preset direction. In the application, the extending distance of the plurality of junction terminal expanding structures arranged on the epitaxial layer is gradually reduced along the preset direction, the extending distance is associated with the concentration of ions, and the concentration of each obtained junction terminal expanding structure is gradually reduced, so that the junction terminal expanding structures with different concentration gradients which are gradually changed are formed, and the gradient effect of the concentration gradients is good.
Description
Technical Field
The utility model relates to the field of semiconductor technology, particularly, relate to a semiconductor terminal structure and semiconductor structure.
Background
An IGBT (insulated gate bipolar transistor) is a semiconductor power device combining a MOSFET (metal oxide field effect transistor) and a BJT (bipolar transistor), and has the characteristics of high input impedance, small switching loss, high speed, low voltage driving power, and the like. The IGBT terminal generally uses a field limiting ring technology to improve the high voltage resistance of the IGBT, and the current commonly used field limiting ring technology realizes the improvement of breakdown voltage by introducing one or more annular regions which are opposite to the doping type of a silicon substrate and have much higher concentration than the substrate into the power semiconductor terminal; however, the above method has a problem of poor concentration gradient effect.
SUMMERY OF THE UTILITY MODEL
The utility model aims to provide an effectual semiconductor terminal structure of concentration gradient gradual change and semiconductor structure.
In a first aspect, an embodiment of the present invention provides a semiconductor terminal structure, including a substrate layer and an epitaxial layer disposed on the substrate layer;
the epitaxial layer is provided with a plurality of junction terminal expansion structures, the junction terminal expansion structures extend towards the substrate layer, and the extending distance of the junction terminal expansion structures decreases progressively along a preset direction.
Further, in a preferred embodiment of the present invention, a plurality of field limiting ring structures are further formed on the epitaxial layer, the field limiting ring structures extend toward the substrate layer, and a plurality of distances that the field limiting ring structures extend decrease progressively along the predetermined direction.
Further, in a preferred embodiment of the present invention, the junction terminal expanding structure and the field limiting ring structure are sequentially arranged along the predetermined direction.
Further, in a preferred embodiment of the present invention, along the predetermined direction, the distance that the junction terminal extension structure extends is greater than the distance that the adjacent field limiting ring structure extends.
Further, in a preferred embodiment of the present invention, along the predetermined direction, the distance between the adjacent two junction terminal extension structures, the distance between the adjacent two field limiting ring structures, and the distance between the adjacent junction terminal extension structure and the field limiting ring structure are all equal.
In a second aspect, an embodiment of the present invention provides a semiconductor structure, including any one of the above semiconductor terminal structures.
The embodiment of the utility model provides a semiconductor terminal structure and semiconductor structure sets up the distance that a plurality of knot terminal extend structure on the epitaxial layer and extends and steadilys decrease along predetermineeing the direction, and the distance of extension associates with the ion concentration that has, and the concentration of each knot terminal extend structure that obtains is steadilyd decrease, consequently forms the knot terminal extend structure that the concentration gradient of difference progressively changes, and concentration gradient's gradual change is effectual.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
FIG. 1 is an initial structure for IGBT termination fabrication;
FIG. 2 is a schematic diagram of a prior art JTE structure formed by ion implantation for IGBT termination fabrication;
FIG. 3 is the final structure of the prior art after the IGBT terminals are adjusted;
fig. 4 is a schematic diagram of forming a first step in the IGBT terminal according to an embodiment of the present invention;
fig. 5 is a schematic diagram of forming a second step in the IGBT terminal according to an embodiment of the present invention;
fig. 6 is a schematic diagram of forming a third step in the IGBT terminal according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of an IGBT terminal planarization process according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of preparation of a subsequent field limiting ring of an IGBT terminal according to an embodiment of the present invention;
fig. 9 is a schematic view of an IGBT terminal structure according to an embodiment of the present invention;
FIG. 10 is a flow chart of a manufacturing method provided in the second embodiment of the present invention;
FIG. 11 is a flow chart of a manufacturing method provided in the third embodiment of the present invention;
fig. 12 is a flowchart of a manufacturing method provided in the fourth embodiment of the present invention.
Reference numerals:
1. the structure comprises a substrate layer, 2, an epitaxial layer, 3, a first oxide layer, 4, a second oxide layer, 5, a junction terminal expansion structure, 6, a field limiting ring structure, 7, a main junction, 8, a step structure, 81, a first junction terminal injection port, 82, a second junction terminal injection port, 83 and a third junction terminal injection port.
Detailed Description
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and that for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
The embodiment of the utility model provides a pair of semiconductor structure, as shown in FIG. 9, including semiconductor terminal structure and main junction 7, wherein, semiconductor terminal structure is IGBT terminal structure, and it includes: the epitaxial layer 2 is grown on the epitaxial layer 2; a plurality of junction terminal expansion structures 5 are formed on the epitaxial layer 2, the junction terminal expansion structures 5 extend towards the substrate layer 1, and the extending distance of the junction terminal expansion structures 5 decreases progressively along the preset direction. Wherein the substrate layer 1 is a silicon (Si) substrate wafer.
Wherein, the extending distance of the junction terminal extension structure 5 is the depth of the junction terminal extension structure 5 in the epitaxial layer 2; the preset direction refers to a direction from one end close to the semiconductor main junction 7 to one end far from the semiconductor main junction 7.
In this embodiment, as shown in fig. 9, a plurality of field limiting ring structures 6 are further formed on the epitaxial layer 2, the field limiting ring structures 6 extend toward the substrate layer 1, and the distance of the plurality of field limiting ring structures 6 decreases progressively along a preset direction; and the terminal extension structures 5 and the field limiting ring structures 6 are arranged in sequence along the preset direction, that is, in the preset direction, the last terminal extension structure 5 is adjacent to the first field limiting ring structure 6. The field limiting ring mechanism 6 enables the epitaxial layer on the radial outer side of the junction terminal expanding structure to have voltage resistance, and the voltage resistance of the whole semiconductor terminal structure is further improved.
As shown in fig. 9, along the preset direction, the extending distance of the junction terminal extension structure 5 is greater than the extending distance of the adjacent field limiting ring structure 6, that is, the extending distance of the last junction terminal extension structure 5 is greater than the extending distance of the first field limiting ring structure 6, so that the extending distance gradual trend of the junction terminal extension structure 5 is further extended to the field limiting ring structure 6, and then each floating field ring (i.e., each junction terminal extension structure 5 and each field limiting ring structure 6) in the terminal structure forms a whole with the gradually decreasing extending distance.
As shown in fig. 9, along the preset direction, the distance between two adjacent junction terminal expansion structures 5, the distance between two adjacent field limiting ring structures 6, and the distance between the junction terminal expansion structure 5 and the field limiting ring structure 6 are equal, that is, the distances between the floating field rings in the whole terminal structure in the preset direction are equal, and in addition, the ion concentration of each floating field ring decreases gradually along the preset direction, so the concentration gradient effect of each floating field ring is better.
The embodiment of the present invention provides a method for manufacturing a semiconductor terminal structure in the first embodiment, as shown in fig. 1, 5-6, and 10, the method includes the following steps:
and S21, growing an epitaxial layer 2 on the substrate layer 1.
S22, growing a first oxide layer 3 with a predetermined thickness on the epitaxial layer 2.
S23, etching the first oxide layer 3 to form a plurality of junction terminal injection ports distributed in a step shape along a preset direction; the step height of each junction terminal injection port is increased progressively along a preset direction; the method comprises the following specific steps:
s231, coating photoresist on one side, far away from the epitaxial layer 2, of the first oxidation layer 3;
s232, sequentially using a plurality of mask plates to expose and develop the photoresist, and etching the first oxide layer 3 and the photoresist after each exposure and development to form a plurality of junction terminal injection ports distributed in a step shape; the exposure areas of the mask plates correspond to the junction terminal injection ports one by one, or the exposure areas of the mask plates are reduced in sequence; an active region is formed.
S24, implanting ions through each junction terminal injection port to form a plurality of junction terminal extension structures 5 with decreasing concentration and distributed at intervals along the predetermined direction in the epitaxial layer 2.
Through sculpture first oxidation layer 3, can form and be a plurality of knot terminal injection mouths that step-like distribution is followed to predetermineeing the direction, because each knot terminal injection mouth is step-like distribution, the height of step-like increases in proper order for each knot terminal injection mouth is different on first oxidation layer 3, after the injected ion, the ion diffuses the degree of depth to epitaxial layer 2 from the knot terminal injection mouth of different degree of depth and reduces in proper order, consequently form the knot terminal of different concentration gradient progressive changes and extend structure 5, concentration gradient's gradual change is effectual.
The third embodiment of the present invention provides a method for manufacturing the semiconductor terminal structure, as shown in fig. 1, 5-6 and 11, including the following steps:
and S31, growing an epitaxial layer 2 on the substrate layer 1.
S32, growing a first oxide layer 3 with a predetermined thickness on the epitaxial layer 2.
S33, etching the first oxide layer 3 to form a plurality of junction terminal injection ports distributed in a step shape along a preset direction; the method comprises the following specific steps:
s331, coating photoresist on one side, far away from the epitaxial layer 2, of the first oxidation layer 3;
s332, sequentially using a first mask, a second mask and a third mask to expose and develop the photoresist, and etching the first oxide layer 3 after each exposure and development to form a first junction terminal injection port 81, a second junction terminal injection port 82 and a third junction terminal injection port 83 which are distributed in a step shape;
wherein, the exposure area of each mask corresponds to each junction terminal injection mouth one by one, for example: the exposure area of the first mask corresponds to the first junction end injection port 81, and the first junction end injection port 81 is directionally etched into a step structure 8 with the lowest height (the deepest etching depth), as shown in fig. 4; the exposure area of the third mask corresponds to the third junction terminal injection port 83, and the third junction terminal injection port 83 is directionally etched into a step structure 8 with the highest height (the etching depth is the shallowest); the exposure area of the second mask corresponds to the second junction end injection port 82, and the second junction end injection port 82 is directionally etched to have a step height between the step height of the first junction end injection port 81 and the step height of the third junction end injection port 83, as shown in fig. 5.
Or the exposure area of the first mask, the exposure area of the second mask and the exposure area of the third mask are reduced in sequence; specifically, the method comprises the following steps: the exposure area of the first reticle simultaneously corresponds to the first, second and third junction termination injection ports 81, 82, 83, i.e., the first reticle can simultaneously expose the first, second and third junction termination injection ports 81, 82, 83; the exposure area of the second reticle corresponds to both the first junction termination injection port 81 and the second junction termination injection port 82, i.e., the second reticle can expose both the first junction termination injection port 81 and the second junction termination injection port 82 simultaneously; the exposure area of the third reticle corresponds to the first junction termination injection port 81, i.e., the third reticle can expose the first junction termination injection port 81. The first junction terminal injection port 81 is etched three times, the second junction terminal injection port 82 is etched twice, the third junction terminal injection port 83 is etched once, and the etching depth can be the same each time, so that the first junction terminal injection port 81, the second junction terminal injection port 82 and the third junction terminal injection port 83 which are gradually increased in step height along the preset direction are obtained.
S34, implanting ions through each junction terminal injection port to form a plurality of junction terminal extension structures 5 with decreasing concentration and distributed at intervals along the predetermined direction in the epitaxial layer 2.
The fourth embodiment of the present invention provides a method for manufacturing the above semiconductor terminal structure, as shown in fig. 1, 5-9 and 12, including the following steps:
and S41, growing an epitaxial layer 2 on the substrate layer 1.
S42, growing a first oxide layer 3 with a predetermined thickness on the epitaxial layer 2.
S43, etching the first oxide layer 3 to form a plurality of junction-end injection ports distributed in a step-like manner along a predetermined direction, as shown in fig. 4-6.
S44, ions are implanted through the respective junction terminal injection ports to form a plurality of junction terminal extension structures 5 with decreasing concentration and distributed at intervals along a predetermined direction in the epitaxial layer 2, as shown in fig. 6.
S45, performing planarization on the remaining first oxide layer 3, as shown in fig. 7; and a second oxide layer 4 of uniform thickness is regrown on the epitaxial layer 2 as shown in fig. 8.
S46, etching the second oxide layer 4 to form a plurality of field limiting ring injection ports distributed along a predetermined direction in a step-like manner, as shown in fig. 9.
S47, implanting ions through each field limiting ring injection opening, and controlling the ion implantation dosage to form a plurality of field limiting ring structures 6 with decreasing concentration and distributed at intervals along the predetermined direction in the epitaxial layer 2, as shown in fig. 9. If more junction terminal expansion structures 5 or field limiting ring structures 6 need to be formed, more step structures 8 can be arranged according to the method, and the corresponding number of masks are used for etching for corresponding times.
Wherein, along the predetermined direction, the concentration of the junction terminal expanding structure 5 is greater than that of the adjacent field limiting ring structure 6.
The embodiment of the utility model provides a preparation method of semiconductor terminal structure, realize the concentration gradient change of lower floor p-well depth through the ladder structure of upper oxide layer and then changed electric field bending degree, increased breakdown voltage; or through the design of the step structure 8 of the oxide layer, a junction terminal expansion structure 5 with sequentially decreasing concentration of each floating field ring from the active region to the chip edge region is formed, so that the electric field is changed to improve the breakdown voltage; the method is easy to realize and the process is simple.
In the description of the present invention, it is to be understood that the terms "upper", "lower", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings. This is merely for convenience in describing the invention and to simplify the description and is not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation and is therefore not to be considered limiting of the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically limited otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," and "fixed" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (6)
1. A semiconductor termination structure, characterized by comprising a substrate layer (1) and an epitaxial layer (2) arranged on said substrate layer (1);
the epitaxial layer (2) is provided with a plurality of junction terminal expansion structures (5), the junction terminal expansion structures (5) extend towards the substrate layer (1), and the extending distance of the junction terminal expansion structures (5) decreases progressively along a preset direction.
2. The semiconductor termination structure according to claim 1, wherein a plurality of field limiting ring structures (6) are further formed on the epitaxial layer (2), the field limiting ring structures (6) extend in a direction of the substrate layer (1), and a distance of extension of the plurality of field limiting ring structures (6) decreases along the predetermined direction.
3. A semiconductor termination structure according to claim 2, wherein the junction termination extension structure (5) and the field limiting ring structure (6) are arranged in sequence along the predetermined direction.
4. A semiconductor termination structure according to claim 3, wherein the junction termination extension structure (5) extends a distance greater than the distance that an adjacent field limiting ring structure (6) extends in the predetermined direction.
5. A semiconductor termination structure according to claim 3, wherein, along the predetermined direction, the distance between two adjacent junction termination extensions (5), the distance between two adjacent field stop ring structures (6) and the distance between the adjacent junction termination extensions (5) and the field stop ring structures (6) are equal.
6. A semiconductor structure comprising the semiconductor termination structure of any of claims 1-5.
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| CN201921806520.6U CN210866185U (en) | 2019-10-24 | 2019-10-24 | Semiconductor terminal structure and semiconductor structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113053999A (en) * | 2021-03-12 | 2021-06-29 | 深圳方正微电子有限公司 | Metal oxide semiconductor transistor and preparation method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113053999A (en) * | 2021-03-12 | 2021-06-29 | 深圳方正微电子有限公司 | Metal oxide semiconductor transistor and preparation method thereof |
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