CN218101271U

CN218101271U - LDMOS device structure design with freely adjustable threshold voltage and breakdown voltage and hot carrier effect resistance

Info

Publication number: CN218101271U
Application number: CN202221535805.2U
Authority: CN
Inventors: 文海波
Original assignee: Hangzhou Hongxin Microelectronics Information Technology Co ltd
Current assignee: Hangzhou Shengjin Microelectronics Co ltd
Priority date: 2022-02-21
Filing date: 2022-02-21
Publication date: 2022-12-20
Anticipated expiration: 2032-02-21

Abstract

The utility model discloses a LDMOS device structure design with freely adjustable threshold voltage and breakdown voltage and hot carrier effect resistance, which comprises a substrate, an N-type diffusion region and a P-type diffusion region; wherein the N-type diffusion region is used as an extension region of the N + type diffusion region or an isolation region of the P + type diffusion region; wherein the P-type diffusion region is used as an extension region of the P + type diffusion region or an isolation region of the N + type diffusion region; wherein the N + type diffusion region is used as an electrode for ohmic contact; wherein the P + type diffusion region is used as an electrode for ohmic contact; the medium deposition area is a high-resistance state insulating medium formed by adopting a CVD (chemical vapor deposition) mode; the polycrystalline region is low-resistance polycrystalline silicon formed by adopting a CVD (chemical vapor deposition) mode and is used as a grid electrode of the LDMOS (laterally diffused metal oxide semiconductor) device; the structure can be completely compatible with the existing CMOS integrated circuit chip production process, and simultaneously, the threshold voltage can be freely adjusted, so that the structure better meets the flexible requirements of various applications.

Description

LDMOS device structure design with freely adjustable threshold voltage and breakdown voltage and hot carrier effect resistance

Technical Field

The utility model belongs to the integrated circuit territory design and semiconductor manufacturing category, the design of the LDMOS territory and the preparation method of different performance of specially adapted general BCD technology processing preparation.

Background

In the design of the LDMOS, the threshold voltage and the source-drain breakdown voltage of the device belong to the core of the design and manufacture of the device. At present, threshold voltages of LDMOS devices provided for designers by different wafer manufacturers are fixed values, and source-drain breakdown voltages of the LDMOS devices provided for the designers are step data from low to high. According to the application environment of the product, designers need to introduce different source-drain breakdown voltages and threshold voltages of the LDMOS devices in the design process. Therefore, it is necessary to design an LDMOS device with a freely linearly adjustable threshold voltage and a source-drain breakdown voltage similar to that of the linearly adjustable LDMOS device to meet different operating requirements.

SUMMERY OF THE UTILITY MODEL

Therefore, in order to solve the above-mentioned insufficiency, the utility model provides a threshold voltage and breakdown voltage freely adjustable, anti hot carrier effect's LDMOS device structure's design method here. Specifically, the method comprises the following steps:

the N-type diffusion region is prepared by doping phosphorus, arsenic or antimony by using a substrate as a base through an ion implantation or diffusion technology, wherein the concentration of the N-type diffusion region is N-, and the specific concentration range is 1E14-1E15cm-3; the N-type diffusion region is used as an active region layer for improving source-drain breakdown voltage of the LDMOS device, the thickness of a depletion layer between the P-type diffusion region and the N-diffusion region in the region is directly determined by the concentration, and different distances can be set on the premise that the N-diffusion region and the P-diffusion region are located under a polycrystalline region and a second medium deposition region in the Y direction according to different source-drain breakdown voltage requirements when the N-type diffusion region is used as the N-diffusion region to the P-diffusion region of the N-type LDMOS device; the P-diffusion region and the N-diffusion region used in the P-type LDMOS period can be set with different pitches according to different source-drain breakdown voltage requirements on the premise of ensuring that the N-diffusion region and the P-diffusion region are positioned below the polycrystalline region and the second dielectric deposition region.

When the N-type LDMOS device is used as an N-diffusion region, the depth of the N-diffusion region extending into the polycrystalline region and the depth of the second medium deposition region are selected to be different in the X direction according to different threshold voltage requirements; similarly, when the polycrystalline silicon region is used as a P-diffusion region of a P-type LDMOS device, the polycrystalline silicon region and the second dielectric deposition region are extended to cover different depths in the X direction according to different threshold voltages.

The second dielectric layer is used as a grid dielectric layer of the LDMOS, and different thicknesses can be selected according to the voltage withstanding requirements of a grid polycrystalline region and a source region; formed by CVD deposition, but not limited to; preferably, the dielectric layer can be formed simultaneously with the first dielectric deposition region and is formed by selectively etching different thicknesses according to different device withstand voltages; the first medium deposition area is made of a SiO2 material, but not limited to, preferably, a silicon oxynitride material can be selected; the voltage resistance of the device is ensured, meanwhile, the parasitic capacitance of the grid electrode can be reduced, and the characteristic frequency of the device is improved.

The utility model has the advantages of as follows: the invention provides a portable water conservancy pipeline cutting device through improvement, compared with the same type of device, the portable water conservancy pipeline cutting device has the following improvement:

the advantages are that: the utility model relates to a threshold voltage and breakdown voltage freely adjustable, anti hot carrier effect's LDMOS device structural design, wherein N-type diffusion zone is as the extension zone of N + type diffusion zone or the isolation zone of P + type diffusion zone; wherein the P-type diffusion region is used as an extension region of the P + type diffusion region or an isolation region of the N + type diffusion region; wherein the N + type diffusion region is used as an electrode for ohmic contact; wherein the P + type diffusion region is used as an electrode for ohmic contact; the medium deposition area is a high-resistance state insulating medium formed by adopting a CVD (chemical vapor deposition) deposition mode; the polycrystalline region is low-resistance polycrystalline silicon formed by adopting a CVD (chemical vapor deposition) mode and is used as a grid electrode of the LDMOS device; the structure can be completely compatible with the existing CMOS integrated circuit chip production process, and simultaneously, the threshold voltage can be freely adjusted, so that the structure better meets the flexible requirements of various applications

Drawings

FIG. 1: do the utility model discloses the device longitudinal structure sketch map.

FIG. 2: do the utility model discloses the vertical structure implementation drawing of device structure.

Detailed Description

The present invention will be described in detail with reference to the accompanying drawings 1-2, wherein the technical solutions in the embodiments of the present invention are clearly and completely described, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

Now, taking the N-type LDMOS as an example, in combination with the drawings, the following detailed description is given to the manufacturing process of the main processes of the present invention:

fig. 1 is a schematic structural diagram of the LDMOS device of the present invention.

As shown in fig. 2, the N-type LDMOS implemented in the present invention uses a substrate as a base, and an N-type diffusion region (3) formed by doping phosphorus, arsenic or antimony through ion implantation or diffusion technology as a drift region of the N-type LDMOS. A substrate is used as a substrate, a P-diffusion region (2) formed by doping boron through an ion implantation or diffusion technology is used as an isolation well of the N-type LDMOS and is combined with the N-type diffusion region to improve the source-drain breakdown voltage of the N-type LDMOS; the dielectric layer is formed by a CVD (chemical vapor deposition) deposition mode, preferably, an initial thermal oxidation mode is adopted, unnecessary parts are etched by a dry method or a wet method step by step according to photoetching patterns of different levels of subsequent processes, and the remained parts are the first dielectric deposition area (4) which is used as a protective layer for resisting electric power concentrated impact of hot carriers on one side edge of the grid electrode close to the drain electrode; the second dielectric deposition region (5) is formed by a CVD deposition mode, preferably, the second dielectric deposition region and the first dielectric deposition region (4) can be formed at the same time, and different thicknesses are selectively etched according to different device withstand voltages and threshold voltages to form the second dielectric deposition region which is used as a grid dielectric layer of the N-type LDMOS; forming a gate poly region (6) by selectively etching away unnecessary portions without limitation to a CVD deposition method; it is to be understood that: the length of the grid polycrystalline region (6) from the side close to the source electrode to the side close to the drain electrode is not selected as the channel length of the N-type LDMOS; an N + diffusion region (7) is formed by implanting arsenic impurities without limitation, and is used as a source-drain ohmic contact leading-out layer of the N-type LDMOS; forming a P + diffusion region (8) by implanting boron impurities without limitation, serving as an ohmic contact leading-out layer of the fourth terminal BULK of the N-type LDMOS, and being connected with the source electrode through a first metal layer (9); second metal layer (R) is formed by magnetron sputtering, and is used as the extraction layer of all electrodes and as the electrical connection between different devices.

The specific implementation steps are as follows:

step 1: coating photoresist on the wafer by using an N-diffusion area photoetching plate, and exposing and developing to obtain an N-diffusion area;

step 2: injecting phosphorus impurities in a glue injection mode, wherein the energy is 10-100Kev, and the dose is 1-10e14/cm & lt-2 >

and step 3: coating photoresist on the wafer by using a P-diffusion area photoetching plate, and exposing and developing to form a P-diffusion area;

and 4, step 4: injecting boron impurities in a glue injection mode, wherein the energy is 10-100Kev, and the dose is 1-10e14/cm & lt-2 >

and 5: forming a silicon dioxide film by adopting a thermal oxidation mode, preferably, selectively carrying out regional chlorine-based RIE etching on a shallow groove at a required position, forming the silicon dioxide film by adopting the thermal oxidation mode, cleaning off part of silicon dioxide, and reserving the silicon dioxide film with the required thickness of 100-1000 angstroms;

and 6: forming a polysilicon film by deposition, wherein the film thickness is 1000-5000 angstroms; coating glue and exposing by using a polycrystalline photoetching plate, developing to remove polycrystalline patterns, and etching to prepare a grid polycrystalline region;

and 7: coating glue on an N + diffusion region photoetching plate, exposing and developing to form an N + diffusion region pattern, and forming the N + diffusion region in an ion implantation mode, wherein the ion implantation material can be but is not limited to arsenic, phosphorus and antimony impurities, preferably, arsenic is implanted by ions, the energy is 10-50Kev, and the dose is 1-10e16/cm < -2 >;

and 8: gluing a P + diffusion region photoetching plate, exposing and developing a P + diffusion region pattern, and forming a P + diffusion region in an ion implantation mode, wherein the ion implantation material can be but is not limited to impurities such as boron, aluminum, gallium, indium and the like, preferably, boron is implanted by ions, the energy is 10-50Kev, and the dosage is 1-10e16/cm & lt-2 >

and step 9: and depositing metal Al in a magnetron sputtering mode to form an electrode lead-out and electrical connection between devices.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. The utility model provides a threshold voltage and breakdown voltage freely adjustable, resistant hot carrier effect's LDMOS device structure design which characterized in that: the substrate comprises a substrate (1), an N-type diffusion region (2 when the substrate is of a P type, and (3) when the substrate is of an N type), a P-type diffusion region (3 when the substrate is of a P type, and (2) when the substrate is of an N type), an N + type diffusion region (7 when the substrate is of a P type, and (8) when the substrate is of an N type), a P + type diffusion region (8 when the substrate is of a P type, and (7) when the substrate is of an N type), a first dielectric deposition region (4), a second dielectric deposition region (5), a polycrystalline region (6), a first metal layer (9), and a second metal layer (R);

the substrate (1) is an implanted or diffused substrate of the N-type diffusion region (when being NMOS (3) or when being PMOS (2)), and can be an original N-type substrate doped with phosphorus, arsenic or antimony, or an N-type well layer doped with phosphorus, arsenic or antimony on a P-type substrate wafer by an implantation or doping mode; the substrate can also be an original P-type substrate doped with boron, or a P-type well layer doped with boron on an N-type substrate wafer in an injection or doping mode;

the N-type diffusion region (when being NMOS (3) or when being PMOS (2)) is made by doping phosphorus, arsenic or antimony by using an ion implantation or diffusion technology on the basis of a substrate (1); the N-type diffusion region is used as an active region layer for improving the source-drain breakdown voltage of the LDMOS device, and the thickness of a depletion layer between the P + type diffusion region or the P-type diffusion region ((3) or (2)) in the region and the substrate (1) is directly determined by the concentration; the P-type diffusion region (2 in the case of NMOS or 3 in the case of PMOS) is made by doping boron by ion implantation or diffusion technique with the substrate 1 as a base; the P + type diffusion region or the P-type diffusion region is used as a buffer layer for improving the source-drain breakdown voltage of the LDMOS device, and the thickness of a depletion layer between the P-type diffusion region ((2) or (3)) and the substrate (1) in the region is directly determined by the concentration; the N + type diffusion region (7) is used as a source and drain ohmic contact layer when being an NMOS device, or (8) is used as a Bulk end ohmic contact layer when being a PMOS device; the P + type diffusion region (7) is used as a source and drain ohmic contact layer when being a PMOS device, or (8) is used as a Bulk end ohmic contact layer when being an NMOS device;

the first dielectric deposition region (4) is used as a protective layer of a device, and the second dielectric deposition region (5) is used as a gate dielectric layer of the LDMOS; the polycrystalline region (6) is used as a grid electrode of the LDMOS.

2. The LDMOS device structure design of claim 1 for resisting hot carrier effect with freely adjustable threshold voltage and breakdown voltage, comprising: the structure is suitable for N-type LDMOS devices under all silicon or germanium-silicon process platforms, or P-type LDMOS devices under all silicon or germanium-silicon process platforms.

3. The LDMOS device structure design of claim 1, with freely adjustable threshold voltage and breakdown voltage and capable of resisting hot carrier effect, wherein: doping all diffusion regions with impurities such as boron, phosphorus, arsenic, antimony, etc., including but not limited to the above types by ion implantation or diffusion; the N-type diffusion area is made by doping As impurities in an ion implantation mode, the N + type diffusion area is made by doping phosphorus impurities in an ion implantation mode, the P-type diffusion area is made by doping boron impurities in an ion implantation mode, and the P + type diffusion area is made by doping boron impurities in an ion implantation mode.

4. The LDMOS device structure design of claim 1 for resisting hot carrier effect with freely adjustable threshold voltage and breakdown voltage, comprising: when the N-type LDMOS device is used, the distance between the N-diffusion region (3) and the P-diffusion region (2) can be set to be different according to different source-drain breakdown voltage requirements on the premise that the N-diffusion region (3) and the P-diffusion region (2) are located below the polycrystalline region (6) and the second dielectric deposition region (5); when the P-type LDMOS device is used, the distance between the P-diffusion region (3) and the N-diffusion region (2) can be set to be different according to different source-drain breakdown voltage requirements on the premise that the N-diffusion region (3) and the P-diffusion region (2) are located below the polycrystalline region (6) and the second dielectric deposition region (5).

5. The LDMOS device structure design of claim 1, with freely adjustable threshold voltage and breakdown voltage and capable of resisting hot carrier effect, wherein: when the N-type LDMOS device is used as an N-diffusion region (3), the N-diffusion region and a second medium deposition region (5) are selected to cover different lengths in the X direction according to different threshold voltages; similarly, the P-diffusion region (2) used as a P-type LDMOS device is selected to extend into the polycrystalline region (6) and cover different lengths of the second dielectric deposition region (5) in the X direction according to different threshold voltages.

6. The LDMOS device structure design of claim 1, with freely adjustable threshold voltage and breakdown voltage and capable of resisting hot carrier effect, wherein: when the polycrystalline silicon region is used as a P-diffusion region (3) of a P-type LDMOS device, the polycrystalline silicon region (6) and the second medium deposition region (5) are selected to cover different lengths in the X direction according to different threshold voltages; similarly, the N-diffusion region (2) used as a P-type LDMOS device is selected to penetrate into the polycrystalline region (6) and cover different lengths with the second medium deposition region (5) in the X direction according to different threshold voltages.

7. The LDMOS device structure design of claim 1, with freely adjustable threshold voltage and breakdown voltage and capable of resisting hot carrier effect, wherein: the first medium deposition region (4) is used as a protective layer and is used for resisting electric power concentrated impact of hot carriers at the edge of one side, close to the drain electrode, of the grid electrode; the dielectric layer is formed in a mode not limited to CVD deposition, an initial thermal oxidation mode is adopted, unnecessary parts are gradually etched away in a dry method or a wet method according to photoetching plate patterns of different levels in subsequent processes, and the remaining parts are the first dielectric deposition regions (4).

8. The LDMOS device structure design of claim 1, with freely adjustable threshold voltage and breakdown voltage and capable of resisting hot carrier effect, wherein: the second dielectric deposition region (5) is used as a gate dielectric layer of the LDMOS, and different thicknesses can be selected for ensuring the withstand voltage of the gate polycrystalline region (6) and the source region; formed by means not limited to CVD deposition; can be formed simultaneously with the first medium deposition area (4) and is made by selectively etching different thicknesses according to different device withstand voltages; the first dielectric deposition region (4) is made of silicon oxynitride material.