CN100594600C - Complementary metal-oxide-semiconductor transistor and manufacturing method thereof - Google Patents
Complementary metal-oxide-semiconductor transistor and manufacturing method thereof Download PDFInfo
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- CN100594600C CN100594600C CN200710005947A CN200710005947A CN100594600C CN 100594600 C CN100594600 C CN 100594600C CN 200710005947 A CN200710005947 A CN 200710005947A CN 200710005947 A CN200710005947 A CN 200710005947A CN 100594600 C CN100594600 C CN 100594600C
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Abstract
The invention provides a complementary metal oxide semiconductor transistor and the manufacturing method thereof. By arranging deep pocket doping region on a semiconductor substrate, locking phenomenon is avoided. In addition, since the manufacture of the deep pocket doping region is integrated into lightly doped drain process or source/drain doping region process, additional mask cost is not needed, so that locking prevention ability is effectively improved.
Description
Technical field
The present invention refers to a kind of CMOS transistor with the anti-system ability (latch-up robustness) of good locking and preparation method thereof especially about a kind of CMOS transistor and preparation method thereof.
Background technology
The basic element of semiconductor that CMOS (Complementary Metal Oxide Semiconductor) (CMOS) transistor is made up of a N type metal oxide semiconductor (NMOS) P-type mos of transistor AND gate (PMOS) transistor.
Please refer to Fig. 1, Fig. 1 is the structural representation of existing CMOS transistor.As shown in Figure 1, existing CMOS transistor includes the semiconductor-based end 10 of a P type, and by can distinguishing P-type mos element region 20 and N type metal oxide semiconductor element region 40 in the semiconductor-based end 10 of looking up direction, and utilize isolation structure 12 to be isolated.Be provided with N type trap 22 in the P-type mos element region 20 and be arranged in the semiconductor-based end 10, gate insulator 24 and be positioned at the both sides that the surface at the semiconductor-based end 10, the surface that gate electrode 26 is positioned at gate insulator 24, two spaced walls 28 are positioned at gate electrode 26, and the source electrode 30 of two P types lays respectively at at the semiconductor-based end 10 of two spaced walls 28 both sides.In addition, be respectively arranged with one lightly doped drain 32 in addition at the semiconductor-based end 10 of spaced walls 28 belows of gate electrode 26 both sides, then be provided with pouch-type (halo orpocket) doped region 34 at the semiconductor-based end 10 of each lightly doped drain 32 below.
On the other hand, be provided with P type trap 42 in the N type metal oxide semiconductor element region 40 and be arranged in the semiconductor-based end 10, gate insulator 44 and be positioned at the both sides that the surface at the semiconductor-based end 10, the surface that gate electrode 46 is positioned at gate insulator 44, two spaced walls 48 are positioned at gate electrode 46, and the source electrode 50 of two N types lays respectively at at the semiconductor-based end 10 of two spaced walls 48 both sides.In addition, be respectively arranged with lightly doped drain 52 in addition at the semiconductor-based end 10 of spaced walls 48 belows of gate electrode 46 both sides.
Be extensive use of CMOS transistor at present in the integrated circuit as main basic electronic component, but under the situation about constantly progressing greatly of technology live width, the isolation to each other of P-type mos transistor AND gate N type metal oxide semiconductor transistor more seems important, otherwise latch-up phenomenon takes place easily.In addition, for some possesses high electric current or high-tension integrated circuit, for example analog circuit (analogue IC) or electric power management circuit (PMIC), CMOS transistor is easy to generate latch-up phenomenon especially.
Please continue with reference to figure 2 and Fig. 3, and in the lump with reference to figure 1.Fig. 2 is the schematic diagram of pnpn diode, and Fig. 3 is that the electric current of pnpn diode of Fig. 2 is to the pass figure of voltage.As shown in Figure 1, CMOS transistor connects in the mode of inverter (inverter), with the test latch-up phenomenon.In P-type mos element region 20, the source/drain 30 of P type, N type trap 22 can form vertical type pnp bipolar transistor with the semiconductor-based end 10 of P type, and on the other hand in the N type metal oxide semiconductor element region 40, the source/drain 50 of N type and P type trap 42 can form transverse type npn bipolar transistor with 22 of the N type traps of P-type mos element region 20.Because the base stage (base) of vertical type pnp bipolar transistor is joined with the collector electrode (collector) of transverse type npn bipolar transistor, the collector electrode of vertical type pnp bipolar transistor also joins with the base stage of transverse type npn bipolar transistor simultaneously, the base stage of arbitrary bipolar transistor all is in the state that is driven (driven) by the collector electrode of another bipolar transistor under this situation, thereby makes vertical type pnp bipolar transistor and transverse type npn bipolar transistor form positive feedback loop (positive feedback loop).
Above-mentioned positive feedback loop can be considered parasitic pnpn diode, and as shown in Figure 2, and the operating curve of electric current of pnpn diode (I) and voltage (V) as shown in Figure 3.The initiation electric current of pnpn diode (triggering currcnt) is I
H, when electric current greater than causing electric current (I＞I
H) time, the pnpn diode can be in the state of running, and makes CMOS transistor produce latch-up phenomenon.In case generation latch-up phenomenon, to make the temporary even permanent loss function of CMOS transistor, and influence the normal operation of CMOS transistor, therefore in the design and fabrication process of CMOS transistor, how to avoid the important topic in the research and development of becoming of latch-up phenomenon.
Summary of the invention
One object of the present invention is to provide a kind of method of making CMOS transistor, with the anti-system ability of the locking that promotes CMOS transistor.
Another object of the present invention is to provide a kind of CMOS transistor with the anti-system ability of good locking.
For reaching above-mentioned purpose, one embodiment of the invention provide a kind of method of making CMOS transistor.The semiconductor-based end, at first be provided, it includes the first conductivity type metal oxide semiconductor device district and the second conductivity type metal oxide semiconductor device district, and this semiconductor-based end, include the second conductivity type dopant well in this first conductivity type metal oxide semiconductor device district, and include the first conductivity type dopant well in this second conductivity type metal oxide semiconductor device district.Then form a plurality of isolation structures, and form grid structure in this first conductivity type metal oxide semiconductor device district in the surface at this semiconductor-based end.Afterwards, form first mask pattern in the surface at this semiconductor-based end, wherein this first mask pattern exposes this grid structure in this first conductivity type metal oxide semiconductor device district and the semiconductor-based end of these grid structure both sides.Subsequently, utilize this first mask pattern, flow into by ion in this second conductivity type dopant well of these grid structure both sides in this first conductivity type metal oxide semiconductor device district and form two lightly doped drains as mask.Utilize this first mask pattern as mask once more, flow into by ion in this second conductivity type dopant well of these grid structure both sides in this first conductivity type metal oxide semiconductor device district and form two dark pouch-type doped regions, wherein these two dark pouch-type doped regions are second conductivity type.Afterwards, remove this first mask pattern, and form spaced walls in the sidewall of this grid structure in this grid structure in this first conductivity type metal oxide semiconductor device district and this second conductivity type metal oxide semiconductor device district.Form second mask pattern in the surface at this semiconductor-based end then, wherein this second mask pattern exposes this semiconductor-based end of these spaced walls both sides of this grid structure in this first conductivity type metal oxide semiconductor device district and this grid structure.Then utilize this second mask pattern as mask, flow into by ion in this second conductivity type dopant well of these grid structure both sides in this first conductivity type metal oxide semiconductor device district and form two source electrode.Remove this second mask pattern subsequently.
The present invention makes mask pattern that the method utilization of CMOS transistor makes lightly doped drain as mask, produces dark pouch-type doped region in the lump, not only can promote the anti-system ability of locking, can not increase extra mask cost simultaneously again.
In order to make those of ordinary skills a nearlyer step understand feature of the present invention and technology contents, see also following about detailed description of the present invention and accompanying drawing.Yet appended graphic only for reference and aid illustration usefulness is not to be used for the present invention is limited.
Description of drawings
Fig. 1 is the structural representation of existing CMOS transistor.
Fig. 2 is the schematic diagram of pnpn diode.
Fig. 3 is that the electric current of pnpn diode of Fig. 2 is to the pass figure of voltage.
Fig. 4 is the method flow diagram that first preferred embodiment of the present invention is made CMOS transistor.
Fig. 5 to Figure 11 makes the method schematic diagram of CMOS transistor for the first embodiment of the present invention.
Figure 12 is the method flow diagram that second preferred embodiment of the present invention is made CMOS transistor.
Figure 13 to Figure 19 makes the method schematic diagram of CMOS transistor for the second embodiment of the present invention.
[main element symbol description]
10 isolation structures of the semiconductor-based ends 12
20P type metal oxide semiconductor element region 22N type trap
24 gate insulators, 26 gate electrodes
28 spaced walls, 30 source electrode
32 lightly doped drains, 34 pouch-type doped regions
40N type metal oxide semiconductor element region 42P type trap
44 gate insulators, 46 gate electrodes
48 spaced walls, 50 source electrode
The 70 semiconductor-based ends of 52 lightly doped drains
72P type metal oxide semiconductor element region 74N type metal oxide semiconductor element region
76N type dopant well 78P type dopant well
80 isolation structures, 82 gate insulators
84 gate insulators, 86 gate electrodes
88 gate electrodes, 89 mask patterns
90 lightly doped drains, 92 spaced walls
93 mask patterns, 94 source electrode
96N type doped region 98 first mask patterns
100 lightly doped drains, 102 pouch-type doped regions
104 dark pouch-type doped region 106 source electrode
108P type doped region 118 second mask patterns
120 semiconductor-based end 122P type metal oxide semiconductor element regions
124N type metal oxide semiconductor element region 126N type dopant well
128P type dopant well 130 isolation structures
132 gate insulators, 134 gate insulators
136 gate electrodes, 138 gate electrodes
140 2 lightly doped drains of 139 mask patterns
142 spaced walls, 143 mask patterns
144 source electrode 146N type doped regions
148 first mask patterns, 150 lightly doped drains
152 pouch-type doped regions, 154 dark pouch-type doped regions
156 source electrode 158P type doped regions
160 second mask patterns
Embodiment
Please refer to Fig. 4, Fig. 4 is the method flow diagram that first preferred embodiment of the present invention is made CMOS transistor.As shown in Figure 4, the main process step of present embodiment making CMOS transistor includes:
Step 60: the semiconductor-based end is provided;
Step 61: form dopant well;
Step 62: form isolation structure;
Step 63: make grid structure;
Step 64: make lightly doped drain, pouch-type doped region and dark pocket doped region;
Step 65: make spaced walls; And
Step 66: make source/drain.
Please continue with reference to figure 5 to Figure 11, Fig. 5 to Figure 11 is the method schematic diagram that the first embodiment of the present invention is made CMOS transistor.In present embodiment, first conductivity type is the P type, and second conductivity type is the N type, but is not limited to this, and in other execution mode, first conductivity type also can be the N type, and second conductivity type then is the P type.As shown in Figure 5, the semiconductor-based end 70 of P type, at first be provided, include P-type mos element region 72 by the semiconductor-based end 70 of looking up direction, in order to make the P-type mos transistor, and N type metal oxide semiconductor element region 74, in order to make N type metal oxide semiconductor transistor.Then in the semiconductor-based end 70 of P-type mos element region 72, be formed with N type dopant well 76, and in the semiconductor-based end 70 of N type metal oxide semiconductor element region 74, form P type dopant well 78.Subsequently, form a plurality of isolation structures 80, for example field oxide or shallow trench isolation structure in the surface at the semiconductor-based end 70.
As shown in Figure 6, then form dielectric layer such as silicon oxide layer in regular turn in the surface at the semiconductor-based end 70, and conductive layer such as polysilicon layer, and utilize photoetching and etching technique, and on the semiconductor-based end 70 of N type metal oxide semiconductor element region 74, form gate insulator 84 and gate electrode 88 respectively at formation gate insulator 82 and gate electrode 86 at the semiconductor-based end 70 of P-type mos element region 72.
As shown in Figure 7, then utilize mask pattern 89 to cover the surface of P-type mos element region 72 and the surface of part N type metal oxide semiconductor element region 74, and in the semiconductor-based end 70 of gate electrode 88 both sides of N type metal oxide semiconductor element region 74, form two lightly doped drains 90 by ion implantation technology, remove mask pattern 89 again.
As shown in Figure 8, form first mask pattern 98 subsequently in the surface at the semiconductor-based end 70, photoresist pattern for example, first mask pattern 98 covers N type metal oxide semiconductor element region 74 and part P-type mos element region 72, and exposes at the gate electrode 86 of P-type mos element region 72 and the semiconductor-based end 70 of gate electrode 86 both sides.Subsequently, utilize first mask pattern 98 as mask, flow into the lightly doped drain 100 that forms two slight P types (P-) in the N type dopant well 76 of grid structure both sides of P-type mos element region 72 by ion, and the pouch-type doped region 102 of two slight N types (N-).Utilize same first mask pattern to do 98 and be mask, flow into dark pouch-type (deep halo) doped region 104 that forms two severe N types (N+) in the N type dopant well 76 of gate electrode 86 both sides of P-type mos element region 72 by ion.
Lightly doped drain 100, pouch-type doped region 102 utilize the first identical mask pattern 98 as mask with dark pouch-type doped region 104, and utilize different ion implantation technologies to be formed in the N type dopant well 76 respectively, follow again once or for several times annealing process to drive in admixture.What deserves to be explained is that the sequencing that carries out in order to the ion implantation technology that forms lightly doped drain 100, pouch-type doped region 102 and dark pouch-type doped region 104 is not limited by the above-mentioned explanation of present embodiment and can the situation of fitting be changed, and wherein dark pouch-type doped region 104 utilizes high energy high dose ion injection technology to be formed, and is located at pouch-type doped region 102 and also corresponding pouch-type doped region 102 in the below of lightly doped drain 100 and lightly doped drain 100.In the present embodiment, the ion implantation energy of high energy high dose ion injection technology is approximately between 150 to 180kev, and ion implantation concentration is approximately between 1013 to 1014 atoms/cm3, but is not limited to this.The existence of dark pouch-type doped region 104 can increase the base width (base width) of the vertical type pnp bipolar transistor that is arranged in P-type mos element region 72, and reduce its beta gain (beta gain), therefore can avoid the generation of latch-up phenomenon.
As shown in Figure 9, remove first mask pattern 98 subsequently, and form spaced walls 92 in the two side of the gate electrode 86 of P-type mos element region 72 and the gate electrode 88 of N type metal oxide semiconductor element region 74.Then utilize the surface of mask pattern 93 shaded portions P-type mos element regions 72 and the surface of part N type metal oxide semiconductor element region 74, and in the semiconductor-based end 70 of spaced walls 92 both sides of N type metal oxide semiconductor element region 74, form two source electrode 94, and in the semiconductor-based end 70 of P-type mos element region 72, form simultaneously and be used for the N type doped region 96 that is electrically connected with N type dopant well 76 by ion implantation technology.Remove mask pattern 93 subsequently.
As shown in figure 10, form second mask pattern 118 again in the surface at the semiconductor-based end 70 subsequently, the surface of second mask pattern, 118 shaded portions P-type mos element regions 72 and the surface of part N type metal oxide semiconductor element region 74, and be that mask forms two source electrode 106 with ion implantation technology in the semiconductor-based end 70 of spaced walls 92 both sides of P-type mos element region 78 by second mask pattern 118, while formation in the semiconductor-based end 70 of N type metal oxide semiconductor element region 74 is used for the P type doped region 108 that is electrically connected with P type dopant well 78.As shown in figure 11, remove second mask pattern 118 at last, promptly produce CMOS transistor with dark pouch-type doped region 104.
From the above, it is produced that the dark pouch-type doped region 104 of present embodiment and pouch-type doped region 102 and lightly doped drain 100 carry out ion implantation technology respectively by same first mask pattern 98, and therefore not needing to increase separately additional masks can reach the effect of avoiding latch-up phenomenon.
Please refer to Figure 12, Figure 12 is the method flow diagram that second preferred embodiment of the present invention is made CMOS transistor.As shown in figure 12, the main process step of present embodiment making CMOS transistor includes:
Step 110: the semiconductor-based end is provided;
Step 111: form dopant well;
Step 112: form isolation structure;
Step 113: make grid structure;
Step 114: make lightly doped drain and pouch-type doped region;
Step 115: make spaced walls; And
Step 116: make source/drain and dark pocket doped region.
Please continue with reference to figures 13 to Figure 19, Figure 13 to Figure 19 makes the method schematic diagram of CMOS transistor for the second embodiment of the present invention.In present embodiment, first conductivity type is the P type, and second conductivity type is the N type, but method of the present invention and application are not limited to this, and in other execution mode, first conductivity type also can be the N type, and second conductivity type then is the P type.As shown in figure 13, the semiconductor-based end 120 of P type, at first be provided, include P-type mos element region 122 by looking up the semiconductor-based end 120 that direction sees, in order to make the P-type mos transistor, and N type metal oxide semiconductor element region 124, in order to make N type metal oxide semiconductor transistor.Then in the semiconductor-based end 120 of P-type mos element region 122, be formed with N type dopant well 126, and in the semiconductor-based end 120 of N type metal oxide semiconductor element region 124, form P type dopant well 128.Subsequently, form a plurality of isolation structures 130, for example field oxide or shallow trench isolation structure in the surface at the semiconductor-based end 120.
As shown in figure 14, then form dielectric layer such as silicon oxide layer in regular turn in the surface at the semiconductor-based end 120, and conductive layer such as polysilicon layer, and utilize photoetching and etching technique, and on the semiconductor-based end 120 of N type metal oxide semiconductor element region 124, form gate insulator 134 and gate electrode 138 respectively at formation gate insulator 132 and gate electrode 136 at the semiconductor-based end 120 of P-type mos element region 122.
As shown in figure 15, then utilize mask pattern 139 to cover the surface of N type metal oxide semiconductor element region 124 and the surface of part P-type mos element region 122, and in the semiconductor-based end 120 of gate electrode 138 both sides of N type metal oxide semiconductor element region 124, form two lightly doped drains 140 by ion implantation technology, remove mask pattern 139 again.
As shown in figure 16, form first mask pattern 148 subsequently in the surface at the semiconductor-based end 120, photoresist pattern for example, first mask pattern 148 covers N type metal oxide semiconductor element region 124 and part P-type mos element region 122, and exposes at the grid structure of P-type mos element region 122 and the semiconductor-based end 120 of grid structure both sides.Subsequently, utilize first mask pattern 148 as mask, flow into the lightly doped drain 150 that forms two slight P types (P-) in the N type dopant well 126 of grid structure both sides of P-type mos element region 122 by ion, and the pouch-type doped region 152 of two slight N types (N-).
As shown in figure 17, remove first mask pattern 148 subsequently, form spaced walls 142 in the two side of the gate electrode 136 of P-type mos element region 122 and the gate electrode 138 of N type metal oxide semiconductor element region 124 again.Then utilize the surface of mask pattern 143 shaded portions P-type mos element regions 122 and the surface of part N type metal oxide semiconductor element region 124, and in the semiconductor-based end 120 of spaced walls 142 both sides of N type metal oxide semiconductor element region 124, form two source electrode 144, and in the semiconductor-based end 120 of P-type mos element region 122, form simultaneously and be used for the N type doped region 146 that is electrically connected with N type dopant well 126 by ion implantation technology.Remove mask pattern 143 subsequently.
As shown in figure 18, form second mask pattern 160 again in the surface at the semiconductor-based end 120 subsequently, the surface of second mask pattern, 160 shaded portions P-type mos element regions 122 and the surface of part N type metal oxide semiconductor element region 124, and be that mask forms two source electrode 156 with ion implantation technology in the semiconductor-based end 120 of spaced walls 142 both sides of P-type mos element region 128 by second mask pattern 160, and formation is used for the P type doped region 158 that is electrically connected with P type dopant well 128 in the semiconductor-based end 120 of N type metal oxide semiconductor element region 124.Pass through second mask pattern 160 simultaneously once more as mask, and in the N type dopant well 126 of the grid structure both sides of P-type mos element region 122, form dark pouch-type (deep halo) doped region 154 of two severe N types (N+) with ion implantation technology.
Dark pouch-type doped region 154 in the N type dopant well 126 utilizes the second identical mask pattern 160 as mask with source electrode 156, and utilizes different ion implantation technologies to be formed in the N type dopant well 126 respectively.What deserves to be explained is that the sequencing that carries out in order to the ion implantation technology that forms source electrode 156 and dark pouch-type doped region 154 is not limited by the above-mentioned explanation of present embodiment and can the situation of fitting be changed, and wherein dark pouch-type doped region 154 utilizes high energy high dose ion injection technology to be formed, and is located at the below and the corresponding source electrode 156 of source electrode 156.In the present embodiment, the ion implantation energy of high energy high dose ion injection technology is approximately between 150 to 180kev, and ion implantation concentration is approximately between 10
13To 10
14Atom/cm
3Between, but be not limited to this.The existence of dark pouch-type doped region 154 can increase the base width of the vertical type pnp bipolar transistor that is positioned at P-type mos element region 122, and reduces its beta gain (beta gain), therefore can avoid the generation of latch-up phenomenon.
At last as shown in figure 19, remove second mask pattern 160 at last, promptly produce CMOS transistor with dark pouch-type doped region 154.
From the above, it is produced that the dark pouch-type doped region 154 of present embodiment and source electrode 156 are carried out ion implantation technology respectively by same second mask pattern 160, and therefore not needing to increase separately additional masks can reach the effect of avoiding latch-up phenomenon.
In sum, CMOS transistor of the present invention increases the base width of vertical type pnp bipolar transistor by dark pocket doped region is set, and then reduce its beta gain, therefore can avoid the generation of latch-up phenomenon, and the making of dark pocket doped region is integrated in lightly doped drain technology or the source electrode technology, therefore the additional masks cost need be do not increased, the anti-system ability of locking can be effectively promoted.
The above only is the preferred embodiments of the present invention, and all equivalent variations and modifications of doing according to claim all should belong to covering scope of the present invention.
Claims (16)
1. method of making CMOS transistor includes:
The semiconductor-based end, be provided, include the first conductivity type metal oxide semiconductor device district and the second conductivity type metal oxide semiconductor device district, this semiconductor-based end, include the second conductivity type dopant well in this first conductivity type metal oxide semiconductor device district, and include the first conductivity type dopant well in this second conductivity type metal oxide semiconductor device district;
Form a plurality of isolation structures in the surface at this semiconductor-based end;
Form grid structure in this first conductivity type metal oxide semiconductor device district;
Form first mask pattern in the surface at this semiconductor-based end, this first mask pattern exposes this grid structure in this first conductivity type metal oxide semiconductor device district and the semiconductor-based end of these grid structure both sides;
Utilize this first mask pattern as mask, flow into by ion in this second conductivity type dopant well of these grid structure both sides in this first conductivity type metal oxide semiconductor device district and form two lightly doped drains;
Utilize this first mask pattern as mask, flow into by ion in this second conductivity type dopant well of these grid structure both sides in this first conductivity type metal oxide semiconductor device district and form two dark pouch-type doped regions, wherein these two dark pouch-type doped regions are second conductivity type;
Remove this first mask pattern, and form spaced walls in the sidewall of this grid structure in this grid structure in this first conductivity type metal oxide semiconductor device district and this second conductivity type metal oxide semiconductor device district;
Form second mask pattern in the surface at this semiconductor-based end, this second mask pattern exposes this semiconductor-based end of these spaced walls both sides of this grid structure in this first conductivity type metal oxide semiconductor device district and this grid structure;
Utilize this second mask pattern as mask, flow into by ion in this second conductivity type dopant well of these grid structure both sides in this first conductivity type metal oxide semiconductor device district and form two source electrode; And
Remove this second mask pattern.
2. method as claimed in claim 1, other includes in this second conductivity type dopant well of these spaced walls both sides of this grid structure in this first conductivity type metal oxide semiconductor device district and to form before these two the dark pouch-type doped regions, utilizes this first mask pattern to form two pouch-type doped regions with second conductivity type earlier in this second conductivity type dopant well of these grid structure both sides in this first conductivity type metal oxide semiconductor device district.
3. method as claimed in claim 1, wherein this first conductivity type is the P type, and this second conductivity type is the N type.
4. method as claimed in claim 1, wherein the ion implantation energy of these two dark pouch-type doped regions is between 150 to 180kev.
5. method as claimed in claim 1, wherein the ion implantation concentration of these two dark pouch-type doped regions is between 10
13To 10
14Atom/cm
3Between.
6. CMOS transistor includes:
The semiconductor-based end, include the first conductivity type metal oxide semiconductor device district and the second conductivity type metal oxide semiconductor device district, this semiconductor-based end, include the second conductivity type dopant well in this first conductivity type metal oxide semiconductor device district, and include the first conductivity type dopant well in this second conductivity type metal oxide semiconductor device district;
A plurality of isolation structures are arranged in this semiconductor-based end;
Grid structure be positioned at the surface at this semiconductor-based end in this first conductivity type metal oxide semiconductor device district, and spaced walls is positioned at the both sides of this gate electrode;
Two source electrode are arranged in this second conductivity type dopant well of this spaced walls both sides of this grid structure in this first conductivity type metal oxide semiconductor device district;
Two lightly doped drains, be arranged in this first conductivity type metal oxide semiconductor device district these grid structure both sides this second conductivity type dopant well and respectively to should spaced walls; And
Two dark pouch-type doped regions, be arranged in this second conductivity type dopant well of these grid structure both sides in this first conductivity type metal oxide semiconductor device district, wherein these two dark pouch-type doped regions are second conductivity type, and respectively this dark pouch-type doped region is positioned at the below of this source electrode of this gate electrode both sides and this lightly doped drain and to should source electrode and this lightly doped drain.
7. CMOS transistor as claimed in claim 6, other comprises two pouch-type doped regions with second conductivity type, is arranged in this second conductivity type dopant well of these grid structure both sides in this first conductivity type metal oxide semiconductor device district.
8. CMOS transistor as claimed in claim 6, wherein this first conductivity type is the P type, and this second conductivity type is the N type.
9. method of making CMOS transistor includes:
The semiconductor-based end, be provided, include the first conductivity type metal oxide semiconductor device district and the second conductivity type metal oxide semiconductor device district, this semiconductor-based end, include the second conductivity type dopant well in this first conductivity type metal oxide semiconductor device district, and include the first conductivity type dopant well in this second conductivity type metal oxide semiconductor device district;
Form a plurality of isolation structures in the surface at this semiconductor-based end;
Form grid structure in this first conductivity type metal oxide semiconductor device district;
Form first mask pattern in the surface at this semiconductor-based end, this first mask pattern exposes this grid structure in this first conductivity type metal oxide semiconductor device district and the semiconductor-based end of these grid structure both sides;
Utilize this first mask pattern as mask, flow into by ion in this second conductivity type dopant well of these grid structure both sides in this first conductivity type metal oxide semiconductor device district and form two lightly doped drains;
Remove this first mask pattern, and form spaced walls in the sidewall of this grid structure in this grid structure in this first conductivity type metal oxide semiconductor device district and this second conductivity type metal oxide semiconductor device district;
Form second mask pattern in the surface at this semiconductor-based end, this second mask pattern exposes this semiconductor-based end of these spaced walls both sides of this grid structure in this first conductivity type metal oxide semiconductor device district and this grid structure;
Utilize this second mask pattern as mask, flow into by ion in this second conductivity type dopant well of these spaced walls both sides of this grid structure in this first conductivity type metal oxide semiconductor device district and form two source electrode;
Utilize this second mask pattern as mask, flow into by ion in this second conductivity type dopant well of these spaced walls both sides of this grid structure in this first conductivity type metal oxide semiconductor device district and form two dark pouch-type doped regions, wherein these two dark pouch-type doped regions are second conductivity type; And
Remove this second mask pattern.
10. method as claimed in claim 9, other included before removing this first mask pattern, utilized this first mask pattern to form two pouch-type doped regions with second conductivity type earlier in this second conductivity type dopant well of these grid structure both sides in this first conductivity type metal oxide semiconductor device district.
11. method as claimed in claim 9, wherein this first conductivity type is the P type, and this second conductivity type is the N type.
12. method as claimed in claim 9, wherein the ion implantation energy of these two dark pouch-type doped regions is between 150 to 180kev.
13. method as claimed in claim 9, wherein the ion implantation concentration of these two dark pouch-type doped regions is between 10
13To 10
14Atom/cm
3Between.
14. a CMOS transistor includes:
The semiconductor-based end, include the first conductivity type metal oxide semiconductor device district and the second conductivity type metal oxide semiconductor device district, this semiconductor-based end, include the second conductivity type dopant well in this first conductivity type metal oxide semiconductor device district, and include the first conductivity type dopant well in this second conductivity type metal oxide semiconductor device district;
A plurality of isolation structures are arranged in this semiconductor-based end;
Grid structure is positioned at the surface at this semiconductor-based end in this first conductivity type metal oxide semiconductor device district and the both sides that spaced walls is positioned at this gate electrode;
Two source electrode are arranged in this second conductivity type dopant well of spaced walls both sides of this grid structure in this first conductivity type metal oxide semiconductor device district;
Two lightly doped drains, be arranged in this first conductivity type metal oxide semiconductor device district these grid structure both sides this second conductivity type dopant well and respectively to should two spaced walls; And
Two dark pouch-type doped regions, be arranged in this second conductivity type dopant well of this spaced walls both sides of this grid structure in this first conductivity type metal oxide semiconductor device district, wherein these two dark pouch-type doped regions are second conductivity type, and respectively this dark pouch-type doped region be positioned at these gate electrode both sides this source electrode the below and to should source electrode.
15. CMOS transistor as claim 14, other comprises two pouch-type doped regions with second conductivity type, is arranged in this second conductivity type dopant well of these grid structure both sides in this first conductivity type metal oxide semiconductor device district.
16. as the CMOS transistor of claim 14, wherein this first conductivity type is the P type, and this second conductivity type is the N type.
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