CN114171386A - Process optimization method for carrier storage groove gate bipolar transistor structure - Google Patents
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- CN114171386A CN114171386A CN202111477741.5A CN202111477741A CN114171386A CN 114171386 A CN114171386 A CN 114171386A CN 202111477741 A CN202111477741 A CN 202111477741A CN 114171386 A CN114171386 A CN 114171386A
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- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000003860 storage Methods 0.000 title claims abstract description 27
- 238000005457 optimization Methods 0.000 title claims abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 25
- 238000005468 ion implantation Methods 0.000 claims description 19
- 229920005591 polysilicon Polymers 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 238000002513 implantation Methods 0.000 claims description 2
- 238000002347 injection Methods 0.000 abstract description 17
- 239000007924 injection Substances 0.000 abstract description 17
- 238000000137 annealing Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 210000000746 body region Anatomy 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000003912 environmental pollution Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a process optimization method for a carrier storage groove gate bipolar transistor structure. By adjusting the injection sequence and the injection energy of the carrier storage layer, the injection efficiency of the carrier storage layer is obviously improved, the concentration of the carrier storage layer is increased, and the conduction voltage drop and the saturation current of the bipolar transistor of the carrier storage groove gate are reduced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a process optimization method for a carrier storage groove gate bipolar transistor structure.
Background
Power electronic equipment is the basis for the development and progress of power electronic technology. High performance power electronics can save electrical energy, thereby saving fossil energy and reducing environmental pollution. An Insulated Gate Bipolar Transistor (IGBT) is a Bipolar Junction Transistor (BJT) controlled by a metal-oxide semiconductor field effect transistor (MOSFET), which combines the high frequency characteristics of a power MOSFET with the low on-state voltage drop advantages of a BJT and has the characteristics of high input impedance and low switching loss. At present, the IGBT becomes a core device for energy conversion and transmission, and is a "CPU" of a power electronic device.
Although the IGBT has the characteristic of handling high voltage and large current, N is used-The drift region has a large number of excess carriers and therefore it experiences a current tailing phenomenon when turned off. Accordingly, there is a trade-off between carrier storage trench gate bipolar transistor (IGBT) turn-on voltage drop and turn-off time (or turn-off power consumption). The folding relation of the CSTBT structure to greatly optimize the device becomes a great breakthrough of the development history of the IGBT device. The carrier storage layer (CS layer) under the P-type body region of csbt suppresses accumulation of holes on the cathode side in the on state, thereby improving hole concentration and conductivity modulation of csbt on the cathode side. The on-state voltage drop of the CSTBT decreases with increasing doping concentration of the CS layer. In the prior art, CS layer injection is limited by a plurality of long-time high-temperature annealing processes in subsequent processes, so that the efficiency is low, and the conduction loss, the safe working area and other properties of CSTBT are greatly reduced.
Disclosure of Invention
The invention discloses a process optimization method of a carrier storage groove gate bipolar transistor structure, which comprises the following steps: in N-Forming a P-type well region on the doped silicon substrate through P-type ion implantation; etching to form a groove, growing a first oxidation layer serving as a gate oxide layer, covering the surface of the groove and extending to cover the surface of the P-type well region; depositing a first polycrystalline silicon layer to cover the first oxide layer on the surface of the groove and completely fill the groove, wherein the upper surface of the first polycrystalline silicon layer is flush with the upper surface of the first oxide layer; etching the first oxide layer, only keeping the first oxide layer at the edge to expose the first polysilicon layer and part of the surface of the P-type well region, and forming N by N-type ion implantation+Removing the first oxide layer on the surface to expose the substrate; forming a carrier storage layer below the P-type well region through high-energy N-type ion implantation; depositing a second oxide layer to cover the surface of the substrate, etching to remove the second oxide layer at the edge to expose part of the silicon substrate, and performing P-type ion implantation to form P+A zone; at the P+Forming a second polysilicon layer above the region; growing a third oxidation layer to cover the surface of the second polycrystalline silicon layer; forming back P-well region by P-type ion implantation and forming back P-well region by N-type ion implantationAnd forming a back N well region, wherein the back P well region is positioned at the bottom, and the back N well region is positioned above the back P well region.
In the method for optimizing a process of a carrier storage trench gate bipolar transistor structure according to the present invention, preferably, the P-channel is selected from the group consisting of P-channel, and P-channel+The step of forming a second polysilicon layer over the region specifically comprises: depositing a second polysilicon layer to completely cover P+A region surface and a second oxide layer surface; and etching to remove the second polysilicon layer above the second oxide layer.
Has the advantages that:
by adjusting the injection sequence and the injection energy of the carrier storage layer, the injection efficiency of the CS layer can be obviously improved, the concentration of the CS layer is increased, and the conduction voltage drop and the saturation current of the CSTBT are reduced. Meanwhile, the trade-off relation between the on-state voltage drop and the off-state loss is obviously optimized. The improved new process can further reduce the depth of the groove, and the comprehensive performance of the CSTBT is further improved.
Drawings
Fig. 1 is a flow chart of a process optimization method for a carrier storage trench gate bipolar transistor structure.
Fig. 2 to 17 are schematic structural diagrams of steps of a process optimization method for a carrier storage trench gate bipolar transistor structure.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly and completely understood, the technical solutions in the embodiments of the present invention will be described below with reference to the accompanying drawings in the embodiments of the present invention, and it should be understood that the specific embodiments described herein are only for explaining the present invention and are not intended to limit the present invention. The described embodiments are only some embodiments of the invention, not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "upper", "lower", "vertical", "horizontal", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Furthermore, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described below in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details. Unless otherwise specified below, each part in the device may be formed of a material known to those skilled in the art, or a material having a similar function developed in the future may be used.
Fig. 1 is a flow chart of a process optimization method for a carrier storage trench gate bipolar transistor structure. As shown in fig. 1, the process optimization method for the carrier storage trench gate bipolar transistor structure specifically includes the following steps:
step S1: at a doping concentration of 1X 1016cm-3～5×1016cm-3N of (A)-A P-type well region 101 is formed on a doped silicon substrate 100 by P-type ion implantation, and the resulting structure is shown in fig. 1.
Step S2: as shown in fig. 2, a trench 102 is etched by using a photoresist as a mask layer, and the trench 102 penetrates the P-type well region 101. Then, a first oxide layer 103 (e.g., SiO) is grown2) As a gate oxide layer, it covers the surface of trench 102 and extends to cover the surface of P-type well region 101. The structure of the device after the gate oxide layer is formed is schematically shown in fig. 3.
Step S3: a first polysilicon layer 104 is deposited on the surface of the first oxide layer 103 so as to cover the first oxide layer 103 and completely fill the trench, and the resulting structure is shown in fig. 5. The first polysilicon layer 104 is subjected to chemical mechanical polishing, and the first oxide layer 103 is used as a stop layer, so that the upper surface of the first polysilicon layer 104 is flush with the upper surface of the first oxide layer 103, and the resulting structure is shown in fig. 6.
Step S4: the first oxide layer 103 is etched by using the photoresist 105 as a masking layer, only the first oxide layer 103 at the edge is remained, and the first polysilicon layer 104 and a part of the surface of the P-type well region 101 are exposed, and the resulting structure is shown in fig. 7. Then, N-type ion implantation is performed to form a dopant concentration of 5 × 10 in the upper portions of P-type well region 101 and first polysilicon layer 104, respectively18cm-3N+Regions 106,107, the resulting structure is shown in FIG. 8.
Step S5 is to remove the first oxide layer 103 on the surface to expose the substrate, and then perform high-energy N-type ion implantation on the region outside the trench in the substrate with the photoresist 108 as a blocking layer, so as to form a carrier storage layer 109 below the P-type well region, where the resulting structure is shown in fig. 9. Wherein, the type of the high-energy N-type ion implantation is phosphorus, and the implantation dosage is 2 multiplied by 1013cm-2The energy was 180 KeV.
Step S6, as shown in fig. 10 to 12, depositing a second oxide layer 110 to cover the substrate surface, etching to remove the second oxide layer 110 at the edge to expose part of the silicon substrate, and performing P-type ion implantation to form a doped layer with a doping concentration of 3 × 1018cm-3P of+And a region 111.
In step S7, second polysilicon layer 112 is deposited so as to completely cover the substrate surface, i.e., P+The surface of the region 111 and the surface of the second oxide layer 110, the resulting structure is shown in fig. 13. The second polysilicon layer 112 over the second oxide layer 110 is etched away, at P+ Second polysilicon layer 112 remains over region 111 and the resulting structure is shown in fig. 14.
Step S8, a third oxide layer 113 is grown to cover the surface of the second polysilicon layer 112, and the resulting structure is shown in fig. 15.
In step S9, back P-well regions 114 are formed by P-type ion implantation, and the resulting structure is shown in fig. 16. Backside nwell region 115 is formed by N-type ion implantation, wherein backside P-well region 114 is at the bottom and backside nwell region 115 is above backside P-well region 114, and the resulting structure is shown in fig. 17. Thus, the preparation of the carrier storage groove gate bipolar transistor is completed.
The invention stores by adjusting the current carrierThe injection sequence of the layers improves the injection energy, effectively improves the injection efficiency of the carrier storage layer, and increases the concentration of the carrier storage layer. In the traditional process, a CS layer is formed by injecting N-type ions before groove etching and carrying out high-temperature annealing and diffusion for multiple times. The invention postpones the CS layer injection step to the emitter injection (P)+Most of the high-temperature annealing process is completed before the region is injected and the CS layer is injected, so that the problem of low injection efficiency of the CS layer caused by the high-temperature annealing process in the prior art is effectively solved.
Compared with the CSTBT of the traditional CS layer injection process, the CSTBT of the invention which is improved by the process optimization method of the current carrier storage groove gate bipolar transistor structure has higher CS layer concentration (same injection dosage), lower conduction voltage drop and lower saturation current (larger safe working area). In addition, the injection efficiency of the CS layer is improved, and the compromise relationship between the turn-on voltage drop and the turn-off loss of the CSTBT is further optimized; the results show that the saturation current and the conduction voltage drop of the CSTBT are respectively reduced by 19.7 percent and 15.1 percent after the process is improved. Compared with the traditional CS layer injection process, the CSTBT realizing the same on-state voltage drop reduces the saturation current and the turn-off time by 76.1 percent and 6.8 percent respectively.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.
Claims (3)
1. A process optimization method for a carrier storage groove gate bipolar transistor structure is characterized in that,
the method comprises the following steps:
in N-Forming a P-type well region on the doped silicon substrate through P-type ion implantation;
etching to form a groove, growing a first oxidation layer serving as a gate oxide layer, covering the surface of the groove and extending to cover the surface of the P-type well region;
depositing a first polycrystalline silicon layer to cover the first oxide layer on the surface of the groove and completely fill the groove, wherein the upper surface of the first polycrystalline silicon layer is flush with the upper surface of the first oxide layer;
etching the first oxide layer, only keeping the first oxide layer at the edge to expose the first polysilicon layer and part of the surface of the P-type well region, and forming N by N-type ion implantation+Removing the first oxide layer on the surface to expose the substrate;
forming a carrier storage layer below the P-type well region through high-energy N-type ion implantation;
depositing a second oxide layer to cover the surface of the substrate, etching to remove the second oxide layer at the edge to expose part of the silicon substrate, and performing P-type ion implantation to form P+A zone;
at the P+Forming a second polysilicon layer above the region;
growing a third oxidation layer to cover the surface of the second polycrystalline silicon layer;
a back P well region is formed through P-type ion implantation, and a back N well region is formed through N-type ion implantation, wherein the back P well region is located at the bottom, and the back N well region is located above the back P well region.
2. The method for optimizing a process of a carrier storage trench gate bipolar transistor structure as claimed in claim 1,
at the P+The step of forming a second polysilicon layer over the region specifically comprises:
depositing a second polysilicon layer to completely cover P+A region surface and a second oxide layer surface;
and etching to remove the second polysilicon layer above the second oxide layer.
3. The method for optimizing a process of a carrier storage trench gate bipolar transistor structure as claimed in claim 1,
the implantation dosage of the high-energy N-type ion implantation is 2 multiplied by 1013cm-2The energy was 180 KeV.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111477741.5A CN114171386A (en) | 2021-12-06 | 2021-12-06 | Process optimization method for carrier storage groove gate bipolar transistor structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111477741.5A CN114171386A (en) | 2021-12-06 | 2021-12-06 | Process optimization method for carrier storage groove gate bipolar transistor structure |
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| Publication Number | Publication Date |
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| CN114171386A true CN114171386A (en) | 2022-03-11 |
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| CN202111477741.5A Pending CN114171386A (en) | 2021-12-06 | 2021-12-06 | Process optimization method for carrier storage groove gate bipolar transistor structure |
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- 2021-12-06 CN CN202111477741.5A patent/CN114171386A/en active Pending
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