CN113540241A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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CN113540241A
CN113540241A CN202010311746.XA CN202010311746A CN113540241A CN 113540241 A CN113540241 A CN 113540241A CN 202010311746 A CN202010311746 A CN 202010311746A CN 113540241 A CN113540241 A CN 113540241A
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region
layer
substrate
drift region
semiconductor structure
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赵猛
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/66689—Lateral DMOS transistors, i.e. LDMOS transistors with a step of forming an insulating sidewall spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors

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  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor structure and method of forming the same, wherein the structure comprises: the semiconductor device comprises a substrate, a first substrate and a second substrate, wherein a doped drift region and a doped body region are arranged in the substrate, and the conductivity type of the drift region is opposite to that of the body region; a gate structure on the substrate, a portion of the gate structure being on the drift region and a portion of the gate structure being on the body region; a blocking layer located adjacent to a portion of the drift region surface of the gate structure; and the doped layer is positioned in the substrate or in the blocking layer, is positioned at the contact interface of the blocking layer and the drift region, and has repair ions in the doped layer. The repair ions can be combined with dangling bonds existing in the barrier layer, and the high-voltage resistance of the formed semiconductor structure is improved.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
An LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor is a power device that forms a lateral current path on the surface of a Semiconductor substrate through planar diffusion (planar diffusion), and is commonly used in radio frequency power circuits. In contrast to conventional MOS transistors, a lightly doped region, referred to as a drift region, is typically provided between the source and drain regions of an LDMOS transistor. Therefore, when the LDMOS transistor is connected to a high voltage between the source region and the drain region, the drift region can withstand a higher voltage drop due to the relatively low impurity concentration and the high resistance state of the drift region, so that the LDMOS transistor can have a higher breakdown voltage.
The LDMOS transistor is compatible with a Complementary Metal Oxide Semiconductor (CMOS) process, so that the LDMOS transistor is widely used in a power device. For LDMOS transistors used as power integrated circuits, the on-resistance (R)dson) And Breakdown Voltage (BV) are two important metrics for the device performance.
However, the performance of the existing LDMOS transistor is still poor.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which are used for improving the performance of the formed semiconductor structure.
To solve the above technical problem, an embodiment of the present invention provides a semiconductor structure, including: the semiconductor device comprises a substrate, a first substrate and a second substrate, wherein a doped drift region and a doped body region are arranged in the substrate, and the conductivity type of the drift region is opposite to that of the body region; a gate structure on the substrate, a portion of the gate structure being on the drift region and a portion of the gate structure being on the body region; a blocking layer located adjacent to a portion of the drift region surface of the gate structure; and the doped layer is positioned in the substrate or in the blocking layer, is positioned at the contact interface of the blocking layer and the drift region, and has repair ions in the doped layer.
Optionally, the blocking layer is further located on the sidewall surface and the top surface of the gate structure.
Optionally, the barrier layer is doped with the repair ions.
Optionally, the repair ions include: one or more of fluoride ion, carbon ion and nitrogen ion.
Optionally, the thickness of the doped layer ranges from 3 nm to 10 nm.
Optionally, the material of the barrier layer includes: silicon oxide, silicon carbonitride, silicon boronitride, silicon oxycarbonitride or silicon oxynitride.
Optionally, the method further includes: the drain region is positioned in the drift region on one side of the barrier layer and the grid structure, and the source region is positioned in the body region on one side of the grid structure.
Optionally, the drain region and the drift region have the same conductivity type.
Optionally, the substrate further has a well region, the drift region and the body region are located in the well region, and the conductivity type of the well region is the same as the conductivity type of the drift region.
Optionally, the method further includes: and the lightly doped regions are positioned in the substrate at two sides of the grid structure.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate is internally provided with a doped drift region and a doped body region, and the conductivity type of the drift region is opposite to that of the body region; forming a gate structure on the substrate, wherein part of the gate structure is located on the drift region, and part of the gate structure is located on the body region; forming an initial barrier layer on the surface of the drift region, the surface of the side wall and the surface of the top of the gate structure and the surface of the body region; and forming a doping layer in the substrate or the initial barrier layer by adopting a first ion implantation process, wherein the doping layer is positioned at the contact interface of the initial barrier layer and the drift region, and the doping layer is internally provided with repairing ions.
Optionally, the first ion implantation process further dopes repair ions in the initial barrier layer.
Optionally, the method further includes: after the doped layer is formed, part of the initial blocking layer is removed, the surface of the substrate is exposed, and the blocking layer is formed on the part of the surface of the drift region adjacent to the gate structure.
Optionally, the blocking layer is further located on a sidewall surface and a top surface of the gate structure.
Optionally, the method for removing a portion of the initial barrier layer includes: forming a patterned layer on the initial barrier layer surface, wherein the patterned layer exposes the initial barrier layer surface on a part of the drift region and the body region; and etching the initial barrier layer by taking the patterning layer as a mask until the surface of the substrate is exposed to form the barrier layer.
Optionally, the first ion implantation process is single-angle implantation, the implantation direction is a direction from the drain region to the source region, and the implantation angle is a direction from the implantation direction to a normal line of the substrate surface.
Optionally, the single angle ranges from 20 degrees to 45 degrees.
Optionally, the method further includes: and forming a drain region in the drift region on one side of the barrier layer and the gate structure, and forming a source region in the body region on one side of the gate structure.
Optionally, the method for forming the source region and the drain region includes: and performing a second ion implantation process on the drift region and the body region by taking the barrier layer and the gate structure as masks to form the source region and the drain region.
Optionally, the parameters of the second ion implantation process include: the angle of implantation is in the range of 0 to 15 degrees, and the implantation dose is 1.0e14atom/cm2To 5.0e15atom/cm2The implantation energy range is 5KeV to 40 KeV.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
in the semiconductor structure provided by the technical scheme of the invention, the doping layer is positioned at the contact interface of the barrier layer and the drift region, and the doping layer is internally provided with repair ions. The repair ions can be combined with more dangling bonds existing at the interface of the blocking layer and the drift region, so that the charges existing in the blocking layer can be effectively reduced, and the charges induced by the drift region positioned at the bottom of the blocking layer are reduced. The electric charge induced by the drift region is reduced, so that the additional electric field of the drift region is reduced, the breakdown voltage of the drift region is improved, and the high voltage resistance of the formed semiconductor structure is improved.
Furthermore, the blocking layer is doped with repair ions, and the repair ions can be combined with unsaturated bonds in the blocking layer, so that charges in the blocking layer can be further reduced, charges induced by a drift region at the bottom of the blocking layer are further reduced, and the high voltage resistance of the formed semiconductor structure is further improved.
According to the forming method of the semiconductor structure, the doped layer is formed at the contact interface of the initial blocking layer and the drift region, and the doped layer is internally provided with the repair ions. The electric charge induced by the drift region is reduced, so that the additional electric field of the drift region is reduced, the breakdown voltage of the drift region is improved, and the high voltage resistance of the formed semiconductor structure is improved.
Further, the first ion implantation process also dopes repair ions in the initial barrier layer. The repair ions can be combined with unsaturated bonds in a subsequently formed blocking layer, so that charges in the blocking layer are further reduced, charges induced in a drift region at the bottom of the blocking layer are further reduced, and the high voltage resistance of the formed semiconductor structure is further improved.
Further, the first ion implantation process is single-angle implantation. Through the first ion implantation process, the doping layer is formed, repair ions are doped in the initial blocking layer, the body region is effectively blocked by the grid structure, and the repair ions are less doped in the body region, so that the good carrier mobility in the body region is kept, the working current is improved, and the performance of the formed semiconductor structure is good.
Drawings
FIG. 1 is a schematic cross-sectional view of a semiconductor structure;
fig. 2 to 10 are schematic cross-sectional views of steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Detailed Description
As described in the background, semiconductor structures have poor performance.
The reason for the poor performance of the semiconductor structure is described in detail below with reference to the accompanying drawings, in which fig. 1 is a schematic cross-sectional view of a semiconductor structure.
Referring to fig. 1, the semiconductor structure includes: a substrate 100, wherein the substrate 100 has a drift region 101 and a body region 102 therein, and the conductivity type of the drift region 101 is opposite to the conductivity type of the body region 102; a gate structure 110 on the substrate 100, wherein a portion of the gate structure 110 is located on the drift region 101, and a portion of the gate structure 110 is located on the body region 102; a barrier layer 120 located adjacent to a portion of the surface of the drift region 101 of the gate structure 110, and the barrier layer 120 is located on the top surface and sidewall surface of the gate structure; a drain region 130 in the drift region 101 on one side of the barrier layer 120 and the gate structure 110, and a source region 140 in the body region 102 on one side of the gate structure 110.
In the above structure, the barrier layer 120 functions to increase the distance between the drain region 130 and the gate structure 110.
However, the semiconductor structure is a high voltage tolerant device, and when a higher voltage is applied to the drain region 130 and the gate structure 110, hot carriers are easily generated in the drain region 130, which causes the blocking layer 120 to generate unsaturated bonds, and particularly, more dangling bonds are easily generated on the surface of the blocking layer 120, that is, charges are easily generated in the blocking layer 120. The charges in the blocking layer 120 are easy to induce the charges in the drift region 101 located at the bottom of the blocking layer 120, so that an additional electric field is generated in the drift region 101 due to the charge induction, and further, thermal collision is easy to generate, so that the drift region 101 located at the bottom of the blocking layer 120 is easy to burn, and the performance is poor.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: after the initial barrier layer is formed, a first ion implantation process is adopted, a doped layer is formed in the substrate or in the barrier layer, the doped layer is located at the contact interface of the barrier layer and the drift region, repair ions are arranged in the doped layer, the repair ions can be combined with more dangling bonds existing at the interface of the barrier layer and the drift region, charges existing in the barrier layer can be effectively reduced, and the high voltage resistance of the formed semiconductor structure is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 10 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Providing a substrate, wherein the substrate has a drift region and a body region, and the conductivity type of the drift region is opposite to that of the body region, and referring to fig. 2 to fig. 4, the process of specifically forming the substrate, and the drift region and the body region located in the substrate is shown.
Referring to fig. 2, a substrate 200 is provided.
The material of the substrate 200 includes silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); silicon-on-insulator (SOI), germanium-on-insulator (GOI); or may be other materials such as group iii-v compounds such as gallium arsenide. In this embodiment, the material of the substrate 200 is silicon.
In the present embodiment, the substrate 200 has a well 201 therein.
The conductivity type of the well region 201 includes: n-type or P-type.
In the present embodiment, the semiconductor structure to be formed is an N-type LDMOS, and the conductivity type of the well 201 is N-type.
In the present embodiment, the well region 201 is formed by doping N-type ions into the substrate 200 through an ion implantation process. In other embodiments, the substrate 200 is doped with P-type ions by an ion implantation process.
The N-type ions are one or more of phosphorus ions, arsenic ions and antimony ions; the P-type ions are one or more of boron ions, indium ions and gallium ions.
In this embodiment, the base 200 is a planar substrate.
In other embodiments, the substrate comprises: the device comprises a substrate and a fin part located on the surface of part of the substrate.
Referring to fig. 3, a doped drift region 210 is formed in the substrate 200.
The drift region 210 is used to separate a drain region and a channel region formed subsequently, thereby extending a current path of the semiconductor structure and improving a breakdown voltage.
The drift region 210 is doped with first ions.
The method for forming the drift region 210 comprises the following steps: a first mask layer 211 is formed on the surface of the substrate 200, and the first mask layer 211 is used for defining the position and the size of a drift region; and performing an ion implantation process on the substrate 200 by using the first mask layer 211 as a mask, so as to form the drift region 210 in the substrate 200.
Specifically, in the present embodiment, the drift region 210 is formed in the well region 201.
In this embodiment, the semiconductor structure to be formed is an N-type LDMOS, and the first ions are N-type ions, which includes: one or more of phosphorus ions, arsenic ions, or antimony ions, that is, the conductivity type of the drift region 210 is N-type.
In other embodiments, the semiconductor structure to be formed is a P-type LDMOS, and the first ions may also be P-type ions, including: one or more of boron ions, indium ions, or gallium ions.
After the drift region 210 is formed, the method further includes: the first mask layer 211 is removed.
In this embodiment, the first mask layer 211 is made of a photoresist, and the first mask layer 211 is removed by an ashing process.
Referring to fig. 4, a doped body region 220 is formed in the substrate 200, and the conductivity type of the drift region 210 is opposite to that of the body region 220.
The body region 220 serves to separate a source region and a channel region, which are formed later.
The body region 220 is doped with second ions.
The method for forming the body region 220 includes: forming a second mask layer 221 on the surface of the substrate 200, wherein the second mask layer 221 is used for defining the position and the size of a body region; and performing an ion implantation process on the substrate 200 by using the second mask layer 221 as a mask to form the body region 220 in the substrate 200.
Specifically, in the present embodiment, the body region 220 is formed in the well region 201.
In this embodiment, the semiconductor structure to be formed is an N-type LDMOS, and the second ions are P-type ions, which includes: one or more of boron ions, indium ions, or gallium ions, that is, the conductivity type of the body region 220 is P-type.
The conductivity types of the drift region 210 and the body region 220 are opposite due to the opposite conductivity types of the first ions and the second ions.
In this embodiment, the drift region 210 and the body region 220 are adjacent. In other embodiments, the drift region and the body region have a space therebetween.
In other embodiments, the semiconductor structure to be formed is a P-type LDMOS, and the second ions may also be N-type ions, including: one or more of phosphorus ions, arsenic ions, or antimony ions.
After the body region 220 is formed, the method further includes: the second mask layer 221 is removed.
In this embodiment, the second mask layer 221 is made of a photoresist, and the second mask layer 221 is removed by an ashing process.
Referring to fig. 5, a gate structure 230 is formed on the substrate 200, a portion of the gate structure 230 is located on the drift region 210, and a portion of the gate structure 230 is located on the body region 220.
The method for forming the gate structure 230 includes: forming a gate material layer (not shown) on the substrate 200; forming a third mask layer (not shown in the figure) on the surface of the gate material layer, wherein the third mask layer covers a part of the gate material layer on the drift region 210 and a part of the body region 220; and etching the gate material layer by using the third mask layer as a mask until the surface of the substrate 200 is exposed, so that the gate material layer forms a gate layer 231 to form the gate structure 230.
In this embodiment, the method for forming the gate structure 230 further includes: forming a gate dielectric material layer (not shown) on the substrate 200 before forming the gate material layer; forming the gate material layer on the surface of the gate dielectric material layer; and etching the gate dielectric material layer and the gate material layer by taking the third mask layer as a mask until the surface of the substrate 200 is exposed, so that the gate dielectric material layer forms a gate dielectric layer 232, the gate material layer forms a gate electrode layer 231, and the gate structure 230 is formed.
The gate structure 230 includes: a gate dielectric layer 232 on the surfaces of the partial drift region 210 and the partial body region 220, and a gate layer 231 on the surface of the gate dielectric layer 232.
In this embodiment, the gate structure 230 further includes: and the side walls 233 are positioned on the surfaces of the side walls of the gate dielectric layer 232 and the gate layer 231.
The side walls 233 serve to protect the side wall surfaces of the gate dielectric layer 232 and the gate layer 231 from the influence of subsequent processes, so that the morphology is maintained and the stability of electrical properties is improved; on the other hand, for subsequent location in the lightly doped region.
The forming method of the side wall 233 includes: forming a sidewall material layer (not shown in the figure) on the surface of the substrate 200, the top surface and the sidewall surface of the gate layer 231, and the sidewall surface of the gate dielectric layer 232; and etching back the side wall material layer until the surface of the substrate 200 and the top surface of the gate layer are exposed, thereby forming the side wall 233.
In this embodiment, the gate structure 230 further includes: and a protection layer (not shown) on the top surface of the gate layer 231, wherein the protection layer is used for protecting the top surface of the gate layer 231, so that the influence of the gate layer 231 on the subsequent processes is reduced, and the performance of the formed semiconductor structure is improved.
Referring to fig. 6, lightly doped regions (not shown) are formed in the substrate 200 at two sides of the gate structure 230.
The lightly doped region is used for effectively improving the hot carrier injection effect.
The forming method of the lightly doped region comprises the following steps: and performing an ion implantation process on the substrate 200 by using the gate structure 230 as a mask, thereby forming the lightly doped region in the substrate 200.
Specifically, the lightly doped regions are formed in the drift region 210 and the body region 220, respectively.
In this embodiment, the semiconductor structure to be formed is an N-type LDMOS, and the conductivity type of the lightly doped region is N-type.
In other embodiments, the semiconductor structure to be formed is a P-type LDMOS, and the conductivity type of the lightly doped region is P-type.
Referring to fig. 7, an initial barrier layer 240 is formed on the surface of the drift region 210, the sidewall surface and the top surface of the gate structure 230, and the surface of the body region 220.
The initial barrier layer 240 provides material for subsequent barrier layer formation.
The materials of the initial barrier layer 240 include: silicon oxide, silicon carbonitride, silicon boronitride, silicon oxycarbonitride or silicon oxynitride.
In this embodiment, the material of the initial barrier layer 240 is silicon oxide.
The formation process of the initial barrier layer 240 includes: a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
In the present embodiment, the initial barrier layer 240 is formed using an atomic layer deposition process. The initial barrier layer 240 formed by the atomic layer deposition process has the advantages of step coverage, uniform thickness and good appearance, and is beneficial to the subsequent etching of the barrier layer formed by the initial barrier layer, so that over-etching of a substrate or a gate structure is avoided, and the stability of the formed semiconductor structure is improved.
Referring to fig. 8, a first ion implantation process is performed to form a doped layer 250 in the substrate 200 or the initial blocking layer 240, wherein the doped layer 250 is located at an interface where the initial blocking layer 240 and the drift region 210 are in contact, and the doped layer 250 has repairing ions therein.
The repair ions include: one or more of fluoride ion, carbon ion and nitrogen ion.
In this embodiment, the implanted repair ions are fluorine ions.
By forming the doped layer 250 at the contact interface between the initial blocking layer 240 and the drift region 210 and having the repair ions in the doped layer 250, the repair ions can be combined with dangling bonds existing on the surface of the blocking layer formed later, so that the charges existing in the blocking layer can be effectively reduced, and the charges induced by the drift region 210 at the bottom of the blocking layer can be reduced. The reduction of the charge induced in the drift region 210 is beneficial to reducing the additional electric field of the drift region 210, and further beneficial to improving the breakdown voltage of the drift region 210, so that the high voltage resistance of the formed semiconductor structure is improved.
The first ion implantation process is single-angle implantation, the implantation direction is a direction from the drain region 210 to the source region 220, and the implantation angle is a direction from the implantation direction to a normal line of the surface of the substrate 200.
In this embodiment, the base 200 is a planar substrate, and the normal line refers to a line perpendicular to the surface of the base.
In other embodiments, the substrate comprises: the fin portion that lies in the substrate surface, the normal refers to the line perpendicular to the substrate surface.
The single angle ranges from 20 degrees to 45 degrees.
The first ion implantation process also dopes repair ions within the initial barrier layer 240. The repair ions can be combined with unsaturated bonds existing in a subsequently formed blocking layer, so that charges existing in the blocking layer are further reduced, charges induced by the drift region 210 located at the bottom of the blocking layer are further reduced, and the high voltage resistance of the formed semiconductor structure is further improved.
The first ion implantation process is single angle implantation. Through the first ion implantation process, the doping layer 250 is formed, and repair ions are doped in the initial blocking layer 240, and meanwhile, the body region 220 is effectively blocked by the gate structure 230, so that the repair ions are less doped in the body region 220, and therefore, the good carrier mobility in the body region 220 is kept, the working current is improved, and the performance of the formed semiconductor structure is good.
Referring to fig. 9, after the doped layer 250 is formed, a portion of the initial blocking layer 240 is removed to expose the surface of the substrate 200, and a blocking layer 241 is formed on a portion of the drift region 250 adjacent to the gate structure 230.
The barrier layer 241 is used to make a space between the subsequently formed drain region and the gate structure 230, so as to prolong a current path of the semiconductor structure and improve a breakdown voltage.
The method for removing part of the initial barrier layer 240 comprises the following steps: forming a patterned layer (not shown) on the surface of the initial barrier layer 240, the patterned layer exposing a portion of the surface of the initial barrier layer 240 on the drift region 210 and on the body region 220; and etching the initial barrier layer 240 by using the patterning layer as a mask until the surface of the substrate 200 is exposed to form the barrier layer 241.
The barrier 241 is formed by etching the initial barrier 240, and the material of the barrier 241 includes: silicon oxide, silicon carbonitride, silicon boronitride, silicon oxycarbonitride or silicon oxynitride.
Referring to fig. 10, a drain region 260 is formed in the drift region 210 at one side of the barrier layer 241 and the gate structure 230, and a source region 270 is formed in the body region 220 at one side of the gate structure 230.
The method for forming the source region 260 and the drain region 270 includes: and performing a second ion implantation process on the drift region 210 and the body region 220 by using the barrier layer 241 and the gate structure 230 as masks to form the source region 270 and the drain region 260.
The parameters of the second ion implantation process include: the angle of implantation is in the range of 0 to 15 degrees, and the implantation dose is 1.0e14atom/cm2To 5.0e15atom/cm2The implantation energy range is 5KeV to 40 KeV.
The range of the angle of implantation refers to the angle between the direction of implantation and the normal to the surface of the substrate 200.
The drain region 260 is doped with third ions, the source region 270 is doped with fourth ions, and the conductivity types of the third ions and the fourth ions are the same.
In this embodiment, the semiconductor structure to be formed is an N-type LDMOS, and the third ions and the fourth ions are N-type ions, which includes: one or more of phosphorus ion, arsenic ion or antimony ion, and accordingly, the drain region 260 and the source region 270 are both N-type in conductivity type,
in the present embodiment, phosphorus ions are implanted in both the drift region 210 and the body region 220 by the second ion implantation process.
Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, with reference to fig. 10, including: a substrate 200, wherein the substrate 200 has a doped drift region 210 and a doped body region 220 therein, and the conductivity type of the drift region 210 is opposite to the conductivity type of the body region 220; a gate structure 230 on the substrate 200, a portion of the gate structure 230 being on the drift region 210, and a portion of the gate structure 239 being on the body region 220; a barrier layer 241 located adjacent to a portion of the surface of the drift region 210 of the gate structure 230; a doped layer 250 located in the substrate 200 or the blocking layer 241, wherein the doped layer 250 is located at an interface where the blocking layer 241 and the drift region 210 are contacted, and the doped layer 250 has repairing ions therein.
Since the doped layer 250 is located at the interface where the blocking layer 241 and the drift region 210 are in contact, the doped layer 250 has repair ions therein. Because the repair ions can be combined with more dangling bonds existing at the interface between the blocking layer 241 and the drift region 210, the charges existing in the blocking layer 241 can be effectively reduced, and thus the charges induced by the drift region 210 located at the bottom of the blocking layer 241 are reduced. The reduction of the charge induced in the drift region 210 is beneficial to reducing the additional electric field of the drift region 210, and further beneficial to improving the breakdown voltage of the drift region 210, so that the high voltage resistance of the formed semiconductor structure is improved.
The following detailed description is made with reference to the accompanying drawings.
In the present embodiment, the substrate 200 has a well region 201 therein, and the drift region 210 and the body region 220 are located in the well region 201.
The barrier layer 241 is also located on the sidewall surface and the top surface of the gate structure 230.
Specifically, in this embodiment, the barrier layer 241 is doped with the repair ions. Because the barrier 241 is doped with the repair ions, the repair ions can be combined with unsaturated bonds existing in the barrier 241, and charges existing in the barrier 241 can be further reduced, so that charges induced by the drift region 210 located at the bottom of the barrier 241 are further reduced, and the high voltage resistance of the formed semiconductor structure is further improved.
The repair ions include: one or more of fluoride ion, carbon ion and nitrogen ion.
The doped layer 250 has a thickness ranging from 3 nm to 10 nm.
The significance of selecting said thickness range is: if the thickness is greater than 10 nanometers, repair ions doped in the doped layer easily affect the mobility of carriers in the drain region 210 to a certain extent, so that the working current is affected, and the performance of the formed semiconductor structure is not facilitated; if the thickness is less than 3 nm, the repair ions still cannot effectively combine dangling bonds existing at the contact interface between the blocking layer 241 and the drift region 210, and further cannot effectively reduce charges existing in the blocking layer 241, which is not beneficial to improving the high voltage resistance of the formed semiconductor structure.
The material of the barrier layer 241 includes: silicon oxide, silicon carbonitride, silicon boronitride, silicon oxycarbonitride or silicon oxynitride.
First ions are doped in the drift region 210, and the first ions are N-type ions or P-type ions; second ions are doped in the body region, and the second ions are N-type ions or P-type ions.
In this embodiment, the semiconductor structure further includes: a drain region 260 in the drift region 210 on one side of the barrier 241 and gate structure 230, and a source region 270 in the body region 220 on one side of the gate structure 230.
The drain region 260 is doped with third ions, the source region 270 is doped with fourth ions, and the conductivity types of the third ions and the fourth ions are the same.
The third ions are N-type ions or P-type ions.
The fourth ions are N-type ions or P-type ions.
The drain region 260 and the drift region 210 have the same conductivity type.
In this embodiment, the semiconductor structure further includes: lightly doped regions (not shown) in the substrate 200 at both sides of the gate structure 230.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A semiconductor structure, comprising:
the semiconductor device comprises a substrate, a first substrate and a second substrate, wherein a doped drift region and a doped body region are arranged in the substrate, and the conductivity type of the drift region is opposite to that of the body region;
a gate structure on the substrate, a portion of the gate structure being on the drift region and a portion of the gate structure being on the body region;
a blocking layer located adjacent to a portion of the drift region surface of the gate structure;
and the doped layer is positioned in the substrate or in the blocking layer, is positioned at the contact interface of the blocking layer and the drift region, and has repair ions in the doped layer.
2. The semiconductor structure of claim 1, wherein the barrier layer is further located on sidewall surfaces and a top surface of the gate structure.
3. The semiconductor structure of claim 1, wherein the barrier layer is doped with the repair ions.
4. The semiconductor structure of claim 3, in which the repair ions comprise: one or more of fluoride ion, carbon ion and nitrogen ion.
5. The semiconductor structure of claim 1, wherein the doped layer has a thickness in a range from 3 nm to 10 nm.
6. The semiconductor structure of claim 1, wherein the material of the barrier layer comprises: silicon oxide, silicon carbonitride, silicon boronitride, silicon oxycarbonitride or silicon oxynitride.
7. The semiconductor structure of claim 1, further comprising: the drain region is positioned in the drift region on one side of the barrier layer and the grid structure, and the source region is positioned in the body region on one side of the grid structure.
8. The semiconductor structure of claim 7, wherein the drain region and the drift region are of the same conductivity type.
9. The semiconductor structure of claim 1, wherein the substrate further comprises a well region, the drift region and the body region are located in the well region, and the conductivity type of the well region is the same as the conductivity type of the drift region.
10. The semiconductor structure of claim 1, further comprising: and the lightly doped regions are positioned in the substrate at two sides of the grid structure.
11. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate is internally provided with a doped drift region and a doped body region, and the conductivity type of the drift region is opposite to that of the body region;
forming a gate structure on the substrate, wherein part of the gate structure is located on the drift region, and part of the gate structure is located on the body region;
forming an initial barrier layer on the surface of the drift region, the surface of the side wall and the surface of the top of the gate structure and the surface of the body region;
and forming a doping layer in the substrate or the initial barrier layer by adopting a first ion implantation process, wherein the doping layer is positioned at the contact interface of the initial barrier layer and the drift region, and the doping layer is internally provided with repairing ions.
12. The method of forming a semiconductor structure of claim 11, wherein said first ion implantation process further dopes repair ions within said initial barrier layer.
13. The method of forming a semiconductor structure of claim 11, further comprising: after the doped layer is formed, part of the initial blocking layer is removed, the surface of the substrate is exposed, and the blocking layer is formed on the part of the surface of the drift region adjacent to the gate structure.
14. The method of forming a semiconductor structure of claim 13, wherein the barrier layer is further located on a sidewall surface and a top surface of the gate structure.
15. The method of forming a semiconductor structure of claim 13, wherein removing a portion of the initial barrier layer comprises: forming a patterned layer on the initial barrier layer surface, wherein the patterned layer exposes the initial barrier layer surface on a part of the drift region and the body region; and etching the initial barrier layer by taking the patterning layer as a mask until the surface of the substrate is exposed to form the barrier layer.
16. The method of claim 13, wherein the first ion implantation process is a single angle implantation, wherein the implantation direction is a direction from the drain region toward the source region, and wherein the implantation angle is a direction from a normal to the substrate surface.
17. The method of forming a semiconductor structure of claim 14, wherein the single angle ranges from 20 degrees to 45 degrees.
18. The method of forming a semiconductor structure of claim 13, further comprising: and forming a drain region in the drift region on one side of the barrier layer and the gate structure, and forming a source region in the body region on one side of the gate structure.
19. The method of forming a semiconductor structure of claim 18, wherein the method of forming the source and drain regions comprises: and performing a second ion implantation process on the drift region and the body region by taking the barrier layer and the gate structure as masks to form the source region and the drain region.
20. The method of forming a semiconductor structure of claim 19, wherein the parameters of the second ion implantation process comprise: the angle of implantation is in the range of 0 to 15 degrees, and the implantation dose is 1.0e14atom/cm2To 5.0e15atom/cm2The implantation energy range is 5KeV to 40 KeV.
CN202010311746.XA 2020-04-20 2020-04-20 Semiconductor structure and forming method thereof Pending CN113540241A (en)

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