CN217406186U - Delay conduction circuit for inhibiting startup peak current at negative terminal - Google Patents
Delay conduction circuit for inhibiting startup peak current at negative terminal Download PDFInfo
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- CN217406186U CN217406186U CN202220831019.0U CN202220831019U CN217406186U CN 217406186 U CN217406186 U CN 217406186U CN 202220831019 U CN202220831019 U CN 202220831019U CN 217406186 U CN217406186 U CN 217406186U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The utility model provides a time delay conduction circuit at negative terminal suppression start peak current, include: the capacitor, the voltage stabilizing diode and the MOS tube are connected in parallel, the first end of the capacitor, the first end of the voltage stabilizing diode and the source electrode of the MOS tube are grounded, and the drain electrode of the MOS tube is connected with a load; when the power supply outputs a voltage to the capacitor, the MOS tube is conducted when the voltage reaches 5V, the MOS tube is in a high-resistance conduction state at the moment, the MOS tube can enter a complete conduction state until the capacitor voltage rushes to 10V, the starting-up current peak suppression is realized by utilizing the grid low-voltage high-resistance conduction characteristic of the MOS tube, the suppression effect is good, and the use is convenient. The utility model discloses a time delay switch-on circuit realizes the start current peak through the grid low pressure high resistance switch-on characteristic that utilizes the MOS pipe and restraines respond well, convenient to use.
Description
Technical Field
The utility model relates to a start current suppression circuit technical field especially relates to a time delay conduction circuit at negative terminal suppression start peak current.
Background
With the continuous development of power supply technology, the miniaturization and high efficiency of the switching power supply are more and more emphasized. The design of the conventional switching power supply module is mainly put on a main circuit of voltage conversion and the like, and for protection circuits of reverse connection prevention, surge suppression and the like, a standard circuit form or modular equipment is mostly used, so that the defects of high power consumption, weak performance, large volume and the like exist.
In the related art, a traditional diode, a resistor and a capacitor are connected, and the diode, the resistor and the capacitor are connected in parallel to prevent the startup current surge in a conduction circuit.
However, the diode, the resistor and the capacitor are connected in parallel, so that the passing current is too small to achieve good control, and the safety of the circuit is protected; aiming at the requirement of reverse connection prevention function, the reverse connection prevention protection of the traditional diode can generate larger loss and lower efficiency.
SUMMERY OF THE UTILITY MODEL
The utility model provides a not enough to above correlation technique, the utility model provides a start current peak restraines the poor time delay conduction circuit who restraines start peak current at the negative terminal of effect.
In order to solve the above technical problem, an embodiment of the present invention provides a delay conduction circuit for suppressing start-up peak current at a negative terminal, including: the capacitor, the voltage stabilizing diode and the MOS tube are connected in parallel, the first end of the capacitor, the first end of the voltage stabilizing diode and the source electrode of the MOS tube are grounded, and the drain electrode of the MOS tube is connected with a load.
Preferably, the time-delay conducting circuit further includes a semiconductor diode, and the semiconductor diode is respectively connected in series with the second end of the capacitor, the second end of the voltage regulator diode, and the gate of the MOS transistor.
Preferably, the delay conducting circuit further includes a first resistor, and the first resistor is respectively connected in series with the second end of the capacitor, the second end of the zener diode, and the gate of the MOS transistor.
Preferably, the semiconductor diode is connected in series with the first resistor.
Preferably, the delay conducting circuit further includes a second resistor, the second resistor is connected in parallel with the capacitor, the zener diode and the MOS transistor, respectively, a first end of the second resistor is grounded, and a second end of the second resistor is connected in series with the first resistor.
Preferably, the model of the MOS transistor comprises one of RU6080L and PTD20N 06.
Preferably, the semiconductor diode is a silicon diode.
Compared with the prior art, the utility model discloses a connect in parallel each other between with electric capacity, zener diode and the MOS pipe, the first end of electric capacity, zener diode's first end and the source electrode ground connection of MOS pipe, the drain electrode of MOS pipe is connected with the load; when the power supply outputs the capacitor, when the voltage reaches 5V, the MOS tube is conducted, and at the moment, the MOS tube is in a high-resistance conduction state, and the MOS tube can enter a complete conduction state until the capacitor voltage rushes to 10V, so that the starting current peak suppression is realized by utilizing the grid low-voltage high-resistance conduction characteristic of the MOS tube, the suppression effect is good, and the use is convenient.
View: the present invention will be described in detail with reference to the accompanying drawings. The foregoing and other aspects of the invention will become more apparent and will be better understood from the following detailed description taken in conjunction with the accompanying drawings. In the drawings:
drawings
Fig. 1 is a circuit diagram of the delay conduction circuit with the negative terminal suppressing the power-on peak current.
Detailed Description
The following describes in detail embodiments of the present invention with reference to the drawings.
The embodiments/examples set forth herein are specific embodiments of the present invention and are presented for illustrative purposes only, and are not intended to be construed as limitations on the scope of the invention. In addition to the embodiments described herein, those skilled in the art will be able to employ other technical solutions which are obvious based on the disclosure of the claims and the specification of the present application, and these technical solutions include those which make any obvious replacement or modification of the embodiments described herein, and all of which are within the scope of the present invention.
The utility model provides a time delay conduction circuit 100 of starting peak current is restrained at the negative terminal.
Referring to fig. 1, fig. 1 is a circuit diagram of a delay-on circuit for suppressing the power-on spike current by the negative terminal of the present invention.
Specifically, the delay-on circuit 100 for suppressing the power-on spike current at the negative terminal includes: the power supply comprises a capacitor C1, a voltage stabilizing diode ZN1 and an MOS tube Q1, wherein the capacitor C1, the voltage stabilizing diode ZN1 and the MOS tube Q1 are connected in parallel, a first end of the capacitor C1, a first end of the voltage stabilizing diode ZN1 and a source electrode of the MOS tube Q1 are grounded (a power supply GND), and a drain electrode of the MOS tube Q1 is connected with a load.
The second end of the capacitor C1 is connected with the positive pole of the power supply DC, the second end of the zener diode ZN1 is connected with the positive pole of the power supply DC, and the grid of the MOS transistor Q1 is connected with the positive pole of the power supply DC. When the power supply outputs to the capacitor C1, the capacitor C1 charges, when the voltage reaches 5V, the MOS transistor is conducted, at the moment, the MOS transistor is in a high-resistance conducting state, until the voltage of the capacitor C1 rushes to 10V, the MOS transistor Q1 can enter a complete conducting state, the starting-up current peak suppression is realized by utilizing the low-voltage high-resistance conducting characteristic of the grid electrode of the MOS transistor Q1, and the suppression effect is good.
In this embodiment, the time-delay conducting circuit 100 further includes a semiconductor diode D1, and the semiconductor diode D1 is connected in series with the second terminal of the capacitor C1, the second terminal of the zener diode ZN1, and the gate of the MOS transistor Q1, respectively. A first terminal of the semiconductor diode D1 is connected between the DC power source DC and the load DC, and a second terminal of the semiconductor diode D1 is connected in series with a second terminal of the capacitor C1 and a second terminal of the first resistor R1, respectively. The direct current power supply anode and the load anode are connected with a semiconductor diode D1, and the first end of the semiconductor diode D1 is connected between the direct current power supply DC anode and the load DC anode. The forward passing current is charged to the capacitor C1 through the semiconductor diode D1, the current of the direct current power supply DC is conducted in a single direction through the semiconductor diode D1, the positive electrode of the current is conducted, the current is not conducted in the reverse direction, and the capacitor C1 is prevented from discharging to conduct reverse charging so as to avoid affecting the circuit safety.
In this embodiment, the time delay conducting circuit 100 further includes a first resistor R1, and the first resistor R1 is respectively connected in series with the second terminal of the capacitor C1, the second terminal of the zener diode ZN1, and the gate of the MOS transistor Q1.
In the present embodiment, the semiconductor diode D1 is connected in series with the first resistor R1.
Specifically, the power DC positive pole and the load DC positive pole are connected to the semiconductor diode D1, the first end of the semiconductor diode D1 is connected between the DC power DC positive pole and the load DC positive pole, the first resistor R1 is connected to the gates of the semiconductor diode D1 and the MOS transistor, and voltage division is performed through the first resistor R1, so that the passing voltage is prevented from being too large, and the time delay conducting circuit 100 is protected.
In this embodiment, the time delay conducting circuit 100 further includes a second resistor R2, the second resistor R2 is respectively connected in parallel with the capacitor C1, the zener diode ZN1 and the MOS transistor Q1, a first end of the second resistor R2 is grounded, and a second end of the second resistor R2 is connected in series with the first resistor R1.
Specifically, through zener diode ZN1 and the common steady voltage of second resistance R2, reach certain degree when reverse voltage, ordinary diode can be reverse breakdown, and zener diode ZN1 then can be through letting the reverse flow of heavy current, prevents that voltage from continuing to rise, and the circuit steady voltage is effectual, and the security is high. The MOS transistor Q1 realizes the suppression of the peak of the power-on current. The capacitor C1, the zener diode ZN1, the second resistor R2 and the MOS tube Q1 are connected in parallel, the first end of the capacitor C1, the first end of the zener diode ZN1, the first end of the second resistor R2 and the source of the MOS tube Q1 are respectively connected to a ground GND of a power supply, and the drain of the MOS tube Q1 is connected to a ground GND of a load. The grounding can protect the safety of the circuit.
Specifically, the first end of the capacitor C1, the first end of the zener diode ZN1, the first end of the second resistor R2, and the source of the MOS transistor Q1 are respectively connected to a power ground, and the drain of the MOS transistor Q1 is connected to a load ground, so that a circuit protection effect is facilitated.
Specifically, the power supply is output to the capacitor C1, when the voltage reaches 5V, the MOS transistor Q1 is turned on, and at this time, the high-resistance on state is achieved, and until the voltage of the capacitor C1 rushes to 10V, the MOS transistor Q1 can enter the complete on state, so that the start-up current spike suppression is achieved by utilizing the low-voltage high-resistance on characteristic of the gate of the MOS transistor Q1, the suppression effect is good, and the use is convenient.
In this embodiment, the MOS transistor Q1 includes RU6080L and PTD20N 06. The suppression effect on the startup current peak of the time delay conduction circuit is good.
In this embodiment, the semiconductor diode D1 is a silicon diode or a germanium diode, and the diode allows current to pass through in a single direction (referred to as forward bias) and blocks (referred to as reverse bias) reverse current, that is, the diode allows current flowing from the DC positive electrode of the DC power supply to pass through.
Compared with the prior art, the utility model discloses through with mutually connecting in parallel between electric capacity, zener diode and the MOS pipe, the first end of electric capacity, zener diode's first end and the source electrode ground connection of MOS pipe, the drain electrode of MOS pipe is connected with the load; when the power supply outputs the capacitor, when the voltage reaches 5V, the MOS tube is conducted, and at the moment, the MOS tube is in a high-resistance conduction state, and the MOS tube can enter a complete conduction state until the capacitor voltage rushes to 10V, so that the starting current peak suppression is realized by utilizing the grid low-voltage high-resistance conduction characteristic of the MOS tube, the suppression effect is good, and the use is convenient.
Claims (7)
1. A turn-on delay circuit for suppressing turn-on spike current at the negative terminal, comprising: the capacitor, the voltage stabilizing diode and the MOS tube are connected in parallel, the first end of the capacitor, the first end of the voltage stabilizing diode and the source electrode of the MOS tube are grounded, and the drain electrode of the MOS tube is connected with a load.
2. The delay-turn-on circuit for suppressing turn-on spike current at a negative terminal of claim 1, further comprising semiconductor diodes respectively connected in series with the second terminal of the capacitor, the second terminal of the zener diode, and the gate of the MOS transistor.
3. The delay-turn-on circuit for suppressing turn-on spike current at a negative terminal of claim 2, further comprising a first resistor connected in series with the second terminal of the capacitor, the second terminal of the zener diode, and the gate of the MOS transistor, respectively.
4. The negative side turn-on spike current suppression delayed turn-on circuit of claim 3, wherein said semiconductor diode is in series with said first resistor.
5. The negative side turn-on spike current suppression delayed turn-on circuit as claimed in claim 4, further comprising a second resistor, said second resistor being connected in parallel with said capacitor, said zener diode and said MOS transistor, respectively, a first end of said second resistor being connected to ground, a second end of said second resistor being connected in series with said first resistor.
6. The delay turn-on circuit for suppressing turn-on spike current at a negative terminal of claim 1, wherein the MOS transistor is of a type including any one of RU6080L and PTD20N 06.
7. The delay-turn-on circuit for suppressing turn-on spike current at a negative terminal of claim 2, wherein the semiconductor diode is a silicon diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220831019.0U CN217406186U (en) | 2022-04-11 | 2022-04-11 | Delay conduction circuit for inhibiting startup peak current at negative terminal |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220831019.0U CN217406186U (en) | 2022-04-11 | 2022-04-11 | Delay conduction circuit for inhibiting startup peak current at negative terminal |
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| CN217406186U true CN217406186U (en) | 2022-09-09 |
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| CN202220831019.0U Active CN217406186U (en) | 2022-04-11 | 2022-04-11 | Delay conduction circuit for inhibiting startup peak current at negative terminal |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116155113A (en) * | 2023-04-14 | 2023-05-23 | 陕西中科天地航空模块有限公司 | ZVS control type module power supply for electromagnetic interference suppression |
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2022
- 2022-04-11 CN CN202220831019.0U patent/CN217406186U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116155113A (en) * | 2023-04-14 | 2023-05-23 | 陕西中科天地航空模块有限公司 | ZVS control type module power supply for electromagnetic interference suppression |
| CN116155113B (en) * | 2023-04-14 | 2024-04-30 | 陕西中科天地航空模块有限公司 | ZVS control type module power supply for electromagnetic interference suppression |
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