CN214626959U

CN214626959U - Negative-pressure level conversion unit

Info

Publication number: CN214626959U
Application number: CN202120358210.3U
Authority: CN
Inventors: 穆拉利·南迪加姆; 陈杨健; 解鹏
Original assignee: Nanjing Weipaishi Semiconductor Technology Co ltd
Current assignee: Nanjing Weipaishi Semiconductor Technology Co ltd
Priority date: 2021-02-07
Filing date: 2021-02-07
Publication date: 2021-11-05
Anticipated expiration: 2031-02-07

Abstract

The utility model discloses a negative voltage level transition unit, including bootstrap circuit, bootstrap circuit includes transistor M4, M5, M6 and M7, and voltage input signal EN links to each other with the input of inverter INV, transistor M4, the base of M6 respectively, the output of inverter INV passes through electric capacity C1 and links to each other and intersect at N point with the emitter of transistor M4, the collector of transistor M5, the emitter of transistor M6 connects voltage VDD, the collector of transistor M6 links to each other with the emitter of transistor M7, the collector of transistor M7 links to each other with the collector of transistor M4, the base of transistor M5, the base of transistor M5 and the collector of transistor M7 intersect at node EN _ BS and link to each other with output node EN _ NEG through electric capacity C2. The negative voltage level conversion unit can realize that the circuit does not generate series current when switching the working state and does not generate high transient current on a negative voltage power supply.

Description

Negative-pressure level conversion unit

Technical Field

The utility model relates to a negative pressure level shift unit belongs to level shift circuit technical field.

Background

The negative voltage level conversion unit is a circuit for converting a logic level signal into a negative voltage signal, is a basic circuit widely applied to a nonvolatile memory, and mainly provides positive voltage and negative voltage required by the nonvolatile memory during read and write operations. In the field of application with high isolation requirements, a level conversion unit from positive voltage to negative voltage is a common circuit for controlling a MOS switch circuit.

The traditional level conversion unit circuit adopts two cascode circuits, and the grid electrodes are driven by the same power supply; when the working state is switched, high series current can be generated, and high transient current can be generated on the negative voltage power supply, so that the design of the negative voltage power supply is very complicated, and meanwhile, a large decoupling capacitor is required to be used for providing the transient current.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to overcome the problem that exists among the prior art, provide a negative pressure level transition unit, can realize that the circuit does not produce the series current when switching operating condition, can not produce very high transient current on negative voltage power supply.

In order to solve the above technical problem, the utility model discloses a negative voltage level shift unit, including bootstrap circuit, bootstrap circuit includes transistor M4, M5, M6 and M7, and voltage input signal EN links to each other with the input of inverter INV, the base of transistor M4, M6 respectively, the output of inverter INV passes through electric capacity C1 and links to each other and meet at N point with the emitter of transistor M4, the collector of transistor M5, the emitter of transistor M6 connects voltage VDD, the collector of transistor M6 links to each other with the emitter of transistor M7, the collector of transistor M7 links to each other with the collector of transistor M4, the base of transistor M5, the base of transistor M5 meets with the collector of transistor M7 at node EN _ BS and links to each other with output node EN _ NEG through electric capacity C2.

Further, the bootstrap circuit further includes a capacitor C3, and the capacitor C3 is connected in parallel between the collector and the emitter of the transistor M5.

Further, a voltage latch circuit is included, the voltage latch circuit includes transistors M0, M1, M2, M3, M8 and M9, the emitter of the transistor M3 is connected to the voltage VDD, the collector of the transistor M3 is connected to the collector of the transistor M0, the base of the transistor M3 is connected to the voltage input signal EN, the base of the transistor M0 is grounded, the emitter of the transistor M0 is connected to the collector of the transistor M1 and meets the output node EN _ NEG, the emitter of the transistor M1 is connected to the output negative terminal, the base of the transistor M2 is connected to the output node EN _ NEG, the collector of the transistor M2 is connected to the emitter of the transistor M9 and meets the point K and is connected to the base of the transistor M1, the emitter of the transistor M2 is connected to the emitter of the transistor M1 and to NVDD, the base of the transistor M9 is connected to the emitter of the transistor M8 and to the point N of the bootstrap circuit, the emitter of the transistor M8 is grounded, and the collector of the transistor M8 is connected with the collector of the transistor M9.

Further, the transistors M3, M6, M7 and M8 are PNP transistors, and the transistors M0, M1, M2, M4, M5 and M9 are NPN transistors.

The utility model has the advantages that: 1. the bootstrap circuit is used for providing charging and discharging current of the 'EN _ NEG' node, and is used for determining the potential of the 'EN _ NEG' node. The latch circuit is used for maintaining the logic level (0 or NVDD) of the 'EN _ NEG' node, and the bootstrap circuit and the latch circuit are matched with each other, so that the circuit does not generate series current when in a switching working state, and does not generate high transient current on a negative voltage power supply.

2. When the voltage input signal EN rises from 0 to VDD, the inverter INV is inverted from VDD to 0, the transistors M6 and M7 are turned off, the transistor M4 is turned on, since the charge of the capacitor C1 remains substantially unchanged and M4 is turned on, N = EN _ BS = -VDD, the transistor M5 is turned off, the transistors M8 and M9 are turned on, the voltage of the node K rises, the transistors M3 and M0 are turned off, the transistor M1 is turned on, the node EN _ NEG is clamped to NVDD, and the capacitor C2 is charged to the voltage VDD across the two terminals.

3. When the voltage input signal EN falls from VDD to 0, the inverter INV is inverted from 0 to VDD, the transistors M6, M7, M3 and M0 are turned on, the potentials of the nodes EN _ NEG and EN _ BS rise, the voltage of the output node EN _ NEG rises to enable M2 to be turned on, at this time, the voltage at the point K is NVDD, the transistor M1 is turned off, the node EN _ BS rises to enable the transistor M5 to be turned on, at this time, N =0, the transistors M6 and M7 are turned on to enable the voltage of the node EN _ BS to rise to VDD, when the voltage of the output node EN _ NEG rises to-Vth, the charging paths of M3 and M0 are turned off, and the charge of the capacitor C2 is basically maintained unchanged. N =0, transistor M4 is off, and capacitor C1 is charged to VDD across.

Drawings

FIG. 1 is a schematic circuit diagram of the negative voltage level shifting unit of the present invention,

FIG. 2 is a schematic diagram of the operation principle of the negative voltage level shift unit of the present invention during discharging,

FIG. 3 is a schematic diagram of the operation principle of the output node of the negative voltage level shifting unit of the present invention during charging,

fig. 4 is a voltage waveform diagram of the internal node of the negative voltage level conversion unit of the present invention.

Detailed Description

The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic drawings and illustrate the basic structure of the present invention only in a schematic manner, and thus show only the components related to the present invention.

As shown in fig. 1, the negative voltage level converting unit of the present invention includes a bootstrap circuit and a voltage latch circuit, the bootstrap circuit includes transistors M4, M5, M6 and M7, a voltage input signal EN is respectively connected to an input terminal of the inverter INV and bases of the transistors M4 and M6, an output terminal of the inverter INV is respectively connected to an emitter of the transistor M4 and a collector of the transistor M5 through a capacitor C1 and meets at a point N, an emitter of the transistor M6 is connected to the voltage VDD, a collector of the transistor M6 is connected to an emitter of the transistor M7, a collector of the transistor M7 is respectively connected to a collector of the transistor M4 and a base of the transistor M5, and a base of the transistor M5 and a collector of the transistor M7 meet at a node EN _ BS and are connected to an output node EN _ NEG through a capacitor C2. A capacitor C3 is connected between the collector and the emitter of the transistor M5.

The voltage latch circuit includes transistors M0, M1, M2, m3, M8 and M9, the emitter of the transistor M3 is connected to the voltage VDD, the collector of the transistor M3 is connected to the collector of the transistor M0, the base of the transistor M3 is connected to the voltage input signal EN, the base of the transistor M0 is connected to ground, the emitter of the transistor M0 is connected to the collector of the transistor M1 and meets at the output node EN _ NEG, the emitter of the transistor M1 is connected to the output negative terminal, the base of the transistor M2 is connected to the output node EN _ NEG, the collector of the transistor M2 is connected to the emitter of the transistor M9 and meets at point K and is connected to the base of the transistor M1, the emitter of the transistor M2 is connected to the emitter of the transistor M1 and is connected to NVDD, the base of the transistor M9 is connected to the base of the transistor M8 and is connected to point N in the bootstrap circuit, the emitter of the transistor M8 is connected to ground, and the collector of the transistor M8 is connected to the collector of the transistor M9.

The transistors M3, M6, M7, and M8 are PNP transistors, and the transistors M0, M1, M2, M4, M5, and M9 are NPN transistors.

The bootstrap circuit is used for providing charge-discharge current of an 'EN _ NEG' node, the latch circuit is used for maintaining a logic level (0 or NVDD) of the 'EN _ NEG' node, and the bootstrap circuit and the latch circuit are matched with each other, so that the circuit does not generate series current when in a switching working state, and does not generate high transient current on a negative voltage power supply.

As shown in fig. 2, when the voltage input signal EN rises from 0 to VDD, the inverter INV is inverted from VDD to 0, the transistors M6 and M7 are turned off, the transistor M4 is turned on, N = EN _ BS = -VDD since the charge of the capacitor C1 remains substantially unchanged and M4 is turned on, the transistor M5 is turned off, the transistors M8 and M9 are turned on, the voltage of the node K rises, the transistors M3 and M0 are turned off, the transistor M1 is turned on, the node EN _ NEG is clamped to NVDD, and the capacitor C2 is charged to have a voltage of VDD at both ends.

As shown in fig. 3, when the voltage input signal EN falls from VDD to 0, the inverter INV is inverted from 0 to VDD, the transistors M6, M7, M3 and M0 are turned on, the potentials of the nodes EN _ NEG and EN _ BS rise, the output node EN _ NEG rises to make M2 turn on, at this time, the voltage at the point K is NVDD, the transistor M1 is turned off, the node EN _ BS rises to make the transistor M5 turn on, at this time, N =0, the transistors M6 and M7 turn on to make the voltage of the node EN _ BS rise to VDD, when the voltage of the output node EN _ NEG rises to-Vth, the charging paths of M3 and M0 are turned off, and the charge of the capacitor C2 is substantially maintained. N =0, transistor M4 is off, and capacitor C1 is charged to VDD across.

Fig. 4 is a graph of internal node voltage waveforms of the negative voltage level conversion unit, where EN = VDD, N = -VDD, EN _ BS = -VDD, and EN _ NEG = NVDD. EN =0, N =0, EN _ BS = VDD, EN _ NEG = -Vth.

In light of the foregoing, it will be apparent to those skilled in the art from this disclosure that various changes and modifications can be made without departing from the spirit and scope of the invention. The technical scope of the present invention is not limited to the content of the specification, and must be determined according to the scope of the claims.

Claims

1. A negative voltage level conversion unit comprises a bootstrap circuit, and is characterized in that: the bootstrap circuit comprises transistors M4, M5, M6 and M7, a voltage input signal EN is respectively connected with an input end of an inverter INV and bases of transistors M4 and M6, an output end of the inverter INV is respectively connected with an emitter of a transistor M4 and a collector of a transistor M5 through a capacitor C1 and meets at a point N, an emitter of a transistor M6 is connected with a voltage VDD, a collector of the transistor M6 is connected with an emitter of a transistor M7, a collector of the transistor M7 is respectively connected with a collector of a transistor M4 and a base of a transistor M5, a base of the transistor M5 and a collector of a transistor M7 meet at a node EN _ BS and are connected with an output node EN _ NEG through a capacitor C2.

2. The negative voltage level shifting unit of claim 1, wherein: the bootstrap circuit also includes a capacitor C3, the capacitor C3 is connected in parallel between the collector and the emitter of the transistor M5.

3. The negative voltage level shifting unit of claim 1, wherein: further comprising a voltage latch circuit comprising transistors M0, M1, M2, M3, M8 and M9, wherein the emitter of transistor M3 is coupled to the voltage VDD, the collector of transistor M3 is coupled to the collector of transistor M0, the base of transistor M3 is coupled to the voltage input signal EN, the base of transistor M0 is coupled to ground, the emitter of transistor M0 is coupled to the collector of transistor M1 and to the output node EN _ NEG, the emitter of transistor M1 is coupled to the output negative terminal, the base of transistor M2 is coupled to the output node EN _ NEG, the collector of transistor M2 is coupled to the emitter of transistor M9 and to the base of transistor M1, the emitter of transistor M2 is coupled to the emitter of transistor M1 and to NVDD, the base of transistor M9 is coupled to the base of transistor M8 and to N in the circuit, the emitter of the transistor M8 is grounded, and the collector of the transistor M8 is connected with the collector of the transistor M9.

4. The negative voltage level shifting unit of claim 1, 2 or 3, wherein: the transistors M3, M6, M7 and M8 are PNP type transistors, and the transistors M0, M1, M2, M4, M5 and M9 are NPN type transistors.