CN210225367U

CN210225367U - Inverter with latch function

Info

Publication number: CN210225367U
Application number: CN201921598284.3U
Authority: CN
Inventors: Zekun Zhou; 周泽坤; Zhengyang Jin; 金正扬; Qi Deng; 邓琪
Original assignee: Chengdu Silicon Energy Technology Co Ltd
Current assignee: Chengdu Silicon Energy Technology Co Ltd
Priority date: 2019-09-24
Filing date: 2019-09-24
Publication date: 2020-03-31
Anticipated expiration: 2029-09-24

Abstract

The phase inverter with the latching function comprises an inverting unit and a latching unit, wherein the inverting unit comprises an input end, an output end, a power supply end and a grounding end, the input end of the inverting unit is connected with an input signal of the phase inverter, the power supply end of the inverting unit is connected with a power supply voltage, and the output end of the inverting unit outputs an output signal of the phase inverter; the latch unit comprises a second NMOS tube, the grid electrode of the second NMOS tube is connected with the control signal, the drain electrode of the second NMOS tube is connected with the grounding end of the phase inversion unit, and the source electrode of the second NMOS tube is grounded. When the control signal is at high level, the inverter is used as a common inverter, and when the control signal is at low level, the output node of the inverter is floated, and the inverter realizes the latch function. The utility model provides a take phase inverter of latch function only utilizes a transistor that connects between the earthing terminal of inverting unit and ground level to realize latching the function, compares the traditional phase inverter that uses positive feedback structure to realize latching, has reduced transistor quantity, has saved the area.

Description

Inverter with latch function

Technical Field

The utility model belongs to the technical field of the analog integrated circuit, concretely relates to phase inverter of function is latched in area.

Background

With the rapid development of integrated circuit process technology, the integrated circuit industry has entered the nanometer era, the scale of the circuit has been continuously increased, on the contrary, the area occupied by the chip is smaller and smaller, and the reduction of the area of the circuit has become an important trend for the development of the integrated circuit industry.

Latches and inverters are basic combinational logic circuits important in digital design, and are widely used in functional modules such as counter circuits and parity determination circuits. The inverter has the function of realizing the inversion of an output level and an input level, and when the input level is high, a low level is output; when the input level is low, a high level is output. The function of the latch is to realize a signal latch function in digital logic, and when the input levels of the latch are all low levels, the latch is output. In order to realize the inverter with the latch function, a latch is required in the conventional circuit scheme, and the latch function is realized by the conventional latch through positive feedback, so that the number of used transistors is large, and the required area is large.

SUMMERY OF THE UTILITY MODEL

The phase inverter to traditional area latch function utilizes positive feedback structure to realize the more problem of the needs transistor quantity that the latch function exists, the utility model provides a phase inverter of function is latched in area only with only a transistor with the output point superficial empty can realize latching, the transistor quantity that has significantly reduced.

The technical scheme of the utility model is that:

the phase inverter with the latching function comprises an inverting unit and a latching unit, wherein the inverting unit comprises an input end, an output end, a power supply end and a grounding end, the input end of the inverting unit is connected with an input signal of the phase inverter, the power supply end of the inverting unit is connected with a power supply voltage, and the output end of the inverting unit outputs an output signal of the phase inverter;

the latch unit comprises a second NMOS tube, the grid electrode of the second NMOS tube is connected with a control signal, the drain electrode of the second NMOS tube is connected with the grounding end of the phase inversion unit, and the source electrode of the second NMOS tube is grounded.

Specifically, the inverting unit includes a first NMOS transistor and a first PMOS transistor, a gate of the first PMOS transistor is connected to a gate of the first NMOS transistor and serves as an input terminal of the inverting unit, a source of the first PMOS transistor serves as a power supply terminal of the inverting unit, and a drain of the first PMOS transistor is connected to a drain of the first NMOS transistor and serves as an output terminal of the inverting unit; and the source electrode of the first NMOS tube is used as the grounding end of the inverting unit.

The utility model has the advantages that: the utility model provides a take phase inverter of latch function only utilizes a transistor that connects between the earthing terminal of inverting unit and ground level to realize latching the function, compares the traditional phase inverter that uses positive feedback structure to realize latching, has reduced transistor quantity, has saved the area.

Drawings

Fig. 1 is an implementation form of a phase inverter with a latch function according to the present invention in an embodiment.

Detailed Description

The invention will be further elucidated with reference to the following figures and specific embodiments:

the utility model provides a take phase inverter of latching function, including inverting unit and latching unit, inverting unit is used for realizing inverting function, can adopt traditional phase inverter structure, a realization form of inverting unit is shown to be given as figure 1, including first NMOS pipe MN1 and first PMOS pipe MP1, the grid of first PMOS pipe MP1 is connected the grid of first NMOS pipe MN1 and is connected the input signal IN of phase inverter as inverting unit's input, its source is connected supply voltage VDD as inverting unit's power end, its drain electrode is connected the drain electrode of first NMOS pipe MN1 and is output signal OUT of phase inverter as inverting unit's output; the source of the first NMOS transistor MN1 serves as the ground terminal of the inverter unit.

The latch unit is used for realizing latching the function, the utility model provides an utilize second NMOS pipe MN2 to connect between the earthing terminal and the ground level of inverting unit, realize floating the output point of phase inverter under control signal EN's control for the output point electric capacity of phase inverter does not charge and discharge, thereby realizes latching the function, as shown in FIG. 1, control signal EN is connected to the grid of second NMOS pipe MN2, and the earthing terminal of inverting unit is connected to its drain electrode, its source ground.

The working principle of the embodiment is as follows:

when the control signal EN is at a high level, the second NMOS transistor MN2 of the latch unit is turned on, and the source potential of the first NMOS transistor MN1 of the inverter unit is pulled down to a low level. In this case, the inverter with latch function in the present embodiment is used as a general inverter. When the input signal IN is at a low level, the first PMOS transistor MP1 of the inverting unit is turned on, the first NMOS transistor MN1 is turned off, and the output signal OUT of the inverter is at a high level; when the input signal IN is at a high level, the first PMOS transistor MP1 IN the inverting unit is turned off, the first NMOS transistor MN1 is turned on, and the output signal OUT of the inverter is at a low level.

When the control signal EN is low, the second NMOS transistor MN2 in the latch unit is turned off. At this time, the source potential of the first NMOS transistor MN1 in the inverting unit is in a floating state, so that the output node of the inverter is floating, and the capacitor at the output node of the inverter is not charged or discharged, thereby realizing latching. When the input signal IN is at a low level, the first PMOS transistor MP1 of the inverting unit is turned on, the first NMOS transistor MN1 is turned off, and the output signal OUT of the inverter is at a high level; when the input signal IN is at a high level, the first PMOS transistor MP1 of the inverter unit is turned off, the first NMOS transistor MN1 is turned on, and the output signal OUT of the inverter is IN a latched state.

In the inverter with latch function in the embodiment, the inverter with latch function is realized by only using 3 transistors, and compared with the traditional inverter for realizing latch by using a positive feedback structure, the inverter with latch function has the advantages that the number of transistors is reduced, and the area is saved.

It is worth explaining that the utility model provides a take phase inverter of latch function utilizes a transistor that is controlled by control signal EN signal to connect between the earthing terminal of opposition unit and ground level, realizes the latch function through floating the output node of phase inverter, though the opposition unit in this embodiment realizes the opposition function with first NMOS pipe MN1 and first PMOS pipe MP1, but other opposition unit structures that can realize the opposition function equally are also applicable to the utility model discloses.

The above embodiments are only used to help understand the basic principle and the core idea of the present invention, and the modifications to the specific implementation mode on the basic principle and the core idea of the present invention should all belong to the scope of the present invention.

Claims

1. The phase inverter with the latching function comprises an inverting unit and a latching unit, wherein the inverting unit comprises an input end, an output end, a power supply end and a grounding end, the input end of the inverting unit is connected with an input signal of the phase inverter, the power supply end of the inverting unit is connected with a power supply voltage, and the output end of the inverting unit outputs an output signal of the phase inverter;

2. The inverter with latch function according to claim 1, wherein the inverting unit comprises a first NMOS transistor and a first PMOS transistor, a gate of the first PMOS transistor is connected to a gate of the first NMOS transistor and serves as an input terminal of the inverting unit, a source of the first PMOS transistor serves as a power supply terminal of the inverting unit, and a drain of the first PMOS transistor is connected to a drain of the first NMOS transistor and serves as an output terminal of the inverting unit; and the source electrode of the first NMOS tube is used as the grounding end of the inverting unit.