CN216086618U - Level conversion circuit - Google Patents

Abstract

The application relates to a level conversion circuit, which is characterized in that a low-voltage domain inverter circuit is arranged, so that an input low-voltage domain square wave voltage signal is converted into an inverted low-voltage domain square wave voltage signal, the low-voltage domain square wave voltage signal and an inverted square low-voltage domain wave voltage signal are jointly input into a high-voltage domain conversion circuit, the low-voltage domain square wave voltage signal and the inverted low-voltage domain square wave voltage signal are complementary in waveform, the high-voltage domain conversion circuit can form a stable load, and the low-voltage domain square wave voltage signal is converted into a high-voltage domain square wave voltage signal to be output. When the voltage signal is periodically and rapidly changed, the level conversion circuit has high level conversion speed and high response speed of the output signal.

Description

Level conversion circuit

Technical Field

The present application relates to the field of electronic circuits, and more particularly, to a level shifter circuit.

Background

In the traditional design of a level conversion circuit for converting a low level into a high level of a square wave voltage signal, the design of the level conversion circuit is generally simpler, so that the performance is not enough, and particularly, when the voltage signal is periodically and rapidly changed, the response speed of an output signal is slow.

SUMMERY OF THE UTILITY MODEL

Therefore, it is necessary to provide a level shift circuit for solving the problem of slow response speed of the output signal when the voltage signal of the conventional level shift circuit periodically changes fast.

The application provides a level shift circuit, includes:

the low-voltage signal input end is used for inputting a low-voltage-domain square wave voltage signal;

the low-voltage domain inverter circuit is used for inverting the low-voltage domain square wave voltage signal;

the low-voltage source is electrically connected with the low-voltage domain inverter circuit and used for providing electric energy for the low-voltage domain inverter circuit;

the high-voltage domain conversion circuit is used for converting the low-voltage domain square wave voltage signal after phase inversion into a square wave voltage signal of a high-voltage domain; the high-voltage domain conversion circuit is also electrically connected with the low-voltage signal input end

The high-voltage source is electrically connected with the high-voltage domain conversion circuit and used for providing electric energy for the high-voltage domain conversion circuit; the output voltage value of the low-voltage source is smaller than that of the high-voltage source;

the high-voltage signal output end is used for outputting a square wave voltage signal of the high-voltage domain; and the effective voltage value of the low-voltage domain square wave voltage signal is smaller than that of the high-voltage domain square wave voltage signal.

Further, the low-voltage domain inverter circuit includes:

the source electrode of the first PMOS tube is electrically connected with the low-voltage source;

the source electrode of the first NMOS tube is grounded, the drain electrode of the first NMOS tube is electrically connected with the drain electrode of the first PMOS tube, and the grid electrode of the first NMOS tube is electrically connected with the grid electrode of the first PMOS tube;

the low-voltage signal input end is electrically connected with a connection link between the grid electrode of the first NMOS tube and the grid electrode of the first PMOS tube.

Further, the high voltage domain conversion circuit comprises:

the source electrode of the second NMOS tube is grounded, and the grid electrode of the second NMOS tube is electrically connected with a connecting link between the drain electrode of the first NMOS tube and the drain electrode of the first PMOS tube;

the source electrode of the third NMOS tube is grounded, and the grid electrode of the third NMOS tube is electrically connected with the connecting link between the grid electrode of the first NMOS tube and the low-voltage signal input end;

the drain electrode of the second PMOS tube is electrically connected with the drain electrode of the second NMOS tube; the grid electrode of the second PMOS tube is electrically connected with the drain electrode of the third NMOS tube;

the drain electrode of the third PMOS tube is electrically connected with the drain electrode of the third NMOS tube; the grid electrode of the third PMOS tube is electrically connected with the drain electrode of the second NMOS tube;

the source electrode of the second PMOS tube is electrically connected with the source electrode of the third PMOS tube;

the high-voltage source is electrically connected to a connection link between the source electrode of the second PMOS tube and the source electrode of the third PMOS tube.

Further, the high voltage signal output terminal includes:

the first output end is electrically connected with a connecting link between the drain electrode of the second PMOS tube and the drain electrode of the second NMOS tube;

and the second output end is electrically connected with a connection link between the drain electrode of the third PMOS tube and the drain electrode of the third NMOS tube.

Further, the voltage signal polarities of the low-voltage signal input end and the first output end are the same, and the voltage signal polarities of the low-voltage signal input end and the second output end are opposite.

Further, the threshold voltage of the first PMOS transistor is greater than 0 and smaller than the output voltage value of the low-voltage source, and the threshold voltage of the first NMOS transistor is greater than 0 and smaller than the output voltage value of the low-voltage source.

Further, the threshold voltage of the second NMOS transistor is greater than the threshold voltage of the first NMOS transistor and less than the output voltage value of the high voltage source, and the threshold voltage of the second NMOS transistor is equal to the threshold voltage of the third NMOS transistor.

Further, the threshold voltage of the second PMOS transistor is greater than the threshold voltage of the first PMOS transistor and less than the output voltage value of the high-voltage source, and the threshold voltage of the second PMOS transistor is equal to the threshold voltage of the third PMOS transistor.

Further, the level shift circuit further includes:

a gate of the fourth NMOS transistor is electrically connected to the low-voltage signal input terminal, a drain of the fourth NMOS transistor is electrically connected to the second PMOS transistor, and a source of the fourth NMOS transistor is electrically connected to a connection link between the drain of the second PMOS transistor and the drain of the second NMOS transistor;

the grid electrode of the fifth NMOS tube is electrically connected with the second NMOS tube, the drain electrode of the fifth NMOS tube is electrically connected with the third PMOS tube, and the source electrode of the fifth NMOS tube is electrically connected with a connecting link between the drain electrode of the third PMOS tube and the drain electrode of the third NMOS tube.

Further, the threshold voltage of the first NMOS transistor is equal to the threshold voltage of the fourth NMOS transistor and is equal to the threshold voltage of the fifth NMOS transistor.

The application relates to a level conversion circuit, which is characterized in that a low-voltage domain inverter circuit is arranged, so that an input low-voltage domain square wave voltage signal is converted into an inverted low-voltage domain square wave voltage signal, the low-voltage domain square wave voltage signal and an inverted square low-voltage domain wave voltage signal are jointly input into a high-voltage domain conversion circuit, the low-voltage domain square wave voltage signal and the inverted low-voltage domain square wave voltage signal are complementary in waveform, the high-voltage domain conversion circuit can form a stable load, and the low-voltage domain square wave voltage signal is converted into a high-voltage domain square wave voltage signal to be output. When the voltage signal is periodically and rapidly changed, the level conversion circuit has high level conversion speed and high response speed of the output signal.

Drawings

Fig. 1 is a schematic structural diagram of a level shift circuit according to an embodiment of the present disclosure.

Fig. 2 is a schematic structural diagram of a level shift circuit according to an embodiment of the present disclosure.

Fig. 3 is a schematic structural diagram of a level shift circuit according to an embodiment of the present disclosure.

Reference numerals:

100-low voltage signal input; 200-a low voltage domain inverter circuit; 210-a first PMOS tube;

211-source of the first PMOS transistor; 212-drain of first PMOS tube;

213-grid of the first PMOS tube; 220-first NMOS transistor; 221-source of first NMOS transistor;

222-drain of the first NMOS transistor; 223-a grid electrode of the first NMOS tube; 300-a low voltage source;

400-high voltage domain switching circuit; 410-a second NMOS tube; 411-source of second NMOS transistor;

412-the gate of the second NMOS transistor; 413-drain electrode of second NMOS tube; 420-third NMOS tube;

421-source of third NMOS transistor; 422-grid electrode of the third NMOS tube;

423-drain electrode of the third NMOS tube; 430-second PMOS tube; 431-the drain electrode of the second PMOS tube;

432-the gate of the second PMOS transistor; 433-a source electrode of the second PMOS tube; 440-third PMOS tube;

441-the drain electrode of the third PMOS tube; 442-a gate of a third PMOS transistor;

443-source of the third PMOS transistor; 500-high voltage source; 600-a high voltage signal output;

610-a first output; 620-second output; 710-fourth NMOS transistor;

711-gate of fourth NMOS transistor; 712-drain of the fourth NMOS transistor;

713-source of the fourth NMOS transistor; 720-fifth NMOS transistor; 721-grid electrode of a fifth NMOS tube;

722-drain of five NMOS tubes; 723-Source electrode of fifth NMOS tube

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

The application provides a level conversion circuit.

As shown in fig. 1, in an embodiment of the present application, the level shifter circuit includes a low voltage signal input terminal 100, a low voltage domain inverter circuit 200, a low voltage source 300, a high voltage domain shifter circuit 400, a high voltage source 500, and a high voltage signal output terminal 600.

The low voltage signal input terminal 100 is used for inputting a low voltage domain square wave voltage signal. The low-voltage domain inverter circuit 200 is configured to invert the low-voltage domain square wave voltage signal. The low voltage source 300 is electrically connected to the low voltage domain inverter circuit 200.

The low voltage source 300 is used to provide power to the low voltage domain inverter circuit 200. The high-voltage domain converting circuit 400 is configured to convert the inverted low-voltage domain square wave voltage signal into a high-voltage domain square wave voltage signal. The high voltage domain switching circuit 400 is also electrically connected to the low voltage signal input terminal 100. The high voltage source 500 is electrically connected to the high voltage domain converting circuit 400. The high voltage source 500 is used for providing electric energy for the high voltage domain converting circuit 400.

The output voltage value of the low voltage source 300 is smaller than the output voltage value of the high voltage source 500. The high voltage signal output terminal 600 is used for outputting the square wave voltage signal of the high voltage domain. And the effective voltage value of the low-voltage domain square wave voltage signal is smaller than that of the high-voltage domain square wave voltage signal.

Specifically, the voltage effective value of the low-voltage domain square wave voltage signal and the voltage effective value of the high-voltage domain square wave voltage signal may be set in advance. As long as the voltage effective value of the low-voltage domain square wave voltage signal is less than the voltage effective value of the high-voltage domain square wave voltage signal. For example, the effective voltage value of the low-voltage domain square wave voltage signal may be set to 1.8V, and the effective voltage value of the high-voltage domain square wave voltage signal may be set to 3.3V. Low voltage 1.8V and high voltage 3.3V are low voltage high voltage configurations common in the field of electronic circuits.

The low-voltage domain square wave voltage signal is input from the low-voltage signal input terminal 100. The low-voltage-domain square-wave voltage signal may be a regular square-wave signal, in other words, the voltage value of the regular square-wave signal exhibits a periodic rule of "0V-1.8V-0V.", and then the voltage value of the inverted low-voltage-domain square-wave voltage signal exhibits a periodic rule of "1.8V-0V-1.8V.".

In this embodiment, the low-voltage-domain square-wave voltage signal input by the low-voltage-domain inverter circuit 200 is converted into an inverted low-voltage-domain square-wave voltage signal, and the low-voltage-domain square-wave voltage signal and the inverted square low-voltage-domain voltage signal are input to the high-voltage-domain conversion circuit 400 together and are complementary in waveform, so that the high-voltage-domain conversion circuit 400 becomes a stable load, and the low-voltage-domain square-wave voltage signal is converted into a high-voltage-domain square-wave voltage signal and output. When the voltage signal is periodically and rapidly changed, the level conversion circuit has high level conversion speed and high response speed of the output signal.

As shown in fig. 2, in an embodiment of the present application, the low-voltage domain inverter circuit 200 includes a first PMOS transistor 210 and a first NMOS transistor 220. The source 211 of the first PMOS transistor 210 is electrically connected to the low voltage source 300. The source 221 of the first NMOS transistor 220 is grounded. The drain 222 of the first NMOS transistor 220 is electrically connected to the drain 212 of the first PMOS transistor 210. The gate 223 of the first NMOS transistor 220 is electrically connected to the gate 213 of the first PMOS transistor 210. The low voltage signal input terminal 100 is electrically connected to a connection link between the gate 223 of the first NMOS transistor 220 and the gate 213 of the first PMOS transistor 210.

Specifically, in the present embodiment, the low-voltage domain inverter circuit 200 is composed of a first PMOS transistor 210 and a first NMOS transistor 220. The combined assembly of the first PMOS transistor 210 and the first NMOS transistor 220 functions as an inverter.

Referring to fig. 2, in an embodiment of the present application, the high voltage domain converting circuit 400 includes a second NMOS transistor 410, a third NMOS transistor 420, a second PMOS transistor 430, and a third PMOS transistor 440.

The source 411 of the second NMOS transistor 410 is grounded. The gate 412 of the second NMOS transistor 410 is electrically connected to the connection link between the drain 222 of the first NMOS transistor 220 and the drain 212 of the first PMOS transistor 210. The source 421 of the third NMOS transistor 420 is grounded. The gate 422 of the third NMOS transistor 420 is electrically connected to the connection link between the gate 223 of the first NMOS transistor 220 and the low voltage signal input terminal 100. The drain 431 of the second PMOS transistor 430 is electrically connected to the drain 413 of the second NMOS transistor 410. The gate 432 of the second PMOS transistor 430 is electrically connected to the drain 423 of the third NMOS transistor 420. The drain 441 of the third PMOS transistor 440 is electrically connected to the drain 423 of the third NMOS transistor 420. The gate 442 of the third PMOS transistor 440 is electrically connected to the drain 413 of the second NMOS transistor 410. The source 433 of the second PMOS transistor 430 is electrically connected to the source 443 of the third PMOS transistor 440. The high voltage source 500 is electrically connected to the connection link between the source 433 of the second PMOS transistor 430 and the source 443 of the third PMOS transistor 440.

Specifically, the high-voltage domain converting circuit 400 is composed of a second NMOS transistor 410, a third NMOS transistor 420, a second PMOS transistor 430, and a third PMOS transistor 440, and these four MOS transistors are cross-coupled to form a load.

Referring to fig. 2, in an embodiment of the present application, the high voltage signal output terminal 600 includes a first output terminal 610 and a second output terminal 620. The first output terminal 610 is electrically connected to a connection link between the drain 431 of the second PMOS transistor 430 and the drain 413 of the second NMOS transistor 410. The second output terminal 620 is electrically connected to a connection link between the drain 441 of the third PMOS transistor 440 and the drain 423 of the third NMOS transistor 420.

Specifically, the polarity of the voltage signal at the low voltage signal input terminal 100 is the same as the polarity of the voltage signal at the first output terminal 610, and the polarity of the voltage signal at the low voltage signal input terminal 100 is opposite to the polarity of the voltage signal at the second output terminal 620. That is, the polarity of the voltage signal at the second output terminal 620 is the same as the polarity of the voltage signal at the Vn point.

The voltage signal polarity of the low voltage signal input terminal 100 is the same as the voltage signal polarity of the first output terminal 610, which means that when the voltage value input by the low voltage signal input terminal 100 is 0V, the voltage value output by the first output terminal 610 is also 0V. When the voltage value input by the low voltage signal input terminal 100 is 1.8V, the voltage value output by the first output terminal 610 is also 1.8V.

The fact that the polarity of the voltage signal at the low voltage signal input terminal 100 is opposite to the polarity of the voltage signal at the second output terminal 620 means that when the voltage value input at the low voltage signal input terminal 100 is 0V, the voltage value output at the second output terminal 620 is 1.8V. When the voltage value input by the low voltage signal input terminal 100 is 1.8V, the voltage value output by the second output terminal 620 is 0V.

In this embodiment, the high voltage signal output terminal 600 uses two output terminals for output, so as to better match the cross-coupling structure of the high voltage domain converting circuit 400.

In an embodiment of the present application, the threshold voltage of the first PMOS transistor 210 is greater than 0 and smaller than the output voltage value of the low voltage source 300. The threshold voltage of the first NMOS transistor 220 is greater than 0 and less than the output voltage value of the low voltage source 300.

Specifically, the threshold voltage is a process parameter and is mainly determined by the characteristics of the MOS device, and the threshold voltage of the MOS device in this application represents the turn-on voltage threshold of the MOS device, and the subsequent occurrence of the same terms will not be repeatedly explained. The first PMOS transistor 210 and the first NMOS transistor 220 are both low-voltage domain MOS transistors, and their threshold voltages (equal to their turn-on threshold voltages in terms of value) are the same and both greater than 0 and smaller than the output voltage value of the low-voltage source 300, so that the normal turn-on of the first PMOS transistor 210 and the first NMOS transistor 220 can be ensured.

The threshold voltage of the first PMOS transistor 210 and the threshold voltage of the first NMOS transistor 220 have no necessary numerical relationship, and the numerical value of the threshold voltage is determined according to the device property of the MOS device, that is, when the MOS device is produced in a factory.

In an embodiment of the present application, the threshold voltage of the second NMOS transistor 410 is greater than the threshold voltage of the first NMOS transistor 220 and less than the output voltage value of the high voltage source, and the threshold voltage of the second NMOS transistor 410 is equal to the threshold voltage of the third NMOS transistor 420.

Specifically, the second NMOS transistor 410 and the third NMOS transistor 420 are both high-voltage domain NMOS transistors, and have the same threshold voltage, which is greater than the threshold voltage of the low-voltage domain NMOS transistor (i.e., greater than the threshold voltage of the first NMOS transistor 220) and less than the output voltage value of the high-voltage source 500, so that the second NMOS transistor 410 and the third NMOS transistor 420 can be ensured.

In an embodiment of the present application, the threshold voltage of the second PMOS transistor 430 is greater than the threshold voltage of the first PMOS transistor 410 and less than the output voltage value of the high voltage source, and the threshold voltage of the second PMOS transistor 430 is equal to the threshold voltage of the third PMOS transistor 440.

Specifically, the second PMOS transistor 430 and the third PMOS transistor 440 are both high-voltage PMOS transistors, and have the same threshold voltage, which is greater than the threshold voltage of the low-voltage PMOS transistor (i.e., greater than the threshold voltage of the first PMOS transistor 210) and less than the output voltage of the high-voltage source 500, so that the second PMOS transistor 430 and the third PMOS transistor 440 can be normally turned on.

The second NMOS transistor 410 and the second PMOS transistor 430 have no necessary numerical relationship, and the value of the threshold voltage is determined according to the device property of the MOS device, i.e. when the MOS device is produced in a factory.

Through the above setting of the threshold voltages of the first PMOS transistor 210, the first NMOS transistor 220, the second NMOS transistor 410, the third NMOS transistor 420, the second PMOS transistor 430, and the third PMOS transistor 440, the low-voltage domain inverter circuit 200 is in the low-voltage domain, and the high-voltage domain converter circuit 400 is in the high-voltage domain as a whole.

As shown in fig. 2, if the low-voltage domain voltage value is 1.8V and the high-voltage domain voltage value is 3.3V, the following operation principle of the whole level shift circuit is illustrated: when the low voltage signal input terminal 100 is switched from 1.8V to 0, the first NMOS transistor 220 is turned off, the first PMOS transistor 210 is turned on, and then Vn inverts to output 1.8V. Since the voltage at Vn is 1.8V, 410 is turned on. Since the voltage at the low voltage signal input 100 is 0, 420 is turned off. Further, the second PMOS transistor 430 is turned off, the third PMOS transistor 440 is turned on, and the second output terminal 620 outputs 3.3V. The first output terminal 610 outputs a voltage of 0.

When the low-voltage signal input end 100 is switched from 0V to 1.8V, the first NMOS tube is conducted, the first PMOS tube is closed, and then Vn outputs 0V voltage after phase inversion. Since the voltage at Vn is 0V, the second NMOS transistor 410 is turned off. Since the voltage at the low voltage signal input terminal 100 is 1.8V, the third NMOS transistor 420 is turned on. Further, the second PMOS transistor 430 is turned on, the third PMOS transistor 440 is turned off, and the first output terminal 610 outputs 3.3V. The second output terminal 620 outputs a voltage of 0.

As shown in fig. 3, in an embodiment of the present application, the level shifter circuit includes a fourth NMOS transistor 710 and a fifth NMOS transistor 720. The gate 711 of the fourth NMOS tube 710 is electrically connected to the low voltage signal input terminal 100. The drain 712 of the fourth NMOS tube 710 is electrically connected to the second PMOS tube 430. The source 713 of the fourth NMOS tube 710 is electrically connected to the connection link between the drain 431 of the second PMOS tube 430 and the drain 413 of the second NMOS tube 410.

As shown in fig. 3, in an embodiment of the present application, the drain 722 of the fifth NMOS transistor 720 is electrically connected to the third PMOS transistor 440, and the source 723 of the fifth NMOS transistor 720 is electrically connected to the connection link between the drain 441 of the third PMOS transistor 440 and the drain 423 of the third NMOS transistor 420.

Specifically, in this embodiment, two NMOS transistors are added: a fourth NMOS transistor 710 and a fifth NMOS transistor 720. Both tubes are low pressure area. When the low voltage signal input terminal 100 is switched from 0 to 1.8V, the gate 711 of the fourth NMOS tube 710 is connected with 1.8V, so that the fourth NMOS tube 710 is connected, and thus, compared with the circuit structure of the previous embodiment, the fourth NMOS tube 710 is added to fill more current into the first output terminal 610, thereby helping the voltage raising speed, which is equivalent to increasing the response speed of the high voltage domain converting circuit 400, and accelerating the establishment of voltage inversion. At this time, the polarity of the fifth NMOS transistor 720 is the same as the polarity of the Vn point. The polarity of the point Vn is opposite to that of the low voltage signal input terminal 100, and the voltage is 0V. Then the gate 721 of the fifth NMOS transistor 720 is turned on with 0V, and the fifth NMOS transistor 720 is turned off.

On the contrary, when the low voltage signal input terminal 100 is switched from 1.8V to 0V, the gate 711 of the fourth NMOS tube 710 is applied with 0V, and the fourth NMOS tube 710 is not turned on. At this time, the polarity of the fifth NMOS transistor 720 is the same as the polarity of the Vn point. The polarity of the Vn point is opposite to that of the low voltage signal input terminal 100, and the voltage is 1.8V. Then the gate 721 of the fifth NMOS transistor 720 is applied with 1.8V, and the fifth NMOS transistor 720 is turned on. The conduction of the fifth NMOS transistor 720 can sink more current into the output node of the second output terminal 620, thereby increasing the output response speed thereof.

In this embodiment, on the basis of the level conversion circuit structure of the previous embodiment, the fourth NMOS 710 and the fifth NMOS 720 are added, so that the response capability of the two high-voltage signal output terminals 600 is increased, and the high-voltage output signal can be turned over and established more quickly.

In an embodiment of the present application, the threshold voltage of the first NMOS transistor 220 is equal to the threshold voltage of the fourth NMOS transistor 710 is equal to the threshold voltage of the fifth NMOS transistor 720.

Specifically, the fourth NMOS 710 and the fifth NMOS 720 are also MOS transistors in a low voltage domain, and the on-off state is switched according to the voltage value of the low voltage signal input terminal 100, so as to inject more current into the output terminal.

The technical features of the embodiments described above may be arbitrarily combined, the order of execution of the method steps is not limited, and for simplicity of description, all possible combinations of the technical features in the embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, the combinations of the technical features should be considered as the scope of the present description.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims (10)

1. A level shift circuit, comprising:

the low-voltage signal input end is used for inputting a low-voltage-domain square wave voltage signal;

the low-voltage domain inverter circuit is used for inverting the low-voltage domain square wave voltage signal;

the low-voltage source is electrically connected with the low-voltage domain inverter circuit and used for providing electric energy for the low-voltage domain inverter circuit;

the high-voltage domain conversion circuit is used for converting the low-voltage domain square wave voltage signal after phase inversion into a square wave voltage signal of a high-voltage domain; the high-voltage domain conversion circuit is also electrically connected with the low-voltage signal input end;

the high-voltage source is electrically connected with the high-voltage domain conversion circuit and used for providing electric energy for the high-voltage domain conversion circuit; the output voltage value of the low-voltage source is smaller than that of the high-voltage source;

the high-voltage signal output end is used for outputting a square wave voltage signal of the high-voltage domain; and the effective voltage value of the low-voltage domain square wave voltage signal is smaller than that of the high-voltage domain square wave voltage signal.

2. The level shift circuit according to claim 1, wherein the low-voltage domain inverter circuit comprises:

the source electrode of the first PMOS tube is electrically connected with the low-voltage source;

the source electrode of the first NMOS tube is grounded, the drain electrode of the first NMOS tube is electrically connected with the drain electrode of the first PMOS tube, and the grid electrode of the first NMOS tube is electrically connected with the grid electrode of the first PMOS tube;

the low-voltage signal input end is electrically connected with a connection link between the grid electrode of the first NMOS tube and the grid electrode of the first PMOS tube.

3. The level shifter circuit of claim 2, wherein the high voltage domain shifter circuit comprises:

the source electrode of the second NMOS tube is grounded, and the grid electrode of the second NMOS tube is electrically connected with a connecting link between the drain electrode of the first NMOS tube and the drain electrode of the first PMOS tube;

the source electrode of the third NMOS tube is grounded, and the grid electrode of the third NMOS tube is electrically connected with the connecting link between the grid electrode of the first NMOS tube and the low-voltage signal input end;

the drain electrode of the second PMOS tube is electrically connected with the drain electrode of the second NMOS tube; the grid electrode of the second PMOS tube is electrically connected with the drain electrode of the third NMOS tube;

the drain electrode of the third PMOS tube is electrically connected with the drain electrode of the third NMOS tube; the grid electrode of the third PMOS tube is electrically connected with the drain electrode of the second NMOS tube;

the source electrode of the second PMOS tube is electrically connected with the source electrode of the third PMOS tube;

the high-voltage source is electrically connected to a connection link between the source electrode of the second PMOS tube and the source electrode of the third PMOS tube.

4. The circuit of claim 3, wherein the high voltage signal output comprises:

the first output end is electrically connected with a connecting link between the drain electrode of the second PMOS tube and the drain electrode of the second NMOS tube;

and the second output end is electrically connected with a connection link between the drain electrode of the third PMOS tube and the drain electrode of the third NMOS tube.

5. The circuit of claim 4, wherein the threshold voltage of the first PMOS transistor is greater than 0 and less than the output voltage value of the low voltage source, and the threshold voltage of the first NMOS transistor is greater than 0 and less than the output voltage value of the low voltage source.

6. The circuit of claim 5, wherein the threshold voltage of the second NMOS transistor is greater than the threshold voltage of the first NMOS transistor and less than the output voltage value of the high voltage source, and wherein the threshold voltage of the second NMOS transistor is equal to the threshold voltage of the third NMOS transistor.

7. The circuit of claim 6, wherein the threshold voltage of the second PMOS transistor is greater than the threshold voltage of the first PMOS transistor and less than the output voltage value of the high voltage source, and wherein the threshold voltage of the second PMOS transistor is equal to the threshold voltage of the third PMOS transistor.

8. The level shift circuit of claim 7, further comprising:

the grid electrode of the fourth NMOS tube is electrically connected with the low-voltage signal input end, the drain electrode of the fourth NMOS tube is electrically connected with the second PMOS tube, and the source electrode of the fourth NMOS tube is electrically connected with a connection link between the drain electrode of the second PMOS tube and the drain electrode of the second NMOS tube.

9. The level shift circuit of claim 8, further comprising:

the grid electrode of the fifth NMOS tube is electrically connected with the second NMOS tube, the drain electrode of the fifth NMOS tube is electrically connected with the third PMOS tube, and the source electrode of the fifth NMOS tube is electrically connected with a connecting link between the drain electrode of the third PMOS tube and the drain electrode of the third NMOS tube.

10. The circuit of claim 9, wherein the threshold voltage of the first NMOS transistor is equal to the threshold voltage of the fourth NMOS transistor is equal to the threshold voltage of the fifth NMOS transistor.

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