CN111884648B - Output feedback logic circuit and chip based on unipolar transistor - Google Patents
Output feedback logic circuit and chip based on unipolar transistor Download PDFInfo
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- CN111884648B CN111884648B CN202010560677.6A CN202010560677A CN111884648B CN 111884648 B CN111884648 B CN 111884648B CN 202010560677 A CN202010560677 A CN 202010560677A CN 111884648 B CN111884648 B CN 111884648B
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- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
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Abstract
The invention discloses an output feedback logic circuit and a chip based on a unipolar transistor, wherein the output feedback logic circuit comprises: the source electrode of the first transistor is connected with the first end of the pull-down unit and serves as the output end of the output feedback logic circuit, and the connecting point between the first end of the input control switch and the first end of the output control switch is connected with the grid electrode of the first transistor; the control end of the input control switch is connected to the signal input end, and the second end of the input control switch is connected with the output end of the output feedback logic circuit; the control end of the output control switch is connected with the output end of the output feedback logic circuit; the control end of the pull-down unit is connected to the signal input end, and the first end of the pull-down unit is connected with the output end of the output feedback logic circuit. The output feedback logic circuit of the invention only consists of unipolar transistors; compared with the traditional design, the output feedback logic circuit has lower circuit complexity and can be widely applied to the field of semiconductor integrated circuits.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuits, in particular to an output feedback logic circuit and a chip based on a unipolar transistor.
Background
There are practical difficulties between conventional rigid electronics and flexible articles of daily life such as paper, tapes, human bodies and textiles. We can solve this problem by large area flexible electronics. These large area flexible electronic technologies offer flexibility, light weight, ultra-thin dimensions, transparency, stretchability, large area applicability, low cost and other attractive functionalities.
However, most flexible electronic technologies today can only provide high performance unipolar (pure n-type or pure p-type) devices. For example, a-Si TFT technology, oxide TFT technology with the main device type being n-type transistors; in the organic TFT technology, the main device type of the carbon nanotube technology is a p-type transistor. Therefore, in general, the flexible electronic circuit can be realized based on only unipolar transistors, which means that the conventional CMOS circuit design technology is no longer applicable, and the design of the flexible integrated circuit faces many challenges compared with the mature CMOS integrated circuit design technology.
The invention only uses a pure n-type circuit as an example for discussion, and for a pure p-type circuit, the circuit is just turned over up and down, so detailed description is not needed.
The basic logic gate circuit based on the unipolar device has two designs in common use at present: pseudo-CMOS technology and capacitive bootstrapping technology. Fig. 1 shows a pseudo CMOS inverter structure. Fig. 2 shows a capacitor bootstrapped inverter architecture. From the circuit complexity point of view, the pseudo CMOS technology requires two power supplies, and the capacitor bootstrap technology requires a bootstrap capacitor, which undoubtedly increases the circuit complexity. From a power consumption perspective, when the input is high, neither the pull-up transistor nor the pull-down transistor can be completely turned off, and thus there is a large leakage current, resulting in non-zero static power consumption.
Disclosure of Invention
In order to solve one of the above technical problems, an object of the present invention is to provide an output feedback logic circuit and a chip based on unipolar transistors.
The first technical scheme adopted by the invention is as follows:
an output feedback logic circuit based on a unipolar transistor comprises a pull-up unit, a pull-down unit, an input control switch and an output control switch, wherein the pull-up unit comprises a first transistor;
the drain electrode of the first transistor is connected with a power supply end, the source electrode of the first transistor is connected with the first end of the pull-down unit and serves as the output end of the output feedback logic circuit, and the connecting point between the first end of the input control switch and the first end of the output control switch is connected with the grid electrode of the first transistor;
the control end of the input control switch is connected to the signal input end, and the second end of the input control switch is connected with the output end of the output feedback logic circuit;
the control end of the output control switch is connected with the output end of the output feedback logic circuit, and the second end of the output control switch is connected with a power supply end;
the control end of the pull-down unit is connected to the signal input end, the first end of the pull-down unit is connected with the output end of the output feedback logic circuit, and the second end of the pull-down unit is connected to the ground end;
the output feedback logic circuit includes at least one of an inverter circuit, a multiple-input nor gate circuit, or a multiple-input nand gate circuit.
Further, the output control switch is made of one transistor.
Further, the unipolar transistor is an n-type transistor, the output feedback logic circuit is an inverter circuit, the pull-down unit includes a second transistor, the output control switch includes a third transistor, and the input control switch includes a fourth transistor;
the drain electrode of the second transistor is connected with the output end of the output feedback logic circuit, the grid electrode of the second transistor is connected to the signal input end, and the source electrode of the second transistor is connected to the ground end;
the drain electrode of the third transistor is connected to a power supply end, the grid electrode of the third transistor is connected with the output end of the output feedback logic circuit, and the source electrode of the third transistor is connected with the drain electrode of the fourth transistor;
and the grid electrode of the fourth transistor is connected to the signal input end, and the source electrode of the fourth transistor is connected with the output end of the output feedback logic circuit.
Further, the unipolar transistor is an n-type transistor, the output feedback logic circuit is a multi-input nor gate circuit, the pull-down unit includes m parallel transistors, the input control switch includes m parallel transistors, the output control switch includes a transistor, a gate of the transistor is connected with an output end of the output feedback logic circuit, and m is an integer greater than 1.
Further, the multiple-input nor gate circuit is a two-input nor gate circuit, the pull-down unit includes a fifth transistor and a sixth transistor, and the input control switch includes a seventh transistor and an eighth transistor;
the drain electrode of the fifth transistor and the drain electrode of the sixth transistor are both connected to the output end of the output feedback logic circuit, the source electrode of the fifth transistor and the source electrode of the sixth transistor are both connected to the ground end, the grid electrode of the fifth transistor is connected to the first signal input end, and the grid electrode of the sixth transistor is connected to the second signal input end;
the drain electrode of the seventh transistor and the drain electrode of the eighth transistor are both connected with the source electrode of the output control switch, the source electrode of the seventh transistor and the source electrode of the eighth transistor are both connected with the output end of the output feedback logic circuit, the grid electrode of the seventh transistor is connected with the first signal input end, and the grid electrode of the eighth transistor is connected with the second signal input end.
Further, the unipolar transistor is an n-type transistor, the output feedback logic circuit is a multi-input nand gate circuit, the pull-down unit includes p transistors connected in series, the input control switch includes p transistors connected in series, the output control switch includes a transistor, a gate of the transistor is connected to an output end of the output feedback logic circuit, and p is an integer greater than 1.
Further, the multiple input nand gate circuit is a two input nand gate circuit, the pull-down unit includes a ninth transistor and a tenth transistor, and the input control switch includes an eleventh transistor and a twelfth transistor;
the drain of the ninth transistor is connected with the output end of the output feedback logic circuit, the source of the ninth transistor is connected with the drain of the tenth transistor, and the gate of the ninth transistor is connected to the first signal input end;
a source of the tenth transistor is connected to a ground terminal, and a gate of the tenth transistor is connected to the second signal input terminal;
the drain of the eleventh transistor is connected with the source of the output control switch, the source of the eleventh transistor is connected with the drain of the twelfth transistor, and the gate of the eleventh transistor is connected to the first signal input end;
and the source electrode of the twelfth transistor is connected to the output end of the output feedback logic circuit, and the grid electrode of the twelfth transistor is connected to the second signal input end.
The second technical scheme adopted by the invention is as follows:
a chip comprises a logic circuit, wherein the logic circuit adopts the output feedback logic circuit based on the unipolar transistor.
The invention has the beneficial effects that: the output feedback logic circuit only consists of unipolar transistors and is suitable for the flexible electronic technology; in addition, the output feedback logic circuit is less complex than conventional designs.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description is made on the drawings of the embodiments of the present invention or the related technical solutions in the prior art, and it should be understood that the drawings in the following description are only for convenience and clarity of describing some embodiments in the technical solutions of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a circuit schematic of a prior art pseudo CMOS inverter;
FIG. 2 is a circuit schematic of a prior art capacitor-bootstrapped inverter;
FIG. 3 is a schematic diagram of an inverter circuit in an embodiment of the invention;
FIG. 4 is an electrical schematic of an inverter circuit according to an embodiment of the present invention;
FIG. 5 is a schematic diagram showing a VTC curve of an inverter circuit in an embodiment;
FIG. 6 is a schematic diagram showing the current consumption of an inverter circuit according to an embodiment;
FIG. 7 is a schematic diagram of the current consumption of a conventional pseudo CMOS logic circuit;
FIG. 8 is a schematic diagram of the current consumption of a conventional capacitive bootstrap logic circuit;
FIG. 9 is a schematic diagram of a two-input NOR gate circuit in an embodiment of the present invention;
FIG. 10 is a schematic diagram of a two input NAND gate circuit in an embodiment of the present invention;
FIG. 11 is a diagram illustrating the operating waveforms and current consumption of a two-input NOR gate according to an embodiment of the present invention;
FIG. 12 is a diagram illustrating the operating waveforms and current consumption of a two-input NAND gate according to an embodiment of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
In the description of the present invention, it should be understood that the orientation or positional relationship referred to in the description of the orientation, such as the upper, lower, front, rear, left, right, etc., is based on the orientation or positional relationship shown in the drawings, and is only for convenience of description and simplification of description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
In the description of the present invention, the meaning of a plurality of means is one or more, the meaning of a plurality of means is two or more, and larger, smaller, larger, etc. are understood as excluding the number, and larger, smaller, inner, etc. are understood as including the number. If the first and second are described for the purpose of distinguishing technical features, they are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
In the description of the present invention, unless otherwise explicitly limited, terms such as arrangement, installation, connection and the like should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above terms in the present invention in combination with the specific contents of the technical solutions.
The embodiment provides an output feedback logic circuit based on a unipolar transistor, wherein the output feedback logic circuit is an inverter circuit, a multi-input NOR gate circuit, a multi-input NAND gate circuit or the like.
As shown in fig. 3, in some embodiments, the output feedback logic circuit is an inverter circuit of an output feedback structure, and the inverter circuit is composed of a pull-up transistor T1 (i.e., a first transistor), a pull-down transistor T2 (i.e., a second transistor), and two switches T3 and T4. Switch T3 is controlled by the output signal and switch T4 is controlled by the input signal. When the control signal is at high level, the switch is turned on, and when the control signal is at low level, the switch is turned off. In some embodiments, the switches T3, T4 may be made using transistors, as shown in fig. 4.
When the input is low, T2 and T4 turn off, the output node voltage rises, which causes T3 to turn on, the gate voltage of T1 increases, and the output voltage continues to rise, causing T3 to turn on further. The above steps are repeated in a circulating way to generate positive feedback, and finally the output voltage is pulled up to a high level.
When the input is high, T2 and T4 turn on, the output node voltage drops, which turns T3 off. Since T4 is on, T1 is off and the pull-up current is zero, so the final output node is pulled down to a low level.
Referring to table 1, the circuit structure of the present embodiment uses the same number of transistors as the conventional structure from the viewpoint of circuit complexity, but does not need to use a dual power supply and a capacitor, and thus the circuit complexity is lower.
TABLE 1
| Pseudo CMOS logic | Capacitive bootstrap logic | This example | |
| Number of |
2 | 1 | 1 |
| Number of devices | 4 transistor | 4 |
4 transistor |
| Static power consumption | Is provided with | Is provided with | Is free of |
From the perspective of circuit power consumption, the circuit of this embodiment has no static power consumption. When the input is low and the output is high, Vgs of T1 and T2 is 0, T1T2 is cut off, no current path exists between a power supply and the ground, and therefore the circuit has no static power consumption. When the input is high and the output is low, Vgs of T1 is 0, Vds of T2 is 0, T1 and T2 are both cut off, and no current path exists between a power supply and the ground, so that the circuit has no static power consumption.
Symmetric Voltage Transfer (VTC) curves can be obtained by adjusting the dimensions of T1, T2. In the present embodiment, the transistors T2, T3, T4 are W/L in size, and T1 is 10W/L in size.
FIG. 5 is a diagram illustrating VTC curves of the inverter circuit under different power sources. As can be seen, the inverter circuit of the present embodiment can achieve the desired high and low levels, and thus has a full output swing. In addition, the VTC curve of the present embodiment is symmetrical. Finally, because of the introduction of positive feedback, the high and low levels are switched very quickly, and the transition interval of the high and low levels is very narrow. The three points collectively indicate that the inverter circuit of the present embodiment has good noise margin.
Fig. 6 shows current consumption of the inverter circuit of the present embodiment in different power supplies. The circuit only consumes current during the high-low level transition interval. In steady state, the circuit has no current consumption. Therefore, the inverter circuit of the present embodiment has only dynamic power consumption and no static power consumption.
In contrast, fig. 7 shows a current consumption diagram of a conventional dummy CMOS logic circuit, and fig. 8 shows a current consumption diagram of a conventional capacitive bootstrap logic circuit. It can be seen that there is some current consumption when the input is high and the output is low because neither the pull-up nor pull-down transistors can be completely turned off. Both logic structures therefore have static power consumption.
In some embodiments, the parallel expansion of the transistors T2 and T4 can obtain a multi-input nor gate, as shown in fig. 9, fig. 9 is a two-input nor gate of this embodiment, and T2 is expanded as parallel T5 and T6, and T4 is expanded as parallel T7 and T8. Wherein, the inputs of T5 and T7 are connected with the same input terminal in1, and the inputs of T6 and T8 are connected with the same input terminal in 2.
In some embodiments, a multi-input nand gate can be obtained by expanding T2 and T4 in series, as shown in fig. 10, fig. 10 is a two-input nand gate of this embodiment, T2 is expanded as series T9 and T10, and T4 is expanded as parallel T11 and T12. Wherein, the inputs of T9 and T11 are connected with the same input terminal in1, and the inputs of T10 and T12 are connected with the same input terminal in 2.
Fig. 11 shows the operating waveform and current consumption of the two-input nor gate according to the present embodiment; fig. 12 shows the operating waveforms and current consumption of the two-input nand gate according to this embodiment. It can be seen that the nor, nand operation functions correctly. The circuit has dynamic power consumption only when the input signal transitions. And no static power consumption in steady state.
In summary, the output feedback logic circuit of the present embodiment is only composed of unipolar transistors, and thus is suitable for flexible electronic technologies (e.g., thin film transistors, carbon nanotubes, etc.). In addition, compared with the traditional design, the circuit of the embodiment has low complexity (no need of a double power supply and a bootstrap capacitor), and has no static power consumption, so that the power consumption is greatly reduced.
The embodiment also provides a chip which comprises a logic circuit, wherein the logic circuit adopts the output feedback logic circuit based on the unipolar transistor.
The chip of the embodiment has a corresponding relationship with the output feedback logic circuit, and therefore has corresponding functions and beneficial effects of the trigger circuit.
While the preferred embodiments of the present invention have been illustrated and described, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (8)
1. An output feedback logic circuit based on a unipolar transistor is characterized by comprising a pull-up unit, a pull-down unit, an input control switch and an output control switch, wherein the pull-up unit comprises a first transistor; the drain electrode of the first transistor is connected with a power supply end, the source electrode of the first transistor is connected with the first end of the pull-down unit and serves as the output end of the output feedback logic circuit, and the connecting point between the first end of the input control switch and the first end of the output control switch is connected with the grid electrode of the first transistor;
the control end of the input control switch is connected to the signal input end, and the second end of the input control switch is connected with the output end of the output feedback logic circuit;
the control end of the output control switch is connected with the output end of the output feedback logic circuit, and the second end of the output control switch is connected with a power supply end;
the control end of the pull-down unit is connected to the signal input end, the first end of the pull-down unit is connected with the output end of the output feedback logic circuit, and the second end of the pull-down unit is connected to the ground end; the output feedback logic circuit is at least one of an inverter circuit, a multi-input NOR gate circuit or a multi-input NAND gate circuit.
2. The output feedback logic circuit based on unipolar transistors according to claim 1, wherein said output control switch is made of one transistor.
3. The unipolar transistor-based output feedback logic circuit according to claim 1, wherein the unipolar transistor is an n-type transistor, the output feedback logic circuit is an inverter circuit, the pull-down unit comprises a second transistor, the output control switch comprises a third transistor, and the input control switch comprises a fourth transistor;
the drain electrode of the second transistor is connected with the output end of the output feedback logic circuit, the grid electrode of the second transistor is connected to the signal input end, and the source electrode of the second transistor is connected to the ground end;
the drain electrode of the third transistor is connected to a power supply end, the grid electrode of the third transistor is connected with the output end of the output feedback logic circuit, and the source electrode of the third transistor is connected with the drain electrode of the fourth transistor;
and the grid electrode of the fourth transistor is connected to the signal input end, and the source electrode of the fourth transistor is connected with the output end of the output feedback logic circuit.
4. The output feedback logic circuit based on unipolar transistors according to claim 1, wherein the unipolar transistor is an n-type transistor, the output feedback logic circuit is a multiple-input nor gate circuit, the pull-down unit includes m parallel transistors, the input control switch includes m parallel transistors, the output control switch includes one transistor, and a gate of the transistor in the output control switch is connected to an output end of the output feedback logic circuit, and m is an integer greater than 1.
5. The output feedback logic circuit based on unipolar transistors according to claim 4, wherein the multiple-input NOR gate circuit is a two-input NOR gate circuit, the pull-down unit comprises a fifth transistor and a sixth transistor, and the input control switch comprises a seventh transistor and an eighth transistor;
the drain electrode of the fifth transistor and the drain electrode of the sixth transistor are both connected to the output end of the output feedback logic circuit, the source electrode of the fifth transistor and the source electrode of the sixth transistor are both connected to the ground end, the grid electrode of the fifth transistor is connected to the first signal input end, and the grid electrode of the sixth transistor is connected to the second signal input end;
the drain electrode of the seventh transistor and the drain electrode of the eighth transistor are both connected with the source electrode of the transistor in the output control switch, the source electrode of the seventh transistor and the source electrode of the eighth transistor are both connected with the output end of the output feedback logic circuit, the grid electrode of the seventh transistor is connected with the first signal input end, and the grid electrode of the eighth transistor is connected with the second signal input end.
6. The output feedback logic circuit based on unipolar transistors according to claim 1, wherein the unipolar transistor is an n-type transistor, the output feedback logic circuit is a multi-input nand gate circuit, the pull-down unit comprises p transistors connected in series, the input control switch comprises p transistors connected in series, the output control switch comprises one transistor, and a gate of the transistor in the output control switch is connected to an output end of the output feedback logic circuit, and p is an integer greater than 1.
7. The output feedback logic circuit based on unipolar transistors according to claim 6, wherein the multiple-input NAND gate circuit is a two-input NAND gate circuit, the pull-down unit comprises a ninth transistor and a tenth transistor, and the input control switch comprises an eleventh transistor and a twelfth transistor; the drain of the ninth transistor is connected with the output end of the output feedback logic circuit, the source of the ninth transistor is connected with the drain of the tenth transistor, and the gate of the ninth transistor is connected to the first signal input end;
a source of the tenth transistor is connected to a ground terminal, and a gate of the tenth transistor is connected to the second signal input terminal;
a drain of the eleventh transistor is connected to a source of a transistor in the output control switch, a source of the eleventh transistor is connected to a drain of the twelfth transistor, and a gate of the eleventh transistor is connected to a first signal input terminal;
and the source electrode of the twelfth transistor is connected to the output end of the output feedback logic circuit, and the grid electrode of the twelfth transistor is connected to the second signal input end.
8. A chip comprising a logic circuit employing a unipolar transistor based output feedback logic circuit according to any one of claims 1 to 7.
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