CN213602634U

CN213602634U - Serial-parallel conversion circuit with stable level converter

Info

Publication number: CN213602634U
Application number: CN202023199284.1U
Authority: CN
Inventors: 仲佳军; 张翼; 杨磊; 周浩; 沈加晨; 吴广来; 蔡志匡; 肖建; 郭宇峰
Original assignee: Nanjing University of Posts and Telecommunications
Current assignee: Nanjing University of Posts and Telecommunications
Priority date: 2020-12-24
Filing date: 2020-12-24
Publication date: 2021-07-02
Anticipated expiration: 2030-12-24

Abstract

The utility model discloses a series-parallel conversion circuit with a stable level shifter, which comprises a level shifting unit, a voltage generating unit, a communication unit and a power-on reset unit; the level conversion unit converts the external TTL level into an applicable stable DCFL level; the voltage generating unit generates a stable voltage with small fluctuation of a power supply; the communication unit comprises a plurality of shifting registers and a plurality of parallel converters, wherein the shifting registers are composed of D triggers, the parallel converters are composed of the D triggers, the shifting registers receive input DCFL serial signals to realize a serial-parallel conversion function, and then the parallel converters output the converted parallel port signals; and when the power-on reset unit is powered on again after power failure, the level reset is realized. The utility model discloses the chip has stable level transition function and goes up the electrical reset function, and the input level transition of having solved traditional cluster parallel conversion circuit is unstable, lack the high problem of electrical reset circuit and consumption, has very important meaning to the development and the batch manufacturing of radio frequency integrated chip performance.

Description

Serial-parallel conversion circuit with stable level converter

Technical Field

The utility model belongs to the technical field of semiconductor integrated circuit design, especially, relate to an adopt series-parallel conversion circuit of taking stable level converter of GaAs PHEMT (pseudo mismatch high electron mobility field effect transistor) technology preparation.

Background

The high-speed serial-to-parallel port circuit is widely applied to a radio frequency control transmission chain of a single-chip microwave integrated circuit. Compared with a common parallel port control circuit, the serial-parallel conversion circuit has the advantages of high speed, easiness in processing and the like. The speed and power consumption of serial-to-parallel conversion circuits in monolithic microwave integrated circuits are often limited by their level shifting modules. With the development of radar digitization and monolithic microwave circuits, the requirements on the accuracy, speed and power consumption of serial-to-parallel conversion are higher and higher. In a typical radio frequency transceiving system, an external serial port control signal is converted into a parallel port signal through a serial-parallel conversion circuit to respectively control a phase shifter, an attenuator, a switch and the like in a monolithic microwave circuit, the traditional level conversion circuit, a voltage generation circuit and other circuits in the serial-parallel conversion circuit are simple in implementation method, and the wave control speed and accuracy of the circuit are severely limited by the defects of fuzzy turning points, low noise tolerance, large temperature drift, low speed and the like.

SUMMERY OF THE UTILITY MODEL

In order to solve the technical problem, the utility model provides a level shifter's serial-parallel conversion circuit is stabilized in area has improved the speed and the precision of serial-parallel conversion when having increased the function of circuit through introducing techniques such as high-precision comparator, follower and wave filter.

A take tandem conversion circuit of stabilizing level shifter, the technical scheme of its adoption is: the device comprises a level conversion unit, a voltage generation unit, a communication unit and a power-on reset unit, wherein the input end of the level conversion unit is respectively connected with external TTL data, a clock CLK and a parallel clock DARY, and the output end of the level conversion unit is respectively connected with the communication unit and provides a DCFL serial port signal of input data and a clock for the communication unit; the output end of the voltage generation unit is respectively connected with the input ends of the communication unit and the power-on reset unit and supplies power to the communication unit and the power-on reset unit; the input end of the power-on reset unit is connected with the output end of the communication unit and is used for realizing the function of level reset when the power is re-powered on after power failure.

The communication unit comprises a plurality of shifting registers and a plurality of parallel converters, wherein the shifting registers are composed of D triggers, the parallel converters are composed of the D triggers, the shifting registers are used for receiving input DCFL data serial port signals, converting the serial port signals into parallel port signals and transmitting the parallel port signals to the parallel converters, and the parallel converters output the converted parallel port signals; the convertible digit of the serial-parallel conversion circuit is determined by the communication unit, can be expanded from single digit to dozens or even more digits, and only needs to increase the digit of the shift register and the digit of the parallel converter at the same time.

Further, the level conversion unit includes a data input terminal IN, first to ninth resistors, first to fifth transistors, first to third diodes, a power supply VEE, a ground GND, and a data output terminal OUT;

one end of the first resistor R1 is connected with the data input end IN, and the other end is connected with the second resistor R2 and then connected to the base electrode of the first transistor Q1; one end of a third resistor R3 is respectively connected with a fourth resistor R4 and a fifth resistor R5, the other end of the fourth resistor R4 is connected with the collector of the first transistor Q1, and the other end of the fifth resistor R5 is connected with the collector of the second transistor Q2 and then connected to the base of the fifth transistor Q5; the emitters of the first transistor Q1 and the second transistor Q2 are connected to the collector of the third transistor Q3; one end of the sixth resistor R6 is connected to the base and collector of the fourth transistor Q4 to form a bias voltage input end, and is connected to the base of the third transistor Q3, and the seventh resistor R7 is connected to the eighth resistor R8 to form a reference voltage input end, and is connected to the base of the second transistor Q2; an emitter of the fifth transistor Q5 is sequentially connected with the first diode D1, the second diode D2 and the third diode D3, and then connected to one end of the ninth resistor R9 to form an output end OUT; the other ends of the first resistor R1, the third resistor R3, the sixth resistor R6 and the seventh resistor R7 are connected with the collector of the fifth transistor and then grounded; the other ends of the second resistor R2, the eighth resistor R8 and the ninth resistor R9 are connected to the emitters of the third transistor Q3 and the fourth transistor Q4 and then connected to the power supply VEE.

The level conversion unit introduces a comparator concept and converts an external TTL level into a suitable stable low-voltage level.

Further, the voltage generation unit includes a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a sixth transistor Q6, a power supply VEE, a ground GND, and a voltage output terminal VS;

the tenth resistor R10 and the eleventh resistor R11 are connected and then connected to the base of the sixth transistor Q6; an emitter of the sixth transistor Q6 is connected with the twelfth resistor R12 to form a voltage output end VS; the other end of the tenth resistor R10 is connected with the collector of the sixth transistor Q6 and then grounded; the other ends of the eleventh resistor R11 and the twelfth resistor R12 are connected with the power supply VEE.

The voltage generation unit introduces a follower concept for generating a stable voltage with less fluctuation from a power supply.

Further, the communication unit comprises a plurality of bit shift registers and a plurality of bit parallel converters, the parallel converters comprise a plurality of D triggers, and the D triggers are formed by cascading two latches formed by a thirteenth resistor R13, a fourteenth resistor R14 and seventh to twelfth transistors; the shift register is formed by cascading a plurality of D triggers consisting of two latches;

wherein the positive data input terminal INP is connected to the base of the seventh transistor Q7; the negative data input terminal INN is connected to the base of a ninth transistor Q9; the clock CLK is connected with the bases of the eighth transistor Q8 and the tenth transistor Q10; one end of the thirteenth resistor R13 is connected with the collector of the seventh transistor Q7, then is connected with the collector of the eleventh transistor Q11 and the base of the twelfth transistor Q12, and then is led out to form a data output positive terminal OUTP; an emitter of the seventh transistor Q7 is connected to a collector of the eighth transistor Q8; one end of the fourteenth resistor R14 is connected with the collector of the ninth transistor Q9, then is connected to the base of the eleventh transistor Q11 and the collector of the twelfth transistor Q12, and is led out as a data output negative terminal OUTN; an emitter of the ninth transistor Q9 is connected to a collector of the 10 th transistor Q10; the other ends of the thirteenth resistor R13 and the fourteenth resistor R14 are connected and then connected to the output VS of the voltage generation unit; the emitters of the eighth transistor Q8, the tenth transistor Q10, the eleventh transistor Q11 and the twelfth transistor Q12 are connected to the power supply VEE.

Further, the power-on reset unit includes a fifteenth R15, a sixteenth resistor R16, a first capacitor C1, a first inverter N1, a fourth diode D4 and a thirteenth transistor Q13;

the fifteenth resistor R15 is connected to the upper plate of the first capacitor C1 and then connected to the input end of the first inverter N1; the output end of the first inverter N1 is connected with one end of a sixteenth resistor R16; the other end of the sixteenth resistor R16 is connected with the forward end of the fourth diode; the negative end of the fourth diode is connected with the base of the thirteenth Q13; the collector of the thirteenth Q13 is connected to the positive data output terminal of the data parallel converter; the emitter of the thirteenth Q13 is connected with the lower plate of the first capacitor and then connected with the power supply VEE, and the other end of the fifteenth resistor R15 is connected with the output VS of the voltage generating unit.

Beneficial effects do:

1. on the basis of a common serial-parallel conversion circuit, a new level conversion unit is used, an input TTL level can be stably converted into an available negative electricity low-voltage level, and the problems of fuzzy level conversion turning points, low noise tolerance and low speed of the common serial-parallel conversion circuit are solved;

2. the voltage generation circuit is improved, and the influence of power supply ripples and temperature changes on output voltage is reduced;

3. the power-on reset function is added, and the problem that output data is uncertain after the traditional serial-parallel conversion circuit is powered on is solved.

Drawings

Fig. 1 is a block diagram of a serial-parallel conversion circuit system according to the present invention.

Fig. 2 is a schematic diagram of a level shift unit according to the present invention.

Fig. 3 is a schematic diagram of the voltage generating unit of the present invention.

Fig. 4 is a schematic diagram of a latch circuit of the communication unit of the present invention.

Fig. 5 is a block diagram of a D flip-flop of the communication unit of the present invention.

Fig. 6 is a schematic diagram of the power-on reset unit of the present invention.

Wherein, 101-level conversion unit, 102-level conversion unit, 103-level conversion unit, 104-communication unit, 105 power-on reset unit, 106-voltage generation unit

Detailed Description

In order that the present invention may be more readily and clearly understood, the following detailed description of the present invention is provided in connection with the accompanying drawings.

As shown in fig. 1. The serial-parallel conversion circuit with the stable level shifter includes

level shift units

101, 102, and 103, a communication unit 104, a power-on reset unit 105, and a voltage generation unit 106. The following is described in detail with reference to a specific embodiment in which the number of serial-to-parallel conversion bits is 8 bits, the corresponding shift register is 8 bits, and the corresponding parallel converter is also 8 bits.

As shown in fig. 1, the voltage generation circuit supplies power to the communication unit and the power-on reset unit which are composed of the shift register and the parallel converter; in a short time of power-on of the power supply, a transient reset signal generated by the power-on reset circuit outputs uncertain data of the communication unit before power-on, and the data are pulled to a determined low potential to complete the power-on reset function; after normal power supply, data and clocks to be converted are input from the outside, converted into usable negative electricity low-voltage data and clocks through the level conversion unit, and accessed into the communication unit, so that the serial-parallel conversion function is completed.

For a level conversion unit, an external TTL level is accurately converted into an available low-voltage negative power DCFL level, and a traditional circuit uses a diode drop circuit, so that the temperature characteristic is poor, the turning point is fuzzy, and the speed is low; therefore, the concept of a comparator is introduced, as shown IN fig. 2, an input TTL serial signal IN (a data signal and a clock signal) is divided into a negative level of-2.5/-3.75V by resistors R1 and R2, and is connected to a differential comparison transistor Q1; adding a reference voltage, connecting a differential comparison tube Q2 after passing through resistors R7 and R8 to obtain a reference voltage of-3V; the two paths of voltages are compared, and the result is led out from the collector of the transistor Q2 and then is connected into an emitter follower consisting of the transistor Q5, the diodes D1, D2, D3 and the resistor R9, and then is extracted to be negative electricity low-voltage waveforms with outputs of-4.2/-5V, so that input is provided for a post-stage circuit, and the improved level conversion circuit is stable in turning point, narrow in fuzzy area, good in temperature characteristic and high in speed.

The voltage generation circuit is shown in fig. 3, the power supply voltage is divided by resistors R10 and R11 to weaken the influence of power supply ripples and then is connected to a follower of a transistor Q6, because a diode voltage reduction circuit is not used, the temperature characteristic is also ensured, and the required voltage can be obtained by adjusting the resistance values of resistors R10, R11 and R12 to supply power for a communication unit and a power-on reset unit.

The communication unit comprises an 8-bit shift register and an 8-bit parallel converter, wherein each bit shift register is formed by cascading a plurality of D triggers consisting of two latches; when the serial clock falls from a high level to a low level, the data registered by the shift register moves forward by one bit, namely the input serial data is registered to the lowest bit of the shift register, and the parallel converter cascaded with the shift register latches the data and releases the data at the next high level;

the latch circuit structure is shown in fig. 4, and has the following functions: when the clock signal CLK jumps from high level to low level, the input data is transmitted via the transistors Q7 and Q9 to the cross latch formed by the transistors Q11 and Q12, and waits until the next clock falling edge to read in and latch the data again; as shown in fig. 5, the D flip-flop is formed by cascading two latches, where a positive output terminal and a negative output terminal of a first-stage latch are respectively connected to a positive input terminal and a negative input terminal of a second-stage parallel converter, and the difference is that clock signal terminals of the two-stage latches are inverted, that is, one of the two latches is a positive latch, and the other is a negative latch.

The structure of the power-on reset circuit is shown in fig. 6, when the circuit is powered on again after power failure, the output VS of the voltage generating circuit jumps from 0V, the lower plate of the capacitor C1 is charged to-5V immediately, the upper plate is charged to VS slowly due to the existence of the resistor R15 to generate a downward pulse, and then the downward pulse is changed into an upward pulse through the inverter N1, unnecessary burrs in the pulse are filtered out under the action of the resistor R16, the threshold of the reset signal is increased by a diode drop under the action of the diode D4 to increase stability, the reset signal is reflected on the transistor Q13 in a short time after power on, the transistor Q13 is turned on, the output of the serial converter is pulled to a low level, and then the serial converter is kept off all the time without affecting the normal work of the circuit, and the power-on reset function is completed.

The practical circuit simulation result shows that in the series-parallel conversion circuit with the stable level shifter provided by the utility model, the level shift circuit has stable turning points, controllable fuzzy areas, higher noise tolerance and faster speed; the voltage generated by the voltage generating circuit has small temperature drift, controllable load regulation rate and high power supply rejection ratio; the communication unit and the power-on reset can realize normal functions, and the power-on reset circuit has stable performance and high noise tolerance.

The above mentioned is only the preferred embodiment of the present invention, not as the further limitation of the present invention, and all the equivalent changes made by the contents of the specification and the drawings are within the protection scope of the present invention.

Claims

1. A serial-parallel conversion circuit with a stable level shifter is characterized by comprising a level shifting unit, a voltage generating unit, a communication unit and a power-on reset unit,

the input end of the level conversion unit is respectively connected with external TTL data, a clock CLK and a parallel clock DARY, and the output end of the level conversion unit is respectively connected with the communication unit and provides a DCFL serial port signal of input data and a clock for the communication unit; the output end of the voltage generation unit is respectively connected with the input ends of the communication unit and the power-on reset unit and supplies power to the communication unit and the power-on reset unit;

the communication unit comprises a plurality of shifting registers and a plurality of parallel converters, wherein the shifting registers are composed of D triggers, the parallel converters are composed of the D triggers, the shifting registers are used for receiving input DCFL data serial port signals, converting the serial port signals into parallel port signals and transmitting the parallel port signals to the parallel converters, and the parallel converters output the converted parallel port signals;

the input end of the power-on reset unit is connected with the output end of the communication unit and is used for realizing the function of level reset when the power is re-powered on after power failure.

2. The serial-parallel conversion circuit with the stable level converter as claimed IN claim 1, wherein the level conversion unit comprises a data input terminal IN, first to ninth resistors, first to fifth transistors, first to third diodes, a power supply VEE, a ground GND and a data output terminal OUT;

3. The serial-to-parallel conversion circuit with the stable level converter as claimed in claim 1, wherein the voltage generating unit comprises a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a sixth transistor Q6, a power supply VEE, a ground GND and a voltage output terminal VS;

4. The serial-to-parallel conversion circuit with the stable level converter as claimed in claim 1, wherein the communication unit comprises a bit shift register and a parallel converter, the parallel converter comprises D flip-flops, and the D flip-flops are formed by cascading two latches formed by a thirteenth resistor R13, a fourteenth resistor R14 and seventh to twelfth transistors; the shift register is formed by cascading a plurality of D triggers consisting of two latches;

5. The serial-to-parallel conversion circuit with the stable level converter as claimed in claim 1, wherein the power-on reset unit comprises a fifteenth R15, a sixteenth resistor R16, a first capacitor C1, a first inverter N1, a fourth diode D4 and a thirteenth transistor Q13;