CN211043568U - Testing device for semiconductor laser chip assembly - Google Patents
Testing device for semiconductor laser chip assembly Download PDFInfo
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- CN211043568U CN211043568U CN201920491340.7U CN201920491340U CN211043568U CN 211043568 U CN211043568 U CN 211043568U CN 201920491340 U CN201920491340 U CN 201920491340U CN 211043568 U CN211043568 U CN 211043568U
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Abstract
The utility model discloses a testing arrangement of semiconductor laser chip subassembly, including range upon range of TEC, support plate and the PCB board of installing on the base plate, it has a chip groove that supplies the chip embedding to open on the support plate, and this chip groove is located directly over the TEC, a plurality of probes that correspond with chip and TEC have on the PCB board, install a heat insulating board on the base plate, it has the thermal-insulated logical groove that supplies the TEC embedding to open on this heat insulating board, the heat insulating board top surface is equipped with a boss, the heat insulating board top surface in boss one side is installed to the support plate, and this boss is higher than support plate and chip, install a backing plate between boss and the PCB board, it has the through-hole that supplies the probe to pass through to open. The utility model has the advantages of rate of heating is fast, efficient, and the control by temperature change precision is high, and the test result of each chip receives the undulant influence of temperature less.
Description
Technical Field
The utility model relates to a testing arrangement of semiconductor laser chip subassembly belongs to chip processing technology field.
Background
Chip burn-in is an electrical stress test method that uses voltage and high temperature to accelerate device electrical failures, where the burn-in process essentially simulates running the entire life of the chip, since the electrical stimuli applied during the burn-in process reflect the worst case for the chip to work.
Burn-in testing can be used as a test of device reliability or as a production window to discover early failure of a device.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a testing arrangement of semiconductor laser chip subassembly, it has that rate of heating is fast, efficient, and the control by temperature change precision is high, and the test result of each chip receives the less advantage of the undulant influence of temperature.
In order to achieve the above purpose, the utility model adopts the technical scheme that: the utility model provides a semiconductor laser chip assembly's testing arrangement, includes range upon range of TEC, support plate and the PCB board of installing on the base plate, it has a chip groove that supplies the chip embedding to open on the support plate, and this chip groove is located the TEC directly over, the PCB board is last to have a plurality of probes that correspond with chip and TEC, install a heat insulating board on the base plate, it has the thermal-insulated logical groove that supplies the TEC embedding to open on this heat insulating board.
The further improved scheme in the technical scheme is as follows:
1. in the above scheme, the top surface of the heat insulation plate is provided with a boss, the carrier plate is mounted on the top surface of the heat insulation plate on one side of the boss, and the boss is higher than the carrier plate and the chip.
2. In the above scheme, the electric pin of the TEC is provided with an electric contact, and the top surface of the heat insulation plate is provided with an electric slot for inserting the electric contact.
3. In the scheme, a base plate is arranged between the boss and the PCB, and a through hole for the probe to pass through is formed in the base plate.
4. In the above scheme, the base plate is provided with the guide posts, and the heat insulation plate, the carrier plate and the base plate are provided with the guide holes for the insertion of the guide posts.
5. In the above scheme, the carrier plate comprises a bottom plate and a positioning plate, and the chip slot is provided with the positioning plate.
Because of above-mentioned technical scheme's application, compared with the prior art, the utility model have the following advantage:
1. the utility model discloses testing arrangement of semiconductor laser chip subassembly, it is including range upon range of TEC, support plate and the PCB board of installing on the base plate, it has a chip groove that supplies the chip embedding to open on the support plate, and this chip groove is located directly over the TEC, a plurality of probes that correspond with chip and TEC have on the PCB board, through install the TEC additional between base plate and PCB board, semiconductor cooler promptly to install the support plate that is used for placing the chip on the TEC, directly arrange single chip in the TEC that is used for heating the accuse temperature in, the TEC can the direct heating chip, and not only the rate of heating is fast, efficient, and the control by temperature change precision is high, and the test result of each chip receives the undulant influence of temperature less.
2. The utility model discloses semiconductor laser chip component's testing arrangement, install a heat insulating board on its base plate, it has the thermal-insulated logical groove that supplies the TEC embedding to open on this heat insulating board, through installing the TEC into the thermal-insulated passageway that has the heat-proof effect's heat insulating board, on the one hand, the heat that prevents the TEC through the heat insulating board produces dissipates to around, improve heating efficiency, on the other hand, through the setting of thermal-insulated passageway with the heating effect restriction of TEC in the chip groove department of support plate, make the control by temperature change precision of TEC higher, further reduce the influence of temperature fluctuation to the measuring accuracy.
3. The utility model discloses semiconductor laser chip assembly's testing arrangement, its heat insulating board top surface are equipped with a boss, the heat insulating board top surface at boss one side is installed to the support plate, and this boss is higher than support plate and chip, lifts the PCB board from the support plate top surface through setting up of boss, avoids it to shield the light that laser chip sent, influences laser chip's test.
Drawings
FIG. 1 is a schematic diagram of the overall structure of the testing device of the semiconductor laser chip assembly of the present invention;
fig. 2 is an exploded view of a testing apparatus for a semiconductor laser chip assembly.
In the above drawings: 1. a substrate; 101. a guide post; 102. a guide hole; 2. a heat insulation plate; 201. a heat insulation through groove; 202. a boss; 203. an electric connection groove; 3. TEC; 301. connecting a power pin; 302. connecting an electrical contact; 4. a carrier plate; 41. a chip slot; 401. a base plate; 402. positioning a plate; 5. a base plate; 501. a through hole; 6. a PCB board; 61. and (3) a probe.
Detailed Description
Example 1: a testing device for semiconductor laser chip assembly, referring to fig. 1-2, comprising a TEC3, a carrier plate 4 and a PCB 6 mounted on a substrate 1 in a stacked manner, wherein the carrier plate 4 is formed with a chip slot 41 for embedding a chip, the chip slot 41 is located directly above a TEC3, and the PCB 6 is formed with a plurality of probes 61 corresponding to the chip and the TEC 3.
The substrate 1 is provided with a heat insulation plate 2, and the heat insulation plate 2 is provided with a heat insulation through groove 201 for embedding the TEC 3; the top surface of the heat insulation board 2 is provided with a boss 202, the carrier board 4 is arranged on the top surface of the heat insulation board 2 at one side of the boss 202, and the boss 202 is higher than the carrier board 4 and the chip; the electric pin 301 of the TEC3 has an electric contact 302, and the top surface of the heat shield 2 has an electric slot 203 for the electric contact 302 to be inserted; a pad 5 is installed between the boss 202 and the PCB 6, and the pad 5 is provided with a through hole 501 for the probe 61 to pass through.
The base plate 1 is provided with guide posts 101, and the heat insulation plate 2, the carrier plate 4 and the backing plate 5 are provided with guide holes 102 for the guide posts 101 to be embedded in; the carrier plate 4 includes a bottom plate 401 and a positioning plate 402, and the chip slot 41 is opened on the positioning plate 402.
Example 2: a testing device for semiconductor laser chip assembly, referring to fig. 1-2, comprising a TEC3, a carrier plate 4 and a PCB 6 mounted on a substrate 1 in a stacked manner, wherein the carrier plate 4 is formed with a chip slot 41 for embedding a chip, the chip slot 41 is located directly above a TEC3, and the PCB 6 is formed with a plurality of probes 61 corresponding to the chip and the TEC 3.
The substrate 1 is provided with a heat insulation plate 2, and the heat insulation plate 2 is provided with a heat insulation through groove 201 for embedding the TEC 3; the top surface of the heat insulation board 2 is provided with a boss 202, the carrier board 4 is arranged on the top surface of the heat insulation board 2 at one side of the boss 202, and the boss 202 is higher than the carrier board 4 and the chip; a pad 5 is installed between the boss 202 and the PCB 6, and the pad 5 is provided with a through hole 501 for the probe 61 to pass through.
The base plate 1 is provided with guide posts 101, and the heat insulation plate 2, the carrier plate 4 and the backing plate 5 are provided with guide holes 102 for the guide posts 101 to be inserted into.
When the testing device of the semiconductor laser chip assembly is adopted, the TEC, namely the semiconductor refrigerator, is additionally arranged between the substrate and the PCB, the carrier plate for placing the chip is arranged on the TEC, and a single chip is directly placed on the TEC for heating and controlling the temperature, so that the TEC can directly heat the chip, the heating speed is high, the efficiency is high, the temperature control precision is high, and the testing result of each chip is less influenced by temperature fluctuation;
in addition, the TEC is installed in the heat insulation channel of the heat insulation plate with the heat insulation effect, on one hand, the heat generated by the TEC is prevented from being dissipated to the periphery through the heat insulation plate, the heating efficiency is improved, on the other hand, the TEC is limited at the chip groove of the carrier plate through the arrangement of the heat insulation channel, so that the temperature control precision of the TEC is higher, and the influence of temperature fluctuation on the test precision is further reduced;
in addition, the PCB is lifted away from the top surface of the carrier plate through the arrangement of the boss, so that the PCB is prevented from shielding light emitted by the laser chip and influencing the test of the laser chip.
The above embodiments are only for illustrating the technical concept and features of the present invention, and the purpose of the embodiments is to enable people skilled in the art to understand the contents of the present invention and to implement the present invention, which cannot limit the protection scope of the present invention. All equivalent changes and modifications made according to the spirit of the present invention should be covered by the protection scope of the present invention.
Claims (7)
1. A kind of testing device of the semiconductor laser chip assembly, characterized by that: the device comprises a TEC (3), a carrier plate (4) and a PCB (6), wherein the TEC, the carrier plate (4) and the PCB are stacked on a substrate (1), a chip groove (41) for embedding a chip is formed in the carrier plate (4), the chip groove (41) is located right above the TEC (3), and a plurality of probes (61) corresponding to the chip and the TEC (3) are arranged on the PCB (6).
2. The apparatus for testing a semiconductor laser chip assembly as claimed in claim 1, wherein: the heat insulation plate (2) is mounted on the substrate (1), and a heat insulation through groove (201) for embedding the TEC (3) is formed in the heat insulation plate (2).
3. The apparatus for testing a semiconductor laser chip assembly as claimed in claim 2, wherein: the top surface of the heat insulation plate (2) is provided with a boss (202), the carrier plate (4) is arranged on the top surface of the heat insulation plate (2) on one side of the boss (202), and the boss (202) is higher than the carrier plate (4) and the chip.
4. The apparatus for testing a semiconductor laser chip assembly as claimed in claim 2, wherein: an electric contact (302) is arranged on an electric pin (301) of the TEC (3), and an electric connecting groove (203) for embedding the electric contact (302) is formed in the top surface of the heat insulation plate (2).
5. The apparatus for testing a semiconductor laser chip assembly as claimed in claim 3, wherein: a backing plate (5) is arranged between the boss (202) and the PCB (6), and a through hole (501) for the probe (61) to pass through is formed in the backing plate (5).
6. The apparatus for testing a semiconductor laser chip assembly as claimed in claim 5, wherein: the base plate (1) is provided with guide columns (101), and the heat insulation plate (2), the carrier plate (4) and the base plate (5) are provided with guide holes (102) for the guide columns (101) to be embedded in.
7. The apparatus for testing a semiconductor laser chip assembly as claimed in claim 1, wherein: the carrier plate (4) comprises a bottom plate (401) and a positioning plate (402), and the chip groove (41) is provided with the positioning plate (402).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920491340.7U CN211043568U (en) | 2019-04-12 | 2019-04-12 | Testing device for semiconductor laser chip assembly |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920491340.7U CN211043568U (en) | 2019-04-12 | 2019-04-12 | Testing device for semiconductor laser chip assembly |
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| Publication Number | Publication Date |
|---|---|
| CN211043568U true CN211043568U (en) | 2020-07-17 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201920491340.7U Active CN211043568U (en) | 2019-04-12 | 2019-04-12 | Testing device for semiconductor laser chip assembly |
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| CN (1) | CN211043568U (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112276816A (en) * | 2020-10-20 | 2021-01-29 | 中北大学南通智能光机电研究院 | Conductive adhesive clamp for multiple chips |
| CN112902492A (en) * | 2021-02-02 | 2021-06-04 | 中国科学院空间应用工程与技术中心 | Mechanical-electrical integrated gas-liquid cooling device based on TEC |
| CN113406468A (en) * | 2021-06-17 | 2021-09-17 | 中国科学院半导体研究所 | Optoelectronic device test platform based on TEC |
| CN114113969A (en) * | 2020-08-28 | 2022-03-01 | 苏州联讯仪器有限公司 | Test system for laser chip |
| WO2022068166A1 (en) * | 2020-09-29 | 2022-04-07 | 苏州联讯仪器有限公司 | High-reliability laser chip test system |
| CN116626476A (en) * | 2023-07-26 | 2023-08-22 | 珠海市申科谱工业科技有限公司 | Laser chip probe testing mechanism |
-
2019
- 2019-04-12 CN CN201920491340.7U patent/CN211043568U/en active Active
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114113969A (en) * | 2020-08-28 | 2022-03-01 | 苏州联讯仪器有限公司 | Test system for laser chip |
| CN114113969B (en) * | 2020-08-28 | 2024-03-01 | 苏州联讯仪器股份有限公司 | Test system for laser chip |
| WO2022068166A1 (en) * | 2020-09-29 | 2022-04-07 | 苏州联讯仪器有限公司 | High-reliability laser chip test system |
| CN112276816A (en) * | 2020-10-20 | 2021-01-29 | 中北大学南通智能光机电研究院 | Conductive adhesive clamp for multiple chips |
| CN112902492A (en) * | 2021-02-02 | 2021-06-04 | 中国科学院空间应用工程与技术中心 | Mechanical-electrical integrated gas-liquid cooling device based on TEC |
| CN113406468A (en) * | 2021-06-17 | 2021-09-17 | 中国科学院半导体研究所 | Optoelectronic device test platform based on TEC |
| CN116626476A (en) * | 2023-07-26 | 2023-08-22 | 珠海市申科谱工业科技有限公司 | Laser chip probe testing mechanism |
| CN116626476B (en) * | 2023-07-26 | 2023-10-20 | 珠海市申科谱工业科技有限公司 | Laser chip probe testing mechanism |
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| GR01 | Patent grant | ||
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Address after: Building 5, No. 1508, Xiangjiang Road, Suzhou High-tech Zone, Suzhou City, Jiangsu Province 215129 Patentee after: Suzhou Lianxun Instrument Co.,Ltd. Address before: Building 5, No. 1508, Xiangjiang Road, High-tech Zone, Suzhou City, Jiangsu Province, 215011 Patentee before: STELIGHT INSTRUMENT Inc. |
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| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: Building 5, No. 1508, Xiangjiang Road, Suzhou High-tech Zone, Suzhou City, Jiangsu Province 215129 Patentee after: Suzhou Lianxun Instrument Co.,Ltd. Address before: Building 5, No. 1508, Xiangjiang Road, High-tech Zone, Suzhou City, Jiangsu Province, 215011 Patentee before: STELIGHT INSTRUMENT Inc. |