CN210072001U - High-efficiency test equipment for chip aging - Google Patents
High-efficiency test equipment for chip aging Download PDFInfo
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- CN210072001U CN210072001U CN201920442561.5U CN201920442561U CN210072001U CN 210072001 U CN210072001 U CN 210072001U CN 201920442561 U CN201920442561 U CN 201920442561U CN 210072001 U CN210072001 U CN 210072001U
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- 238000012360 testing method Methods 0.000 title claims abstract description 142
- 230000032683 aging Effects 0.000 title claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000005192 partition Methods 0.000 claims abstract description 23
- 238000001816 cooling Methods 0.000 claims description 38
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 26
- 239000000498 cooling water Substances 0.000 claims description 15
- 239000000969 carrier Substances 0.000 claims description 4
- 238000013522 software testing Methods 0.000 abstract description 5
- 238000000034 method Methods 0.000 description 4
- 238000009825 accumulation Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002372 labelling Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 239000008400 supply water Substances 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
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Abstract
The utility model discloses a high-efficiency test device for chip aging, which comprises a test loading platform, a connecting block and a control assembly, wherein a support plate is installed on the test loading platform, a plurality of chip grooves for embedding chips are formed on the support plate, a plurality of wires communicated with the chips are arranged on the support plate, the plurality of wires form an electric connector at one end of the support plate, a connecting port for inserting a power supply connector is formed on the connecting block, and the connecting block is electrically connected with the control assembly; the test platform comprises a test platform and is characterized in that two sides of the test platform are respectively provided with a mounting plate in parallel, the inner side walls of the two mounting plates are provided with a sliding groove, the support plate is mounted on a substrate, two sides of the substrate are embedded into the sliding groove, the test platform is provided with a plurality of partition plates around, the plurality of partition plates enclose a test cavity, one side of the test cavity is provided with a socket for the substrate to be inserted, and the end part of the substrate is provided with a baffle matched with the socket. The utility model discloses its asynchronous test that can realize a large amount of chips, and mutual noninterference, efficiency of software testing is higher.
Description
Technical Field
The utility model relates to a chip is ageing to use high-efficient test equipment belongs to chip test technical field.
Background
Chip burn-in is an electrical stress test method that uses voltage and high temperature to accelerate device electrical failures, where the burn-in process essentially simulates running the entire life of the chip, since the electrical stimuli applied during the burn-in process reflect the worst case for the chip to work.
The aging test can be used for detecting the reliability of a device or finding the early failure of the device as a production window, a device generally used for chip aging test works together with an external circuit board through a test socket, and because high-power lasers and chips, particularly lasers and chips above 1W, have larger heat productivity and are difficult to control the temperature, most of the existing aging test equipment adopts a single measurement mode to operate, so that the test efficiency is lower.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a chip is ageing to use high-efficient test equipment, its asynchronous test that can realize a large amount of chips, and mutual noninterference, efficiency of software testing is higher.
In order to achieve the above purpose, the utility model adopts the technical scheme that: a high-efficiency test device for chip aging comprises a test loading platform, a connecting block and a control assembly, wherein a support plate is arranged on the test loading platform, a plurality of chip grooves for embedding chips are formed in the support plate, a plurality of wires communicated with the chips are arranged on the support plate, an electric connector is formed at one end of the support plate by the plurality of wires, a connecting port for inserting the electric connector is formed in the connecting block, and the connecting block is electrically connected with the control assembly;
the test platform comprises a test platform and is characterized in that two mounting plates are respectively arranged on two sides of the test platform in parallel, a sliding groove is formed in the side wall of the inner side of each of the two mounting plates, a carrier plate is arranged on a substrate, two sides of the substrate are embedded into the sliding grooves, a plurality of partition plates are arranged around the test platform, a test cavity is defined by the plurality of partition plates, a socket for inserting the substrate is formed in one side of the test cavity, and a baffle plate matched with the socket is arranged at the end part of the substrate.
The further improved scheme in the technical scheme is as follows:
1. in the above scheme, be provided with a cooling box under the carrier plate, it has water inlet and delivery port to open on this cooling box, be provided with the cooling chamber that link up with water inlet, delivery port in the cooling box, water inlet and delivery port all lead to pipe and a cooling water circulation case intercommunication, the carrier plate lower surface still is provided with a heat-conducting plate, and this heat-conducting plate is used for being connected with cooling box upper surface contact.
2. In the above scheme, the number of the chip slots is 40.
3. In the above scheme, the chip slots of the first row and the last row are provided with corresponding marks.
4. In the above scheme, the carrier plates and the cooling boxes corresponding to the carrier plates are arranged in a plurality, and the plurality of cooling boxes are communicated with one cooling water circulation box.
5. In the above scheme, the number of the test carriers in one test chamber is two.
6. In the above scheme, the number of the cooling boxes in one test chamber is one.
7. In the above scheme, the partition plate is provided with a pipe hole through which a water supply pipe passes.
8. In the above scheme, a handle is installed on the baffle.
9. In the above scheme, the test cavities are arranged in a plurality and form a box structure.
Because of above-mentioned technical scheme's application, compared with the prior art, the utility model have the following advantage:
1. the high-efficiency test equipment for chip aging is characterized in that the carrier plate is provided with a plurality of wires communicated with the chips, the plurality of wires form an electric connector at one end of the carrier plate, the connecting block is provided with a connecting port for inserting the power supply connector, the connecting block is electrically connected with the control assembly, the density of the chips on the carrier plate is improved through the matching of the chip grooves on the carrier plate and the wires, the simultaneous test of a plurality of chips by one carrier plate is realized, the test efficiency is effectively improved, the consistency of the test environment of each chip can be ensured, the difference of the test results of different chips is reduced, and the chips are convenient for workers to disassemble and assemble.
2. According to the efficient test equipment for chip aging, the cooling box is arranged right below the carrier plate, the lower surface of the carrier plate is also provided with the heat conducting plate, the heat conducting plate is used for being in contact connection with the upper surface of the cooling box, and the cooling box is arranged below the carrier plate to take away heat generated by a chip in a test process, so that the heat accumulation of the chip can be avoided to influence the test result of the chip, the chip can be maintained in a stable temperature range, the temperature fluctuation is reduced, the consistency of a test environment is ensured, and the test precision is improved; furthermore, through the setting of cooling box, can eliminate the influence that many chips generate heat to the measuring accuracy to can use a support plate to test many chips simultaneously, effectively improve efficiency of software testing, can also guarantee the uniformity of every chip test environment, in order to reduce the difference of different chip test results, and the radiating effect of each part of support plate can be evenly distributed in the setting of heat-conducting plate, further improves the precision of test result.
3. According to the high-efficiency test equipment for chip aging, the sliding groove is formed in the inner side wall of the mounting plate, the two sides of the substrate are embedded into the sliding groove, the plurality of partition plates are arranged around the test carrier, and the plurality of partition plates enclose the test cavity, so that on one hand, the test cavity enclosed by the partition plates forms a relatively independent space to isolate the influence of the external environment, further improve the stability of the temperature of the chip on the carrier plate, and effectively improve the precision of a test result, on the other hand, the substrate with the carrier plate is slidably inserted into the test cavity, so that a worker can conveniently test and take out the carrier plate at any time, the test work of other carrier plates is not influenced, and the test efficiency is further improved.
4. The invention relates to a high-efficiency test device for chip aging, wherein a plurality of carrier plates and cooling boxes corresponding to the carrier plates are arranged, the cooling boxes are communicated with a cooling water circulation box, pipe holes for water inlet pipes and water outlet pipes to pass through are formed in a partition plate, the cooling water circulation box is used for supplying water for the cooling boxes, and the cooling water circulation box is isolated from a single test cavity by the partition plate, so that the space where the carrier plates are located is reduced by the carrier plates, the influence of the ambient temperature on the chips is reduced, the temperature control efficiency is higher, and the test precision and the test efficiency are further improved.
Drawings
FIG. 1 is a schematic diagram of the overall structure of the high-efficiency test equipment for chip aging according to the present invention;
FIG. 2 is a schematic view of a cooling water circulation tank in a rack;
FIG. 3 is a schematic diagram of a single test chamber and cooling water circulation tank configuration;
FIG. 4 is a schematic view of the internal structure of a single test chamber;
FIG. 5 is a schematic view of a connecting block portion;
FIG. 6 is a schematic structural view of a carrier and a substrate portion;
FIG. 7 is a partial cross-sectional view of a carrier plate and base plate portion;
fig. 8 is an enlarged view of a portion a of fig. 7.
In the above drawings: 1. testing the carrier; 11. a partition plate; 12. a test chamber; 13. mounting a plate; 14. a sliding groove; 15. a socket; 101. a control component; 2. a carrier plate; 21. a wire; 22. an electrical connector; 201. a chip slot; 202. labeling; 3. connecting blocks; 31. a connecting port; 34. a baffle plate; 303. a handle; 4. a cooling box; 401. a water inlet; 402. a water outlet; 403. a cooling water circulation tank; 5. a substrate; 52. a heat conducting plate.
Detailed Description
Example 1: an efficient test device for chip aging is disclosed, referring to fig. 1-8, and comprises a test carrier 1, a connection block 3 and a control assembly 101, wherein the control assembly 101 comprises a power module and a test module, the power module is used for supplying power to a chip, the test module is used for collecting and transmitting data of chip test, a carrier plate 2 is installed on the test carrier 1, a plurality of chip grooves 201 for embedding the chip are formed on the carrier plate 2, a plurality of wires 21 communicated with the chip are arranged on the carrier plate 2, an electric connector 22 is formed at one end of the carrier plate 2 by the plurality of wires 21, a connector 31 into which the power connector 22 is inserted is formed on the connection block 3, and the connection block 3 is electrically connected with the control assembly 101;
the testing device comprises a testing carrier 1, a mounting plate 13, a plurality of partition plates 11, a testing cavity 12, a socket 15 for inserting the substrate 5, a baffle plate 34 matched with the socket 15, a handle 303 and a plurality of testing cavities 12, wherein the mounting plate 13 is respectively arranged on two sides of the testing carrier 1 in parallel, the sliding groove 14 is formed in the side wall of the inner side of each of the two mounting plates 13, the carrier plate 2 is arranged on the substrate 5, the two sides of the substrate 5 are embedded into the sliding groove 14, the plurality of partition plates 11 are arranged around the testing carrier 1, the plurality of partition plates 11 enclose the testing cavity 12, the socket 15 for inserting the substrate 5 is formed in one side of the testing cavity 12.
The number of the chip grooves 201 is 40; the chip slots 201 are uniformly distributed in rows, and the carrier plates 2 at the positions of the chip slots 201 in the first row and the last row are provided with labels 202 corresponding to the chip slots 201;
the carrier plate 2 and the cooling boxes 4 corresponding to the carrier plate are provided in plurality, and the plurality of cooling boxes 4 are communicated with a cooling water circulation box 403; the number of the test carriers 1 in one test cavity 12 is two; the number of cooling boxes 4 in one of the test chambers 12 is one; the partition plate 11 is provided with a pipe hole through which a water supply pipe passes.
Example 2: an efficient test device for chip aging is disclosed, referring to fig. 1-8, and comprises a test carrier 1, a connection block 3 and a control assembly 101, wherein the control assembly 101 comprises a power module and a test module, the power module is used for supplying power to a chip, the test module is used for collecting and transmitting data of chip test, a carrier plate 2 is installed on the test carrier 1, a plurality of chip grooves 201 for embedding the chip are formed on the carrier plate 2, a plurality of wires 21 communicated with the chip are arranged on the carrier plate 2, an electric connector 22 is formed at one end of the carrier plate 2 by the plurality of wires 21, a connector 31 into which the power connector 22 is inserted is formed on the connection block 3, and the connection block 3 is electrically connected with the control assembly 101;
the testing device comprises a testing carrier 1, a mounting plate 13, a plurality of partition plates 11, a testing cavity 12, a socket 15 for inserting the substrate 5, a baffle plate 34 matched with the socket 15, a handle 303 and a plurality of testing cavities 12, wherein the mounting plate 13 is respectively arranged on two sides of the testing carrier 1 in parallel, the sliding groove 14 is formed in the side wall of the inner side of each of the two mounting plates 13, the carrier plate 2 is arranged on the substrate 5, the two sides of the substrate 5 are embedded into the sliding groove 14, the plurality of partition plates 11 are arranged around the testing carrier 1, the plurality of partition plates 11 enclose the testing cavity 12, the socket 15 for inserting the substrate 5 is formed in one side of the testing cavity 12.
A cooling box 4 is arranged right below the carrier plate 2, a water inlet 401 and a water outlet 402 are arranged on the cooling box 4, a cooling cavity communicated with the water inlet 401 and the water outlet 402 is arranged in the cooling box 4, the water inlet 401 and the water outlet 402 are both communicated with a cooling water circulation box 403 through water pipes, a heat conduction plate 52 is arranged on the lower surface of the carrier plate 2, and the heat conduction plate 52 is used for being in contact connection with the upper surface of the cooling box 4;
the number of the chip grooves 201 is 40; the chip slots 201 are uniformly distributed in rows, and the carrier plates 2 at the positions of the chip slots 201 in the first row and the last row are provided with labels 202 corresponding to the chip slots 201;
the carrier plate 2 and the cooling boxes 4 corresponding to the carrier plate are provided in plurality, and the plurality of cooling boxes 4 are communicated with a cooling water circulation box 403; the number of the test carriers 1 in one test cavity 12 is two; the number of cooling boxes 4 in one of the test chambers 12 is one; the partition plate 11 is provided with a pipe hole through which a water supply pipe passes.
When the high-efficiency test equipment for chip aging is adopted, the chip density on the carrier plate is improved through the matching of the chip grooves and the wires on the carrier plate, the fact that one carrier plate simultaneously tests a plurality of chips is achieved, the test efficiency is effectively improved, the consistency of the test environment of each chip can be guaranteed, the difference of test results of different chips is reduced, and the chips are convenient for workers to disassemble and assemble.
In addition, the cooling box is arranged below the carrier plate, so that heat generated by the chip in the test process is taken away, the test result of the chip can be prevented from being influenced by the heat accumulation of the chip, the chip can be maintained in a stable temperature range, the temperature fluctuation is reduced, the consistency of the test environment is ensured, and the test precision is improved; furthermore, through the setting of cooling box, can eliminate the influence that many chips generate heat to the measuring accuracy to can use a support plate to test many chips simultaneously, effectively improve efficiency of software testing, can also guarantee the uniformity of every chip test environment, in order to reduce the difference of different chip test results, and the radiating effect of each part of support plate can be evenly distributed in the setting of heat-conducting plate, further improves the precision of test result.
In addition, on the one hand, the test chamber that encloses through the baffle forms relatively independent space, and isolated external environment's influence further promotes the stability of chip temperature on the carrier plate, effectively improves the precision of test result, and on the other hand, slides the base plate that will have the carrier plate and pegs graft in the test chamber, makes things convenient for the staff to test at any time and takes out the carrier plate, and can not influence the test work of all the other carrier plates, further improves efficiency of software testing.
In addition, a cooling water circulation box is arranged to supply water for the plurality of cooling boxes, and the cooling water circulation box is isolated from a single test cavity by the aid of the partition plates, so that the space where the carrier plate is located is reduced, the influence of the ambient temperature on the chip is reduced, the temperature control efficiency is higher, and the test precision and the test efficiency are further improved.
The above embodiments are only for illustrating the technical concept and features of the present invention, and the purpose of the embodiments is to enable people skilled in the art to understand the contents of the present invention and to implement the present invention, which cannot limit the protection scope of the present invention. All equivalent changes and modifications made according to the spirit of the present invention should be covered by the protection scope of the present invention.
Claims (9)
1. The utility model provides a chip is ageing with high-efficient test equipment which characterized in that: the test device comprises a test carrier (1), a connecting block (3) and a control assembly (101), wherein a carrier plate (2) is installed on the test carrier (1), a plurality of chip grooves (201) for embedding chips are formed in the carrier plate (2), a plurality of wires (21) communicated with the chips are arranged on the carrier plate (2), an electric connector (22) is formed at one end of the carrier plate (2) by the plurality of wires (21), a connector (31) for inserting the power connector (22) is formed in the connecting block (3), and the connecting block (3) is electrically connected with the control assembly (101);
the test platform is characterized in that two sides of the test platform (1) are respectively provided with a mounting plate (13) in parallel, the inner side walls of the two mounting plates (13) are provided with a sliding groove (14), the carrier plate (2) is mounted on a substrate (5), two sides of the substrate (5) are embedded into the sliding groove (14), the periphery of the test platform (1) is provided with a plurality of partition plates (11), the plurality of partition plates (11) enclose a test cavity (12), one side of the test cavity (12) is provided with a socket (15) for the substrate (5) to be inserted into, the end part of the substrate (5) is provided with a baffle plate (34) matched with the socket (15), a cooling box (4) is arranged under the carrier plate (2), the cooling box (4) is provided with a water inlet (401) and a water outlet (402), and a cooling cavity communicated with the water inlet (401) and the water outlet (402) is arranged in the cooling, the water inlet (401) and the water outlet (402) are communicated with a cooling water circulation box (403) through water pipes, the lower surface of the carrier plate (2) is further provided with a heat-conducting plate (52), and the heat-conducting plate (52) is used for being in contact connection with the upper surface of the cooling box (4).
2. The efficient test apparatus for chip burn-in according to claim 1, wherein: the number of the chip grooves (201) is 40.
3. The efficient test apparatus for chip burn-in according to claim 2, wherein: the chip grooves (201) are uniformly distributed in rows, and the carrier plates (2) at the positions of the first row and the last row of chip grooves (201) are provided with marks (202) corresponding to the chip grooves (201).
4. The efficient test apparatus for chip burn-in according to claim 1, wherein: the carrier plate (2) and the cooling boxes (4) corresponding to the carrier plate are arranged in a plurality, and the plurality of cooling boxes (4) are communicated with a cooling water circulation box (403).
5. The efficient test apparatus for chip burn-in according to claim 4, wherein: the number of the test carriers (1) in one test cavity (12) is two.
6. The efficient test apparatus for chip burn-in according to claim 5, wherein: the number of the cooling boxes (4) in one test cavity (12) is one.
7. The efficient test apparatus for chip burn-in of claim 6, wherein: the partition plate (11) is provided with a pipe hole through which a water supply pipe passes.
8. The efficient test apparatus for chip burn-in according to claim 1, wherein: and a handle (303) is arranged on the baffle plate (34).
9. The efficient test apparatus for chip burn-in according to claim 1, wherein: the test chambers (12) are arranged in a plurality and form a box structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920442561.5U CN210072001U (en) | 2019-04-03 | 2019-04-03 | High-efficiency test equipment for chip aging |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920442561.5U CN210072001U (en) | 2019-04-03 | 2019-04-03 | High-efficiency test equipment for chip aging |
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| CN210072001U true CN210072001U (en) | 2020-02-14 |
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| CN201920442561.5U Active CN210072001U (en) | 2019-04-03 | 2019-04-03 | High-efficiency test equipment for chip aging |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113777475A (en) * | 2021-11-15 | 2021-12-10 | 枣庄智博智能科技有限公司 | Automatic test platform and test method for aging of electronic product |
| WO2022068166A1 (en) * | 2020-09-29 | 2022-04-07 | 苏州联讯仪器有限公司 | High-reliability laser chip test system |
| CN116359715A (en) * | 2023-05-26 | 2023-06-30 | 南京芯驰半导体科技有限公司 | Multi-chip testing method and device, electronic equipment and storage medium |
-
2019
- 2019-04-03 CN CN201920442561.5U patent/CN210072001U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022068166A1 (en) * | 2020-09-29 | 2022-04-07 | 苏州联讯仪器有限公司 | High-reliability laser chip test system |
| CN113777475A (en) * | 2021-11-15 | 2021-12-10 | 枣庄智博智能科技有限公司 | Automatic test platform and test method for aging of electronic product |
| CN113777475B (en) * | 2021-11-15 | 2022-01-25 | 枣庄智博智能科技有限公司 | Automatic test platform and test method for aging of electronic product |
| CN116359715A (en) * | 2023-05-26 | 2023-06-30 | 南京芯驰半导体科技有限公司 | Multi-chip testing method and device, electronic equipment and storage medium |
| CN116359715B (en) * | 2023-05-26 | 2023-11-03 | 南京芯驰半导体科技有限公司 | Multi-chip testing method and device, electronic equipment and storage medium |
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Address after: Building 5, No. 1508, Xiangjiang Road, Suzhou High-tech Zone, Suzhou City, Jiangsu Province 215129 Patentee after: Suzhou Lianxun Instrument Co.,Ltd. Address before: Building 1, No. 1508 Xiangjiang Road, High tech Zone, Suzhou City, Jiangsu Province, 215000, China Post code: 215011 Patentee before: STELIGHT INSTRUMENT Inc. |