CN210575913U - 一种分拣倒装芯片的封盖平衡性填充封装结构 - Google Patents

一种分拣倒装芯片的封盖平衡性填充封装结构 Download PDF

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CN210575913U
CN210575913U CN201921850773.3U CN201921850773U CN210575913U CN 210575913 U CN210575913 U CN 210575913U CN 201921850773 U CN201921850773 U CN 201921850773U CN 210575913 U CN210575913 U CN 210575913U
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flip chip
metal cover
substrate
heat
silicon
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阳芳芳
陆海琴
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Taiji Semiconductor Suzhou Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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Abstract

本实用新型涉及一种分拣倒装芯片的封盖平衡性填充封装结构，包含基板、倒装芯片、硅垫片和金属盖，金属盖焊接在基板上，倒装芯片位于金属盖内；倒装芯片与基板之间设置填充胶，倒装芯片背面的左右两侧上均设置有硅垫片；硅垫片的上下两侧均通过导热粘接层与金属盖盒倒装芯片粘连；本方案采用上下双层导热界面胶与左右两块硅垫片相结合的结构，保证最小散热接触面积，也保证金属盖粘贴时左右平衡无位置偏移，最终实现散热优良的封盖产品封装；导热界面胶的散热系数为3.4W/Mk，硅垫片的散热系数为149W/mK，实现了热量从薄型分拣倒装芯片到金属盖的快速传递，同时满足客户对封装类型的个性化追求。

Description

一种分拣倒装芯片的封盖平衡性填充封装结构
技术领域
本实用新型涉及一种分拣倒装芯片的封盖平衡性填充封装结构，属于集成电路倒装芯片封装技术领域。
背景技术
芯片倒装焊接在基板或其他载板上时，一般需要在芯片凸块（bump）间埋入底部填充胶（underfiller），金属盖（Lid cover）底端通过粘接剂（adhensive）强力连接在基板或其他载板上予以支撑；金属盖的腔体顶端通过界面散热材料（TIM胶）连通到芯片背面（非电性能面）实现热传导，然后植球，切割成形。
而当分拣倒装芯片的厚度小于500μm，常规金属盖腔体深度高于800μm时，正常刷界面散热胶无法完全填满最小约300μm，甚至更大的间隙空间，并实现高效散热；从而只能采用塑封（EMC）类FCBGA封装，不能满足客户对封装形式的个性化要求；特别是在金属盖共享模具，统一大小，以保证成本最小化的前提下。
实用新型内容
本实用新型目的是为了克服现有技术的不足而提供一种分拣倒装芯片的封盖平衡性填充封装结构。
为达到上述目的，本实用新型采用的技术方案是：一种分拣倒装芯片的封盖平衡性填充封装结构，包含基板、倒装芯片、硅垫片和金属盖，金属盖的边框通过焊接剂焊接在基板上，倒装芯片位于金属盖内；所述倒装芯片的正面具有多个凸块，倒装芯片与基板之间设置填充胶，倒装芯片背面的左右两侧上均设置有硅垫片；所述硅垫片通过其下侧的下导热粘接层粘贴在倒装芯片的背面，硅垫片的上侧通过上导热粘接层与金属盖粘连。
优选的，所述填充胶充满倒装芯片与基板之间的间隙，以及凸块与凸块之间的间隙。
优选的，所述下导热粘接层和上导热粘接层均由界面散热胶点涂形成。
优选的，所述基板的底部焊有锡球。
由于上述技术方案的运用，本实用新型与现有技术相比具有下列优点：
本方案采用上下双层导热界面胶与左右两块硅垫片相结合的结构，保证最小散热接触面积，也保证金属盖粘贴时左右平衡无位置偏移，最终实现散热优良的封盖产品封装；导热界面胶的散热系数为3.4W/Mk，硅垫片的散热系数为149W/mK，实现了热量从薄型分拣倒装芯片到金属盖的快速传递，同时满足客户对封装类型的个性化追求。
附图说明
下面结合附图对本实用新型技术方案作进一步说明：
附图1为本实用新型所述的一种分拣倒装芯片的封盖平衡性填充封装结构的示意图；
附图2为本实用新型所述的加工过程的第一步示意图；
附图3为本实用新型所述的加工过程的第二步示意图；
附图4为本实用新型所述的加工过程的第三步示意图；
附图5为本实用新型所述的加工过程的第四步示意图；
附图6为本实用新型所述的加工过程的第五步示意图；
附图7为本实用新型所述的加工过程的第六步示意图；
附图8为本实用新型所述的加工过程的第七步示意图；
附图9为本实用新型所述的加工过程的第八步示意图；
附图10为本实用新型所述的加工过程的第九步示意图。
具体实施方式
下面结合附图及具体实施例对本实用新型作进一步的详细说明。
如图1所示，本实用新型所述的一种分拣倒装芯片的封盖平衡性填充封装结构，包含基板11、倒装芯片12和金属盖7，基板11的底部焊有锡球9，金属盖7的边框通过焊接剂6焊接在基板11上，倒装芯片12位于金属盖7内；所述倒装芯片12的正面具有多个凸块，倒装芯片12与基板11之间设置填充胶2，填充胶2充满倒装芯片12与基板11之间的间隙，以及凸块与凸块之间的间隙；所述倒装芯片12背面的左右两侧上均设置有硅垫片4，硅垫片4通过其下侧的下导热粘接层3粘贴在倒装芯片12的背面，硅垫片4的上侧通过上导热粘接层5与金属盖7粘连，下导热粘接层3和上导热粘接层5均由点涂的界面散热胶形成。
此种分拣倒装芯片的封盖平衡性填充封装结构，主要为实现热量从薄型分拣倒装芯片到金属盖的快速传递，保证最小散热接触面积，并保证金属盖粘贴时左右平衡无位置偏移，最终实现散热优良的封盖产品封装。
如图2-10所示，该封装结构的加工过程如下：
第一步：芯片倒装焊接；
将薄型分拣芯片倒装在基板或其他载板上,实现信号的100%对应连接。
第二步：芯片底部填充；
通过虹吸现象使底部填充材料布满薄型分拣芯片与基板或其他载板的全部间隙，并固化以增强芯片凸块与基板焊盘的连接牢固度。
第三步：第一次点涂界面散热胶；
将界面散热胶均匀点涂在倒装芯片背面的两个短边，保证相近的点胶宽度和相同的点胶量，之后送进烘箱固化，形成两侧的下导热粘接层。
第四步：贴硅垫片并烘烤；
将硅垫片通过下导热粘接层粘贴在倒装芯片背面的两个短边上，保证两侧具有相同的压合高度。
第五步：第二次点涂界面散热胶；
将界面散热胶分别点涂在左右两边的硅垫片上，保证相近的点胶宽度和相同的点胶量，形成上导热粘接层。
第六步：点涂焊接剂；
将焊接剂点涂在基板或其他载板的环形贴盖区，保证均匀BLT及一致焊接宽度。
第七步：粘贴金属盖；
将金属盖对准基板或其他载板的环形贴盖区，即焊接剂点涂区，并控制位移和压合高度。
第八步：全固化；
将完成金属盖压合的半成品放入烘箱81中，并填充压块82，之后烘烤使整体全固化。
第九步：植球；
将锡球焊接在基板或其他载板的球垫（ball pad）上，完成芯片信号单元通过基板到锡球的有效连通。
第十步：切单；
使用切刀将整板产品切割成单颗单元。
以上仅是本实用新型的具体应用范例，对本实用新型的保护范围不构成任何限制。凡采用等同变换或者等效替换而形成的技术方案，均落在本实用新型权利保护范围之内。

Claims (4)

1.一种分拣倒装芯片的封盖平衡性填充封装结构，其特征在于：包含基板（11）、倒装芯片（12）、硅垫片（4）和金属盖（7），金属盖（7）的边框通过焊接剂（6）焊接在基板（11）上，倒装芯片（12）位于金属盖（7）内；所述倒装芯片（12）的正面具有多个凸块，倒装芯片（12）与基板（11）之间设置填充胶（2），倒装芯片（12）背面的左右两侧上均设置有硅垫片（4）；所述硅垫片（4）通过其下侧的下导热粘接层（3）粘贴在倒装芯片（12）的背面，硅垫片（4）的上侧通过上导热粘接层（5）与金属盖（7）粘连。
2.根据权利要求1所述的分拣倒装芯片的封盖平衡性填充封装结构，其特征在于：所述填充胶（2）充满倒装芯片（12）与基板（11）之间的间隙，以及凸块与凸块之间的间隙。
3.根据权利要求1所述的分拣倒装芯片的封盖平衡性填充封装结构，其特征在于：所述下导热粘接层（3）和上导热粘接层（5）均由界面散热胶点涂形成。
4.根据权利要求1所述的分拣倒装芯片的封盖平衡性填充封装结构，其特征在于：所述基板（11）的底部焊有锡球（9）。
CN201921850773.3U 2019-10-31 2019-10-31 一种分拣倒装芯片的封盖平衡性填充封装结构 Active CN210575913U (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110767617A (zh) * 2019-10-31 2020-02-07 太极半导体（苏州）有限公司 一种分拣倒装芯片的封盖平衡性填充封装结构及工艺

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110767617A (zh) * 2019-10-31 2020-02-07 太极半导体（苏州）有限公司 一种分拣倒装芯片的封盖平衡性填充封装结构及工艺

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