CN209197769U - Sine and cosine encoder signal processing apparatus and sine and cosine encoder - Google Patents
Sine and cosine encoder signal processing apparatus and sine and cosine encoder Download PDFInfo
- Publication number
- CN209197769U CN209197769U CN201822195505.4U CN201822195505U CN209197769U CN 209197769 U CN209197769 U CN 209197769U CN 201822195505 U CN201822195505 U CN 201822195505U CN 209197769 U CN209197769 U CN 209197769U
- Authority
- CN
- China
- Prior art keywords
- signal
- input terminal
- circuit
- adjustment
- sine
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Transmission And Conversion Of Sensor Element Output (AREA)
Abstract
The utility model provides a kind of sine and cosine encoder signal processing apparatus and sine and cosine encoder, the sine and cosine encoder signal processing apparatus, including processor and adjustment circuit；Wherein: the input terminal pin of the processor connects A, B, Z signal of the sine and cosine encoder, and the signal offset and signal amplification factor of A, B, Z signal are exported by the output pin of the processor；The input terminal of the adjustment circuit is connected to the output pin of the processor, and according to A, B, Z signal, A, B, Z signal signal offset and signal amplification factor output adjustment after A, B, Z signal.The automated production of sine and cosine coding may be implemented by processor, adjustment circuit and filter circuit for the utility model, improve the production efficiency of sine and cosine encoder, reduce the influence for portraying error to code device signal due to rigging error and code-disc.
Description
Technical field
The utility model embodiment is related to encoder field, more specifically to a kind of positive sine and cosine encoder signal
Processing unit and sine and cosine encoder.
Background technique
Sine and cosine encoder is a kind of widely used sensor of automatic field, thin by carrying out to cosine and sine signal
Point, the function of higher resolution encoder may be implemented, sine and cosine encoder typically contains A, B, Z, C, D signal, and wherein A, B believe
Number resolution ratio can be relatively high, generally can 1024 or 2048 resolution ratio, Z signal is that encoder often rotates a circle generation one Z letter
Number, C, D signal are that encoder often rotates a circle and generates C the and D signal of a cycle, and A, B, Z signal are generally by array light
The mode of battery generates, and C, D signal are generated by the involute code channel on code-disc.
The adjustment of above-mentioned A, B, Z, C, D signal is adjusted using potentiometer, but potentiometer higher cost, and in production process
Adjustment it is more complicated；Wherein, the quality of C, D signal for code-disc portray quality, installation accuracy, production environment have it is very big
It relies on.
Utility model content
The utility model embodiment provides a kind of sine and cosine encoder signal processing apparatus and sine and cosine encoder, it is intended to
The adjustment for solving A, B, Z, C, D signal in existing sine and cosine encoder is adjusted using potentiometer, but potentiometer higher cost, and
Adjustment in production process is more complicated；Wherein, the quality of C, D signal portrays quality, installation accuracy, production ring for code-disc
There is the problem of very big dependence in border.
The technical solution that the utility model embodiment solves above-mentioned technical problem is to provide a kind of sine and cosine encoder signal
Processing unit, including processor and adjustment circuit；Wherein: the input terminal pin of the processor connects the sine and cosine encoder
A, B, Z signal, and the signal offset of A, B, Z signal is exported by the output pin of the processor and signal is put
Big multiple；The input terminal of the adjustment circuit is connected to the output pin of the processor, and according to A, B, Z signal,
The signal offset of A, B, Z signal and A, B, Z signal after signal amplification factor output adjustment.
In sine and cosine encoder signal processing apparatus described in the utility model embodiment, the adjustment circuit includes the
One adjustment sub-circuit, first group of input terminal pin of the processor are connected to the a-signal of the sine and cosine encoder, and described
The output pin of processor includes a-signal offset output pin and a-signal amplification factor output pin；The first adjustment
Sub-circuit includes signal input terminal, signal offset input terminal and signal amplification factor input terminal, and described first
The signal input terminal for adjusting sub-circuit connects the a-signal, the signal offset input terminal of the first adjustment sub-circuit
It is connected to the a-signal offset output pin, the signal amplification factor input terminal of the first adjustment sub-circuit is connected to
The a-signal amplification factor output pin；
The adjustment circuit includes second adjustment sub-circuit, and second group of input terminal pin of the processor is connected to described
The B signal of sine and cosine encoder, and the output pin of the processor includes that B signal offset output pin and B signal are put
Big multiple output pin；The second adjustment sub-circuit includes signal input terminal, signal offset input terminal and signal
Amplification factor input terminal, and the signal input terminal of the second adjustment sub-circuit connects the B signal, the second adjustment
The signal offset input terminal of sub-circuit is connected to the B signal offset output pin, the second adjustment sub-circuit
Signal amplification factor input terminal is connected to the B signal amplification factor output pin；
The adjustment circuit includes third adjustment sub-circuit, and the third group input terminal pin of the processor is connected to described
The Z signal of sine and cosine encoder, and the output pin of the processor includes that Z signal offset output pin and Z signal are put
Big multiple output pin；The third adjustment sub-circuit includes signal input terminal, signal offset input terminal and signal
Amplification factor input terminal, and the signal input terminal of third adjustment sub-circuit connects the Z signal, the third adjustment
The signal offset input terminal of sub-circuit is connected to the Z signal offset output pin, the third adjustment sub-circuit
Signal amplification factor input terminal is connected to the Z signal amplification factor output pin.
In sine and cosine encoder signal processing apparatus described in the utility model embodiment, the first adjustment electricity
Road, second adjustment sub-circuit and third adjust sub-circuit circuit topology having the same.
In sine and cosine encoder signal processing apparatus described in the utility model embodiment, the first adjustment electricity
Each of road, second adjustment sub-circuit and third adjustment sub-circuit include that signal offset adjustment unit and signal amplify
The input terminal of multiple adjustment unit, the signal offset adjustment unit connects the signal input terminal and signal offset
Input terminal, the output end of the signal offset adjustment unit and the signal amplification factor input terminal are connected to the letter
The input terminal of number amplification factor adjustment unit, and pass through the signal after the signal amplification factor adjustment unit output adjustment.
In sine and cosine encoder signal processing apparatus described in the utility model embodiment, the signal offset adjustment
Unit includes the first operational amplifier, first input end, the second input terminal, third input terminal, first resistor, second resistance, the
Three resistance, the 4th resistance and first capacitor；Wherein, the first input end and second input terminal are connected respectively to described
Signal input terminal, and the same of first operational amplifier is connected to via the first resistor and the second resistance respectively
Phase input terminal and inverting input terminal；Third input terminal is connected to the signal offset input terminal, and via the third electricity
Resistance and the first capacitor are connected to the inverting input terminal of first operational amplifier；The reverse phase of first operational amplifier
Input terminal is connected to the output end of first operational amplifier via the 4th resistance, first operational amplifier it is defeated
Outlet is connected to the output end of the signal offset adjustment unit.
In sine and cosine encoder signal processing apparatus described in the utility model embodiment, the signal amplification factor tune
Whole unit includes second operational amplifier, the 4th input terminal, the 5th input terminal, the 5th resistance, the 6th resistance and the 7th resistance；
Wherein, the 4th input terminal connects the output end of the signal offset adjustment unit, and connects via the 5th resistance
To the non-inverting input terminal of the second operational amplifier, the inverting input terminal of the second operational amplifier is via the 6th electricity
Resistance is connected to low level；5th input terminal is connected respectively to the signal amplification factor input terminal and second operation
The inverting input terminal of the inverting input terminal of amplifier, the second operational amplifier is connected to described via the 7th resistance
The output end of two operational amplifiers, the output end of the second operational amplifier are connected to the signal amplification factor adjustment unit
Output end.
In sine and cosine encoder signal processing apparatus described in the utility model embodiment, the signal processing apparatus packet
The first filter circuit is included, the 4th group of input terminal pin of the processor is connected to the C signal of the sine and cosine encoder, and institute
The output pin for stating processor includes C signal PWM output pin；First filter circuit includes PWM input terminal, and institute
The PWM input terminal for stating the first filter circuit is connected to the C signal PWM output pin；
The signal processing apparatus includes the second filter circuit, and the 5th group of input terminal pin of the processor is connected to institute
The D signal of sine and cosine encoder is stated, and the output pin of the processor includes D signal PWM output pin；Second filter
Wave circuit includes PWM input terminal, and the PWM input terminal of second filter circuit is connected to the D signal PWM output and draws
Foot.
In sine and cosine encoder signal processing apparatus described in the utility model embodiment, first filter circuit and
Second filter circuit circuit topology having the same.
In sine and cosine encoder signal processing apparatus described in the utility model embodiment, first filter circuit or
Second filter circuit includes third operational amplifier, the 6th input terminal, the 8th resistance, the 9th resistance, the tenth resistance, the second electricity
Appearance, third capacitor and the 4th capacitor；Wherein, the 6th input terminal connects the PWM input terminal, and via the described 8th
Resistance and the 9th resistance are connected to the non-inverting input terminal of the third operational amplifier, the third operational amplifier it is same mutually defeated
Enter end via second capacitance connection to low level；The tie point of 8th resistance and the 9th resistance is via the third electricity
Hold the output end for being connected to the third operational amplifier；Tenth resistance and the 4th capacitor are connected in described in parallel
Between the inverting input terminal of three operational amplifiers and the output end of the third operational amplifier, the third operational amplifier
Output end is connected to the output end of first filter circuit.
The utility model embodiment also provides a kind of sine and cosine encoder, including sine and cosine encoder signal as described above
Processing unit.
The sine and cosine encoder signal processing apparatus and sine and cosine encoder of the utility model embodiment have following skill
Art effect: the automated production of sine and cosine coding may be implemented by processor, adjustment circuit and filter circuit, improve just remaining
The production efficiency of string encoder reduces the influence for portraying error to code device signal due to rigging error and code-disc.
Detailed description of the invention
Fig. 1 is the schematic diagram of sine and cosine encoder signal processing apparatus provided by the embodiment of the utility model；
Fig. 2 is the first adjustment sub-circuit in sine and cosine encoder signal processing apparatus provided by the embodiment of the utility model
Schematic diagram；
Fig. 3 is second adjustment sub-circuit in sine and cosine encoder signal processing apparatus provided by the embodiment of the utility model
Schematic diagram；
Fig. 4 is that third adjusts sub-circuit in sine and cosine encoder signal processing apparatus provided by the embodiment of the utility model
Schematic diagram；
Fig. 5 is the first, second third tune in sine and cosine encoder signal processing apparatus provided by the embodiment of the utility model
Whole sub-circuit figure；
Fig. 6 is that the first filter circuit shows in sine and cosine encoder signal processing apparatus provided by the embodiment of the utility model
It is intended to；
Fig. 7 is that the second filter circuit shows in sine and cosine encoder signal processing apparatus provided by the embodiment of the utility model
It is intended to；
Fig. 8 is the first, second filtered electrical in sine and cosine encoder signal processing apparatus provided by the embodiment of the utility model
Lu Tu.
Specific embodiment
In order to make the purpose of the utility model, technical solutions and advantages more clearly understood, below in conjunction with attached drawing and implementation
Example, the present invention will be further described in detail.It should be appreciated that specific embodiment described herein is only used to explain
The utility model is not used to limit the utility model.
As shown in Figure 1, be the schematic diagram of sine and cosine encoder signal processing apparatus provided by the embodiment of the utility model, it should
Sine and cosine encoder signal processing apparatus is suitable for automatic field may be implemented more by being finely divided to cosine and sine signal
The function of high resolution encoder.The sine and cosine encoder signal processing apparatus specifically includes processor 1 and adjustment circuit 2；Its
In: A, B, Z signal of the input terminal pin connection sine and cosine encoder of processor 1, and it is defeated by the output pin of processor 1
The signal offset and signal amplification factor of A, B, Z signal out；The output end that the input terminal of adjustment circuit 2 is connected to processor draws
Foot, and according to A, B, Z signal, A, B, Z signal signal offset and signal amplification factor output adjustment after A, B, Z signal.
Sine and cosine encoder signal processing apparatus provided by the embodiment of the utility model can by processor and adjustment circuit
To realize the automated production of sine and cosine coding, the production efficiency of sine and cosine encoder is improved, is reduced due to rigging error
Influence of the error to code device signal is portrayed with code-disc.
Specifically, as shown in Fig. 2, above-mentioned adjustment circuit 2 includes the first adjustment sub-circuit 21, first group of processor 1 is defeated
Enter the a-signal for holding pin to be connected to sine and cosine encoder, a-signal offset and a-signal times magnification can get by processor 1
Number；And the output pin of processor 1 includes a-signal offset output pin and a-signal amplification factor output pin；First adjusts
Whole sub-circuit 21 includes signal input terminal, signal offset input terminal and signal amplification factor input terminal, and first
The signal input terminal for adjusting sub-circuit 21 connects a-signal, the signal offset input terminal connection of the first adjustment sub-circuit 21
Signal amplification factor input terminal to a-signal offset output pin, the first adjustment sub-circuit 21 is connected to a-signal times magnification
Number output pin.A-signal is deviated by the a-signal offset output pin and a-signal amplification factor output pin of processor 1
Amount and a-signal amplification factor be transferred to the first adjustment sub-circuit 21 signal offset input terminal and signal amplification factor it is defeated
Enter terminal；A-signal offset and a-signal amplification factor obtain a-signal adjusted to the first adjustment sub-circuit 21 based on the received.
As shown in figure 3, above-mentioned adjustment circuit 2 includes second adjustment sub-circuit 22, second group of input terminal pin of processor 1
It is connected to the B signal of sine and cosine encoder, B signal offset and B signal amplification factor can get by processor 1；And it handles
The output pin of device 1 includes B signal offset output pin and B signal amplification factor output pin；Second adjustment sub-circuit
22 include signal input terminal, signal offset input terminal and signal amplification factor input terminal, and second adjustment is electric
The signal input terminal on road 22 connects B signal, and it is inclined that the signal offset input terminal of second adjustment sub-circuit 22 is connected to B signal
Shifting amount output pin, the signal amplification factor input terminal of second adjustment sub-circuit are connected to B signal amplification factor output pin.
B signal offset and B signal are put by the B signal offset output pin and B signal amplification factor output pin of processor 1
Big multiple is transferred to the signal offset input terminal and signal amplification factor input terminal of second adjustment sub-circuit 22；Second
Adjusting sub-circuit 22, B signal offset and B signal amplification factor obtain B signal adjusted based on the received.
As shown in figure 4, above-mentioned adjustment circuit 2 includes that third adjusts sub-circuit 23, the third group input terminal pin of processor 1
It is connected to the Z signal of sine and cosine encoder, Z signal offset and Z signal amplification factor can get by processor 1；And it handles
The output pin of device 1 includes Z signal offset output pin and Z signal amplification factor output pin；Third adjusts sub-circuit
23 include signal input terminal, signal offset input terminal and signal amplification factor input terminal, and third adjustment is electric
The signal input terminal on road 23 connects Z signal, and it is inclined that the signal offset input terminal of third adjustment sub-circuit 23 is connected to Z signal
Shifting amount output pin, the signal amplification factor input terminal of third adjustment sub-circuit 23 are connected to the output of Z signal amplification factor and draw
Foot.Z signal offset and Z are believed by the Z signal offset output pin and Z signal amplification factor output pin of processor 1
Number amplification factor is transferred to the signal offset input terminal and signal amplification factor input terminal of third adjustment sub-circuit 23；
Third adjusts sub-circuit 23, and Z signal offset and Z signal amplification factor obtain Z signal adjusted based on the received.
The utility model embodiment adjusts sub-circuit by the first adjustment sub-circuit 21, second adjustment sub-circuit 22 and third
23 can make the signal offset of A, B, Z signal of sine and cosine encoder and signal amplification factor in the range of requiring.
Above-mentioned the first adjustment sub-circuit 21, second adjustment sub-circuit 22 and third adjustment sub-circuit 23 can electricity having the same
Road topology.
Specifically, as shown in figure 5, above-mentioned the first adjustment sub-circuit 21, second adjustment sub-circuit 22 and third adjustment
Each of circuit 23 all includes signal offset adjustment unit 24 and signal amplification factor adjustment unit 25, signal offset
The input terminal connection signal input terminal and signal offset input terminal of adjustment unit 24, signal offset adjustment unit 24
Output end and signal amplification factor input terminal be connected to the input terminal of signal amplification factor adjustment unit 25, and pass through signal
Signal after 25 output adjustment of amplification factor adjustment unit.
Above-mentioned signal offset adjustment unit 24 include the first operational amplifier 241, first input end, the second input terminal,
Third input terminal, first resistor R1, second resistance R2,3rd resistor R3, the 4th resistance R4 and first capacitor C1；Wherein,
One input terminal and the second input terminal are connected respectively to signal input terminal, as the a-signal of sine and cosine encoder differential signal A+/
A-, and the non-inverting input terminal and reverse phase of the first operational amplifier 241 are connected to via first resistor R1 and second resistance R2 respectively
Input terminal；Third input terminal is connected to signal offset input terminal, and is connected to via 3rd resistor R3 and first capacitor C1
The inverting input terminal of first operational amplifier 241；The inverting input terminal of first operational amplifier 241 is via the 4th resistance R4 connection
To the output end of the first operational amplifier 241, the output end of the first operational amplifier 241 is connected to signal offset adjustment unit
24 output end.
Above-mentioned signal amplification factor adjustment unit 25 includes second operational amplifier 251, the 4th input terminal, the 5th input
End, the 5th resistance R5, the 6th resistance R6 and the 7th resistance R7；Wherein, the 4th input terminal connection signal offset adjustment unit
24 output end, and it is connected to via the 5th resistance R5 the non-inverting input terminal of second operational amplifier 251, second operational amplifier
251 inverting input terminal is connected to low level via the 6th resistance R6；It is defeated that 5th input terminal is connected respectively to signal amplification factor
Enter the inverting input terminal of terminal and second operational amplifier 251, the inverting input terminal of second operational amplifier 251 is via the 7th electricity
Resistance R7 is connected to the output end of second operational amplifier 251, and the output end of second operational amplifier 251 is connected to signal times magnification
The output end of number adjustment unit 25.
The first adjustment sub-circuit 21, second adjustment sub-circuit 22 and third adjustment provided by the embodiment of the utility model
The circuit topology of circuit 23 is not limited only to foregoing circuit, and variable gain amplifier or D/A (digital-to-analogue conversion) can also be used to realize pair
The adjustment of A, B, Z signal of sine and cosine encoder.
As shown in fig. 6, said signal processing device includes the first filter circuit 3, the 4th group of input terminal pin of processor 1
It is connected to the C signal of sine and cosine encoder, C signal PWM can get by processor 1；And the output pin of processor 1 includes
C signal PWM output pin；First filter circuit 3 includes PWM input terminal, and the PWM input terminal of the first filter circuit 3 connects
It is connected to C signal PWM output pin.C signal PWM is transferred to the first filtered electrical by the C signal PWM output pin of processor 1
The PWM input terminal on road 3；C signal PWM obtains C signal adjusted to first filter circuit 3 based on the received.
As shown in fig. 7, said signal processing device includes the second filter circuit 4, the 5th group of input terminal pin of processor 1
It is connected to the D signal of sine and cosine encoder, D signal PWM can get by processor 1；And the output pin of processor 1 includes
D signal PWM output pin；Second filter circuit 4 includes PWM input terminal, and the PWM input terminal of the second filter circuit 4 connects
It is connected to D signal PWM output pin.D signal PWM is transferred to the second filtered electrical by the D signal PWM output pin of processor 1
The PWM input terminal on road 4；D signal PWM obtains D signal adjusted to second filter circuit 4 based on the received.
Above-mentioned first filter circuit 3 and the second filter circuit 4 can circuit topologies having the same.
Specifically, as shown in figure 8, above-mentioned first filter circuit 3 or the second filter circuit 4 include third operational amplifier,
6th input terminal, the 8th resistance R8, the 9th resistance R9, the tenth resistance R10, the second capacitor C2, the electricity of third capacitor C3 and the 4th
Hold C4；Wherein, the 6th input terminal connects PWM input terminal, and is connected to third fortune via the 8th resistance R8 and the 9th resistance R9
The non-inverting input terminal of amplifier is calculated, the non-inverting input terminal of third operational amplifier is connected to low level via the second capacitor C2；The
The tie point of eight resistance R8 and the 9th resistance R9 is connected to the output end of third operational amplifier via third capacitor C3；Tenth electricity
Resistance R10 and the 4th capacitor C4 is connected in the inverting input terminal of third operational amplifier and the output end of third operational amplifier in parallel
Between, the output end of third operational amplifier is connected to the output end of the first filter circuit.
Above-mentioned processor 1 synthesizes C, D signal of the sine and cosine encoder of input with A, B, Z signal of sine and cosine encoder
Individual pen absolute value signal be compared, and record deviation.When inputting C, D signal of sine and cosine encoder next time, processing
Device 1 can obtain C, D signal after A, B, Z signal correction by sine and cosine encoder by searching for the mode of table, in this way may be used
To improve the precision of C, D signal of sine and cosine encoder, reduce since rigging error and code-disc portray influence caused by error.
Certainly, processor 1 realizes C, D of sine and cosine encoder by the way of look-up table in the utility model embodiment
The correction of signal, is not limited to that, the schemes such as multinomial can also be used.
The utility model embodiment also provides a kind of sine and cosine encoder, including sine and cosine encoder signal as described above
Processing unit.
The preferable specific embodiment of the above, only the utility model, but the protection scope of the utility model is not
It is confined to this, anyone skilled in the art within the technical scope disclosed by the utility model, can readily occur in
Change or replacement, should be covered within the scope of the utility model.Therefore, the protection scope of the utility model should
It is subject to the protection scope in claims.
Claims (10)
1. a kind of sine and cosine encoder signal processing apparatus, which is characterized in that including processor and adjustment circuit；Wherein: described
The input terminal pin of processor connects A, B, Z signal of the sine and cosine encoder, and is drawn by the output end of the processor
Foot exports the signal offset and signal amplification factor of A, B, Z signal；The input terminal of the adjustment circuit is connected to described
The output pin of processor, and according to A, B, Z signal, the signal offset of A, B, Z signal and signal times magnification
A, B, Z signal after number output adjustment.
2. sine and cosine encoder signal processing apparatus according to claim 1, which is characterized in that the adjustment circuit includes
The first adjustment sub-circuit, first group of input terminal pin of the processor are connected to the a-signal of the sine and cosine encoder, and institute
The output pin for stating processor includes a-signal offset output pin and a-signal amplification factor output pin；Described first adjusts
Whole sub-circuit includes signal input terminal, signal offset input terminal and signal amplification factor input terminal, and described
The signal input terminal of one adjustment sub-circuit connects the a-signal, the signal offset input terminal of the first adjustment sub-circuit
Son is connected to the a-signal offset output pin, the signal amplification factor input terminal connection of the first adjustment sub-circuit
To the a-signal amplification factor output pin；
The adjustment circuit includes second adjustment sub-circuit, and second group of input terminal pin of the processor is connected to described just remaining
The B signal of string encoder, and the output pin of the processor includes B signal offset output pin and B signal times magnification
Number output pin；The second adjustment sub-circuit includes signal input terminal, signal offset input terminal and signal amplification
Multiple input terminal, and the signal input terminal of the second adjustment sub-circuit connects the B signal, the second adjustment electricity
The signal offset input terminal on road is connected to the B signal offset output pin, the signal of the second adjustment sub-circuit
Amplification factor input terminal is connected to the B signal amplification factor output pin；
The adjustment circuit includes third adjustment sub-circuit, and the third group input terminal pin of the processor is connected to described just remaining
The Z signal of string encoder, and the output pin of the processor includes Z signal offset output pin and Z signal times magnification
Number output pin；The third adjustment sub-circuit includes signal input terminal, signal offset input terminal and signal amplification
Multiple input terminal, and the signal input terminal of third adjustment sub-circuit connects the Z signal, the third adjustment son electricity
The signal offset input terminal on road is connected to the Z signal offset output pin, the signal of the third adjustment sub-circuit
Amplification factor input terminal is connected to the Z signal amplification factor output pin.
3. sine and cosine encoder signal processing apparatus according to claim 2, which is characterized in that the first adjustment electricity
Road, second adjustment sub-circuit and third adjust sub-circuit circuit topology having the same.
4. sine and cosine encoder signal processing apparatus according to claim 3, which is characterized in that the first adjustment electricity
Each of road, second adjustment sub-circuit and third adjustment sub-circuit include that signal offset adjustment unit and signal amplify
The input terminal of multiple adjustment unit, the signal offset adjustment unit connects the signal input terminal and signal offset
Input terminal, the output end of the signal offset adjustment unit and the signal amplification factor input terminal are connected to the letter
The input terminal of number amplification factor adjustment unit, and pass through the signal after the signal amplification factor adjustment unit output adjustment.
5. sine and cosine encoder signal processing apparatus according to claim 4, which is characterized in that the signal offset tune
Whole unit include the first operational amplifier, first input end, the second input terminal, third input terminal, first resistor, second resistance,
3rd resistor, the 4th resistance and first capacitor；Wherein, the first input end and second input terminal are connected respectively to institute
Signal input terminal is stated, and is connected to first operational amplifier via the first resistor and the second resistance respectively
Non-inverting input terminal and inverting input terminal；Third input terminal is connected to the signal offset input terminal, and via the third
Resistance and the first capacitor are connected to the inverting input terminal of first operational amplifier；First operational amplifier it is anti-
Phase input terminal is connected to the output end of first operational amplifier via the 4th resistance, first operational amplifier
Output end is connected to the output end of the signal offset adjustment unit.
6. sine and cosine encoder signal processing apparatus according to claim 5, which is characterized in that the signal amplification factor
Adjustment unit includes second operational amplifier, the 4th input terminal, the 5th input terminal, the 5th resistance, the 6th resistance and the 7th electricity
Resistance；Wherein, the 4th input terminal connects the output end of the signal offset adjustment unit, and connects via the 5th resistance
It is connected to the non-inverting input terminal of the second operational amplifier, the inverting input terminal of the second operational amplifier is via the described 6th
Resistance is connected to low level；5th input terminal is connected respectively to the signal amplification factor input terminal and second fortune
The inverting input terminal of amplifier is calculated, the inverting input terminal of the second operational amplifier is connected to described via the 7th resistance
The output end of second operational amplifier, it is single that the output end of the second operational amplifier is connected to the signal amplification factor adjustment
The output end of member.
7. sine and cosine encoder signal processing apparatus according to claim 1, which is characterized in that the signal processing apparatus
Including the first filter circuit, the 4th group of input terminal pin of the processor is connected to the C signal of the sine and cosine encoder, and
The output pin of the processor includes C signal PWM output pin；First filter circuit includes PWM input terminal, and
The PWM input terminal of first filter circuit is connected to the C signal PWM output pin；
The signal processing apparatus include the second filter circuit, the 5th group of input terminal pin of the processor be connected to it is described just
The D signal of cosine encoder, and the output pin of the processor includes D signal PWM output pin；Second filtered electrical
Road includes PWM input terminal, and the PWM input terminal of second filter circuit is connected to the D signal PWM output pin.
8. sine and cosine encoder signal processing apparatus according to claim 7, which is characterized in that first filter circuit
With the second filter circuit circuit topology having the same.
9. sine and cosine encoder signal processing apparatus according to claim 8, which is characterized in that first filter circuit
Or second filter circuit include third operational amplifier, the 6th input terminal, the 8th resistance, the 9th resistance, the tenth resistance, second electricity
Appearance, third capacitor and the 4th capacitor；Wherein, the 6th input terminal connects the PWM input terminal, and via the described 8th
Resistance and the 9th resistance are connected to the non-inverting input terminal of the third operational amplifier, the third operational amplifier it is same mutually defeated
Enter end via second capacitance connection to low level；The tie point of 8th resistance and the 9th resistance is via the third electricity
Hold the output end for being connected to the third operational amplifier；Tenth resistance and the 4th capacitor are connected in described in parallel
Between the inverting input terminal of three operational amplifiers and the output end of the third operational amplifier, the third operational amplifier
Output end is connected to the output end of first filter circuit.
10. a kind of sine and cosine encoder, which is characterized in that encoded including sine and cosine as claimed in any one of claims 1-9 wherein
Device signal processing apparatus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201822195505.4U CN209197769U (en) | 2018-12-25 | 2018-12-25 | Sine and cosine encoder signal processing apparatus and sine and cosine encoder |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201822195505.4U CN209197769U (en) | 2018-12-25 | 2018-12-25 | Sine and cosine encoder signal processing apparatus and sine and cosine encoder |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209197769U true CN209197769U (en) | 2019-08-02 |
Family
ID=67430372
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201822195505.4U Active CN209197769U (en) | 2018-12-25 | 2018-12-25 | Sine and cosine encoder signal processing apparatus and sine and cosine encoder |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN209197769U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111669153A (en) * | 2020-06-18 | 2020-09-15 | 长春汇通光电技术有限公司 | Circuit for improving resolution of sine and cosine encoder |
| CN113091774A (en) * | 2021-03-17 | 2021-07-09 | 陈权 | Sine and cosine coding method based on absolute value encoder |
-
2018
- 2018-12-25 CN CN201822195505.4U patent/CN209197769U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111669153A (en) * | 2020-06-18 | 2020-09-15 | 长春汇通光电技术有限公司 | Circuit for improving resolution of sine and cosine encoder |
| CN111669153B (en) * | 2020-06-18 | 2023-06-23 | 长春汇通光电技术有限公司 | Resolution improving circuit of sine and cosine encoder |
| CN113091774A (en) * | 2021-03-17 | 2021-07-09 | 陈权 | Sine and cosine coding method based on absolute value encoder |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103414442B (en) | High accuracy fully-differential amplifier based on wave chopping technology | |
| CN209197769U (en) | Sine and cosine encoder signal processing apparatus and sine and cosine encoder | |
| CN109884384B (en) | Signal acquisition circuit compatible with current and voltage input | |
| CN103532556A (en) | Axial angle signal-to-serial digital signal conversion circuit of single chip | |
| CN104330096B (en) | A kind of rectification building-out of measurement signal and the method and device of automatic Calibration | |
| CN108459645A (en) | Constant current control loop and electronic load | |
| CN112468103B (en) | Differential sampling circuit and method for improving common mode rejection ratio | |
| CN206531513U (en) | A kind of encoder signal processing circuit and frequency converter | |
| CN104734712B (en) | Analog-digital converter input stage | |
| CN1011844B (en) | Variable gain encoder apparatus and method | |
| CN207910761U (en) | A kind of high speed reference buffer circuit applied to high-speed AD converter | |
| CN103856170B (en) | Power-stage power supply noise error elimination method of H-bridge type digital D type power amplifier | |
| CN104811181A (en) | Current-to-voltage conversion circuit with input bias and active power filtering effects and current-to-voltage conversion method | |
| CN106505985B (en) | It is single-ended to differential conversion circuit and signal processing module | |
| CN101090267A (en) | High linearity wide input range changable gain single quadrant CMOS multiplier | |
| CN203965986U (en) | A kind of numerical control adjustable D. C regulated | |
| CN210225354U (en) | Isolated sampling circuit | |
| CN204559542U (en) | A kind of current-to-voltage converting circuit with inputting biased and active power filtering | |
| CN102868405B (en) | A kind of parallel analog-digital signal conversion device | |
| CN209803233U (en) | Signal acquisition circuit compatible with current and voltage input | |
| CN208174644U (en) | A kind of number tunable capacitor circuit | |
| CN206235914U (en) | A kind of programmable reference voltage generating circuit of fully differential | |
| CN107103929B (en) | Floating type HP memristor equivalent circuit with bipolar characteristic | |
| CN205986681U (en) | String ripples conversion recoverer | |
| CN202750073U (en) | Parallel analog-to-digital signal conversion apparatus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |