CN101090267A - High linearity wide input range changable gain single quadrant CMOS multiplier - Google Patents
High linearity wide input range changable gain single quadrant CMOS multiplier Download PDFInfo
- Publication number
- CN101090267A CN101090267A CN 200710142984 CN200710142984A CN101090267A CN 101090267 A CN101090267 A CN 101090267A CN 200710142984 CN200710142984 CN 200710142984 CN 200710142984 A CN200710142984 A CN 200710142984A CN 101090267 A CN101090267 A CN 101090267A
- Authority
- CN
- China
- Prior art keywords
- voltage
- current
- field effect
- effect transistor
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Amplifiers (AREA)
Abstract
This invention discloses a linear wide input sphere variable gain single quadrant CMOS multiplier including a first stage of voltage-current conversion circuit for receiving a first input voltage and outputting a first current, a first stage of current-voltage conversion circuit receiving the first current and outputting the voltage of the middle stage, a second-stage of voltage-current conversion circuit receiving the middle stage of voltage to get an output current, a second stage of current-voltage conversion circuit converting output current to output voltage and a gain control circuit.
Description
Technical field
The present invention relates to multiplier, be specifically related to a kind of single quadrant CMOS multiplier with high linearity, wide input range, variable gain.
Background technology
Multiplier mainly is used in power factor correction (Power Factor Correction the abridge PFC) circuit, and it is the core of pfc circuit.The function that multiplier is finished can be used following formulate: C=KA * B.Wherein A is the dividing potential drop of the AC voltage that obtains after bridge rectifier; B is the feedback signal of output voltage, in order to keep output voltage constant; K is the gain of multiplier; C is the output of multiplier, as the comparative level of PWM comparator, is used for controlling the frequency and the duty ratio of PWM module output signal.
For the total harmonic distortion that reduces multiplier (Total Harmonic Distortion abridge THD), require the linearity of C/A very high, i.e. the variation that is critical with A of C changes.In the prior art, most integrated analog multipliers all adopt famous Gilbert multiplication unit, but the linear input range of Gilbert unit is narrow, and traditional multiplier can only be accepted the input about 0～1V, has limited the use of multiplier.The tradition integrated analog multiplier adopts Bipolar technology, and processing compatibility is relatively poor, and the cost height is difficult to satisfy the requirement of IC industry production.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of single quadrant analog multiplier of the CMOS of employing technology, this multiplier has high linearity and wide input range, and Gain Adjustable.
For achieving the above object, the technical solution used in the present invention is as follows:
A kind of high linearity wide input range changable gain single quadrant CMOS multiplier is characterized in that this multiplier comprises the first order and second level current/charge-voltage convertor, the first order and second level current-voltage conversion circuit and a gain control circuit, wherein,
First order current/charge-voltage convertor receives first input voltage, exports first electric current;
First order current-voltage conversion circuit receives first electric current, the output mid-stage voltage;
Second level current/charge-voltage convertor receives mid-stage voltage, is converted to first branch current and second branch current, and two branch currents are subjected to second current offset, and the difference of two branch currents obtains output current through both-end to single-ended change-over circuit;
The output current of second level current-voltage conversion circuit is converted to output voltage;
Gain control circuit is controlled the size of second electric current by the size of second input voltage.
Described first order current/charge-voltage convertor comprises first operation transconductance amplifier, and its reverse inter-input-ing ending grounding, normal phase input end receive described first input voltage, and output is exported first electric current.
Described first order current-voltage conversion circuit comprises the first, second, third and the 4th field effect transistor, the drain and gate of first, second field effect transistor all is connected with a voltage source, the source electrode of first, second field effect transistor connects the drain electrode of the 3rd, the 4th field effect transistor respectively, the drain and gate of the 3rd field effect transistor links to each other and receives first electric current, three, the grid of the 4th field effect transistor links to each other, source grounding, constitute current mirror, the positive and negative electrode of described mid-stage voltage is taken from the source electrode of first, second field effect transistor respectively.
Described second level current/charge-voltage convertor comprises the 5th field effect transistor and the 6th field effect transistor that constitutes differential pair tube, six, the grid of the 5th field effect transistor is connected with the positive and negative electrode of described mid-stage voltage respectively, described first, second branch current is respectively the electric current of the 5th, the 6th field effect transistor of flowing through, five, the continuous remittance knot end that forms two branch currents of the source electrode of the 6th field effect transistor, two branch currents are subjected to second current offset.
Described second level current/charge-voltage convertor comprises that also a both-end is to single-ended change-over circuit, described both-end comprises the current mirror that the 7th, the 8th field effect transistor constitutes to single-ended change-over circuit, seven, the drain electrode of the 8th field effect transistor is connected with the drain electrode of the 5th, the 6th field effect transistor respectively, described both-end also comprises the current mirror that the 9th, the tenth field effect transistor constitutes to single-ended change-over circuit, the drain electrode of the 9th field effect transistor connects the drain electrode of the 6th field effect transistor, give the tenth field effect transistor with the difference current mirror of second branch current and first branch current, obtain output current.
Described second level current-voltage conversion circuit comprises a resistance, an end ground connection of resistance, and the other end is connected with the output of described both-end to single-ended change-over circuit, receives output current and is converted to output voltage.
Described gain control circuit comprises second, third operation transconductance amplifier, the normal phase input end of two operation transconductance amplifiers receives the feedback voltage of output voltage, the output of two operation transconductance amplifiers is connected with the remittance knot end of described two branch currents provides second electric current, the inverting input of second, third operation transconductance amplifier to import first reference voltage and second reference voltage respectively.
Described first reference voltage is 2.5V, and described second reference voltage is 3.15V.
The difference of the described feedback voltage and first reference voltage provides second input voltage.
Described first input voltage is for exchanging the dividing potential drop of input behind bridge rectifier.
A kind of high linearity wide input range changable gain single quadrant CMOS multiplier of the present invention, total operation principle is a series of conversions by V → I → V → I → V, realize the function of multiplier, with the output of multiplying each other of first input voltage of multiplier and second input voltage.
First order current/charge-voltage convertor, first order current-voltage conversion circuit, second level current/charge-voltage convertor and second level current-voltage conversion circuit are the cores of multiplier.First order current/charge-voltage convertor is converted into first electric current by first operation transconductance amplifier with the difference between first input voltage and the ground GND, first order current-voltage conversion circuit is a mid-stage voltage with first current conversion, and mid-stage voltage is from the source electrode both-end output of first, second field effect transistor.In the current/charge-voltage convertor of the second level, six, the grid of the 5th field effect transistor connects the positive and negative electrode of mid-stage voltage respectively, be used to receive mid-stage voltage, and be converted to first branch current of the 5th field effect transistor of flowing through and second branch current of the 6th field effect transistor of flowing through, the source electrode of the source electrode of the 5th field effect transistor and the 6th field effect transistor is connected to form the remittance knot end of two branch currents, and two tributary electric currents are subjected to second current offset.Two branch currents obtain the output current of multiplier to single-ended change-over circuit by both-end.Second level current-voltage conversion circuit receives this output current, by the output voltage of resistance conversion output multiplier.The size of second electric current is by gain control circuit controls, and the gain of multiplier is by second Current Control, changes with the variation of second electric current.The output of second, third operation transconductance amplifier links together in the gain control circuit, and is connected second electric current that is provided for setovering with the remittance knot end of first branch current and second branch current.The normal phase input end of second, third operation transconductance amplifier receives the feedback voltage of output voltage, and inverting input is imported the first reference voltage 2.5V and the second reference voltage 3.15V respectively.When feedback voltage during less than 2.5V, the output of two operation transconductance amplifiers does not all have electric current, and second electric current is 0, and multiplier is not worked.When feedback voltage less than 3.15V the time, has only the output of second operation transconductance amplifier to have electric current to produce greater than 2.5V, second electric current equals the electric current that this output produces.When feedback voltage during greater than 3.15V, the output of second, third operation transconductance amplifier all has electric current to produce, and second electric current equals the electric current sum that two outputs produce.Therefore, the gain of multiplier is influenced by the feedback voltage size, when feedback voltage when 3.15V changes up and down, the gain of multiplier is respectively different values.
Beneficial effect of the present invention is, by setting to first order current/charge-voltage convertor, first order current-voltage conversion circuit, second level current/charge-voltage convertor, can guarantee the high linearity between the multiplier output voltage and first input voltage, reduce the total harmonic distortion of multiplier, enlarged the scope of input voltage simultaneously, input voltage can be selected between 0～3V.The size of gain control circuit controls second electric current realizes Gain Adjustable, makes input voltage in 85V～265V scope, and system can keep good stability.。
The present invention adopts CMOS technology, and processing compatibility is good, and circuit structure is simply compact, saves area, saves cost, reduces power consumption, has satisfied the needs of IC industry production better.
Description of drawings
The invention will be further elaborated below in conjunction with the drawings and specific embodiments.
Fig. 1 is the circuit structure diagram of the specific embodiment of the invention;
Fig. 2 is the local circuit structure chart that both-end arrives single-ended change-over circuit among Fig. 1.
Embodiment
As shown in Figure 1, a kind of high linearity wide input range changable gain single quadrant CMOS multiplier comprises first order current/charge-voltage convertor 1, first order current-voltage conversion circuit 2, second level current/charge-voltage convertor 3, second level current-voltage conversion circuit 4 and gain control circuit 5.
First order current/charge-voltage convertor 1 comprises the first operation transconductance amplifier OTA1.The normal phase input end of the first operation transconductance amplifier OTA1 receives the first input voltage Multin, and reverse inter-input-ing ending grounding GND, output export first electric current I 1.
First order current-voltage conversion circuit 2 comprises the first field effect transistor M1, the second field effect transistor M2, the 3rd field effect transistor M3 and the 4th field effect transistor M4.Four field effect transistor all adopt the NMOS pipe.The grid of the first field effect transistor M1 and the second field effect transistor M2 and drain electrode all are connected on the voltage source V CC, the source electrode of the first field effect transistor M1 and the second field effect transistor M2 is connected the drain electrode of the 3rd field effect transistor M3 and the 4th field effect transistor M4 respectively, the grid of the 3rd field effect transistor M3 is connected with drain electrode, also be connected simultaneously with the grid of the 4th field effect transistor M4, the source ground GND of the 3rd field effect transistor M3 and the 4th field effect transistor M4, two field effect transistor constitute current mirror.The drain electrode of the 3rd field effect transistor M3 is connected with the output of the first operation transconductance amplifier OTA1, receives first electric current I 1.Mid-stage voltage Δ V is from the source electrode output of the first field effect transistor M1 and the second field effect transistor M2.The first field effect transistor M1 has identical parameter with the second field effect transistor M2, is equivalent to two substitutional resistances.Because the 3rd field effect transistor M3 and the 4th field effect transistor M4 constitute current mirror, and the second field effect transistor M2 and the 4th field effect transistor M4 are on same circuit, when the 3rd field effect transistor M3 had identical parameters such as length-width ratio with the 4th field effect transistor M4, the electric current that flows through the second field effect transistor M2, the 3rd field effect transistor M3 and the 4th field effect transistor M4 equated.The electric current that can obtain flowing through the first field effect transistor M1 according to kirchhoff electric current theorem is to flow through the electric current of the 3rd field effect transistor M3 and the difference of first electric current I 1, littler than the electric current that flows through the second field effect transistor M2, therefore the current potential of the first field effect transistor M1 source electrode is than the current potential height of the second field effect transistor M2 source electrode, so the positive pole of the corresponding mid-stage voltage Δ of the source electrode of first field effect transistor M1 V, the negative pole of the corresponding mid-stage voltage Δ of the source electrode of second field effect transistor M2 V.
Second level current/charge-voltage convertor 3 comprises the differential pair tube that is made of the 5th field effect transistor M5 and the 6th field effect transistor M6 and both-end to single-ended change-over circuit, and two field effect transistor adopt the NMOS pipe.The grid of the 5th field effect transistor M5 and the 6th field effect transistor M6 is connected with the source electrode of the second field effect transistor M2 and the first field effect transistor M1 respectively, promptly is connected with negative pole, the positive pole of mid-stage voltage Δ V respectively, is used to receive mid-stage voltage Δ V.The drain electrode of the 5th field effect transistor M5 and the 6th field effect transistor M6 is as two inputs of both-end to single-ended change-over circuit, the electric current that flows through the 5th field effect transistor M5 and the 6th field effect transistor M6 is respectively the first branch current I5 and the second branch current I6, the source electrode of the 5th field effect transistor M5 and the 6th field effect transistor M6 is connected, form the remittance knot end A of two branch currents, two branch currents are subjected to 2 biasings of second electric current I.
Both-end to the circuit structure of single-ended change-over circuit as shown in Figure 2, this circuit comprises the current mirror that is made of the 7th field effect transistor M7 and the 8th field effect transistor M8, two field effect transistor adopt the PMOS pipe, their source electrode is connected with voltage source V CC, and drain electrode is connected with the drain electrode of the 5th field effect transistor M5 and the 6th field effect transistor M6 respectively.This both-end also comprises the current mirror that the 9th field effect transistor M9 and the tenth field effect transistor M10 constitute to single-ended change-over circuit.The 9th field effect transistor M9 and the tenth field effect transistor M10 adopt the PMOS pipe, and their source electrode is connected with voltage source V CC.The drain electrode of the 9th field effect transistor M9 connects the drain electrode of the 8th field effect transistor M8.Because the voltage height of voltage ratio the 5th field effect transistor M5 grid of the 6th field effect transistor M6 grid, the electric current that flows through the 6th field effect transistor M6 are that promptly the first branch current I5 is big than the electric current that flows through the 5th field effect transistor M5 for the second branch current I6.And the 5th field effect transistor M5 and the 7th field effect transistor M7 are on same circuit, the electric current of the 5th field effect transistor M5 i.e. first branch current I5 is given the 8th field effect transistor M8 by the 7th field effect transistor M7 mirror image, make electric current on the 8th field effect transistor M8 less than the electric current of the 6th field effect transistor M6, their difference electric current is that the difference electric current of the second branch current I6 and the first branch current I5 is mirrored to the tenth field effect transistor M10 through the 9th field effect transistor M9, obtains the output current of multiplier.
Second level current-voltage conversion circuit 4 comprises resistance R, an end ground connection GND of resistance R, and the other end connects the drain electrode of the tenth field effect transistor M10, receives the output current of multiplier, and is converted to the output voltage Multout of multiplier.
Gain control circuit 5 is used to control the size of second electric current I 2, thus the gain of control multiplier.This circuit comprises the second operation transconductance amplifier OTA2 and the 3rd operation transconductance amplifier OTA3.The normal phase input end of the second operation transconductance amplifier OTA2 receives the feedback voltage V aout of output voltage, and its inverting input receives the first reference voltage 2.5V.The normal phase input end of the 3rd operation transconductance amplifier OTA3 receives the feedback voltage V aout of output voltage, and its inverting input receives the second reference voltage 3.15V.The output of the second operation transconductance amplifier OTA2 and the 3rd operation transconductance amplifier OTA3 links together, and is connected with the remittance knot end A of the first branch current I5 and the second branch current I6, provides second electric current I 2 as biasing.When feedback voltage V aout greater than the first reference voltage 2.5V during less than the second reference voltage 3.15V, the output of the second operation transconductance amplifier OTA2 produces electric current I 2a, the output of the 3rd operation transconductance amplifier OTA3 does not have electric current, and this moment, second electric current I 2 equaled electric current I 2a; As feedback voltage V aout during greater than the second reference voltage 3.15V, the output of the second operation transconductance amplifier OTA2 produces electric current I 2a, the output of the 3rd operation transconductance amplifier OTA3 produces electric current I 2b, and this moment, second electric current I 2 equaled electric current I 2a and electric current I 2b sum; As feedback voltage V aout during less than the first reference voltage 2.5V, the output of the output of the second operation transconductance amplifier OTA2 and the 3rd operation transconductance amplifier OTA3 does not all have electric current, and this moment, second electric current I 2 equaled 0, and multiplier is not worked.This shows that the gain of multiplier is subjected to the influence of feedback voltage V aout, when feedback voltage V aout when 3.15V changes up and down, multiplier has different gains.Multiplier is total to be output as:
Multout＝K·Multin·(Vaout-2.5V)
Wherein, Multout represents the output voltage of multiplier; K represents the gain of multiplier, and this gain is by I2 control, changes with the variation of I2; Multin represents first input voltage of multiplier, and first input voltage is for exchanging the dividing potential drop that input obtains behind bridge rectifier; (Vaout-2.5V) second input voltage of formation multiplier.
Claims (10)
1. a high linearity wide input range changable gain single quadrant CMOS multiplier is characterized in that this multiplier comprises the first order and second level current/charge-voltage convertor, the first order and second level current-voltage conversion circuit and a gain control circuit, wherein,
First order current/charge-voltage convertor receives first input voltage, exports first electric current;
First order current-voltage conversion circuit receives first electric current, the output mid-stage voltage;
Second level current/charge-voltage convertor receives mid-stage voltage, is converted to first branch current and second branch current, and two branch currents are subjected to second current offset, and the difference of two branch currents obtains output current through both-end to single-ended change-over circuit;
The output current of second level current-voltage conversion circuit is converted to output voltage;
Gain control circuit is controlled the size of second electric current by the size of second input voltage.
2. high linearity wide input range changable gain single quadrant CMOS multiplier as claimed in claim 1, it is characterized in that described first order current/charge-voltage convertor comprises first operation transconductance amplifier, its reverse inter-input-ing ending grounding, normal phase input end receives described first input voltage, and output is exported first electric current.
3. high linearity wide input range changable gain single quadrant CMOS multiplier as claimed in claim 1, it is characterized in that described first order current-voltage conversion circuit comprises first, second, third and fourth field effect transistor, first, the drain and gate of second field effect transistor all is connected with a voltage source, first, the source electrode of second field effect transistor connects the 3rd respectively, the drain electrode of the 4th field effect transistor, the drain and gate of the 3rd field effect transistor links to each other and receives first electric current, the 3rd, the grid of the 4th field effect transistor links to each other, source grounding, constitute current mirror, described mid-stage voltage just, negative pole takes from first respectively, the source electrode of second field effect transistor.
4. high linearity wide input range changable gain single quadrant CMOS multiplier as claimed in claim 1, it is characterized in that described second level current/charge-voltage convertor comprises the 5th field effect transistor and the 6th field effect transistor that constitutes differential pair tube, six, the grid of the 5th field effect transistor is connected with the positive and negative electrode of described mid-stage voltage respectively, described first, second branch current is respectively the electric current of the 5th, the 6th field effect transistor of flowing through, five, the continuous remittance knot end that forms two branch currents of the source electrode of the 6th field effect transistor, two branch currents are subjected to second current offset.
5. high linearity wide input range changable gain single quadrant CMOS multiplier as claimed in claim 4, it is characterized in that described second level current/charge-voltage convertor comprises that also a both-end is to single-ended change-over circuit, described both-end comprises the 7th to single-ended change-over circuit, the current mirror that the 8th field effect transistor constitutes, the 7th, the drain electrode of the 8th field effect transistor is respectively with the 5th, the drain electrode of the 6th field effect transistor connects, described both-end also comprises the 9th to single-ended change-over circuit, the current mirror that the tenth field effect transistor constitutes, the drain electrode of the 9th field effect transistor connects the drain electrode of the 6th field effect transistor, give the tenth field effect transistor with the difference current mirror of second branch current and first branch current, obtain output current.
6. high linearity wide input range changable gain single quadrant CMOS multiplier as claimed in claim 1, it is characterized in that described second level current-voltage conversion circuit comprises a resistance, one end ground connection of resistance, the other end is connected with the output of described both-end to single-ended change-over circuit, receives output current and is converted to output voltage.
7. high linearity wide input range changable gain single quadrant CMOS multiplier as claimed in claim 1, it is characterized in that described gain control circuit comprises second, third operation transconductance amplifier, the normal phase input end of two operation transconductance amplifiers receives the feedback voltage of output voltage, the output of two operation transconductance amplifiers is connected with the remittance knot end of described two branch currents provides second electric current, the inverting input of second, third operation transconductance amplifier to import first reference voltage and second reference voltage respectively.
8. high linearity wide input range changable gain single quadrant CMOS multiplier as claimed in claim 7 is characterized in that described first reference voltage is 2.5V, and described second reference voltage is 3.15V.
9. high linearity wide input range changable gain single quadrant CMOS multiplier as claimed in claim 7 is characterized in that the difference of the described feedback voltage and first reference voltage provides second input voltage.
10. high linearity wide input range changable gain single quadrant CMOS multiplier as claimed in claim 1 is characterized in that described first input voltage is for exchanging the dividing potential drop of input behind bridge rectifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710142984 CN101090267A (en) | 2007-08-14 | 2007-08-14 | High linearity wide input range changable gain single quadrant CMOS multiplier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710142984 CN101090267A (en) | 2007-08-14 | 2007-08-14 | High linearity wide input range changable gain single quadrant CMOS multiplier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101090267A true CN101090267A (en) | 2007-12-19 |
Family
ID=38943464
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200710142984 Pending CN101090267A (en) | 2007-08-14 | 2007-08-14 | High linearity wide input range changable gain single quadrant CMOS multiplier |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101090267A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101877044A (en) * | 2010-05-21 | 2010-11-03 | 西安电子科技大学 | Total harmonic distortion optimization analog multiplier |
| CN103226460A (en) * | 2013-04-18 | 2013-07-31 | 电子科技大学 | Multichannel analogue multiply-divide arithmetic circuit |
| WO2016119661A1 (en) * | 2015-01-27 | 2016-08-04 | 意瑞半导体（上海）有限公司 | Power factor correction circuit and multiplier |
| US10256716B2 (en) | 2015-01-27 | 2019-04-09 | Cosemitech (Shanghai) Co., Ltd. | Power factor correction circuit, multiplier and voltage feed-forward circuit |
-
2007
- 2007-08-14 CN CN 200710142984 patent/CN101090267A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101877044A (en) * | 2010-05-21 | 2010-11-03 | 西安电子科技大学 | Total harmonic distortion optimization analog multiplier |
| CN101877044B (en) * | 2010-05-21 | 2013-02-27 | 西安电子科技大学 | Total harmonic distortion optimization analog multiplier |
| CN103226460A (en) * | 2013-04-18 | 2013-07-31 | 电子科技大学 | Multichannel analogue multiply-divide arithmetic circuit |
| CN103226460B (en) * | 2013-04-18 | 2016-08-24 | 电子科技大学 | Multichannel analogue multiply-divide arithmetic circuit |
| WO2016119661A1 (en) * | 2015-01-27 | 2016-08-04 | 意瑞半导体（上海）有限公司 | Power factor correction circuit and multiplier |
| CN105991127A (en) * | 2015-01-27 | 2016-10-05 | 意瑞半导体（上海）有限公司 | Power factor correction circuit and multiplier |
| CN105991127B (en) * | 2015-01-27 | 2018-11-13 | 意瑞半导体（上海）有限公司 | Circuit of power factor correction and multiplier |
| US10171035B2 (en) | 2015-01-27 | 2019-01-01 | Cosemitech (Shanghai) Co., Ltd. | Power factor correction circuit and multiplier |
| US10256716B2 (en) | 2015-01-27 | 2019-04-09 | Cosemitech (Shanghai) Co., Ltd. | Power factor correction circuit, multiplier and voltage feed-forward circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101692603B (en) | Gain bootstrap type C class reverser and application circuit thereof | |
| CN104101764B (en) | Novel inductor current detection circuit applied to DC-DC converter | |
| CN102882482B (en) | Ultralow power consumption error amplifier | |
| CN202548685U (en) | Reference voltage buffer circuit | |
| CN104270150B (en) | High-speed low-power-consumption reference voltage output buffer applied to production line analog-digital converter | |
| CN102130659A (en) | Circuit structure for reducing input offset voltage of two-stage operational amplifier | |
| CN107315439A (en) | High-precision voltage controlled current source circuit | |
| CN101794159A (en) | Band-gap reference voltage source of high power supply voltage rejection ratio | |
| CN101090267A (en) | High linearity wide input range changable gain single quadrant CMOS multiplier | |
| CN109814647A (en) | A kind of wide-range and the ac current source and processing method of closed-loop control | |
| WO2018205832A1 (en) | Superposed operation circuit and floating-voltage digital-to-analog conversion circuit | |
| CN104348431B (en) | Common-mode feedback differential amplification circuit, method and integrated circuit | |
| CN103944571A (en) | High-speed configurable assembly line analog-to-digital converter | |
| CN102931833B (en) | Circuit for converting high voltage into low voltage in analogue circuit | |
| CN203457116U (en) | CMFB differential amplification circuit and integrated circuit | |
| CN106940580B (en) | A kind of low-power consumption band gap reference and supply unit | |
| CN201113977Y (en) | High linearity broad input range variable gain single quadrant CMOS multiplier | |
| CN203012570U (en) | Resistor calibration circuit | |
| CN201766574U (en) | High-speed common mode insensitive charge comparator circuit | |
| CN106371495B (en) | The MPPT control circuits and energy harvesting circuit obtained for micro-energy | |
| CN102594352A (en) | Sample hold circuit and method for expanding dynamic range of streamline analog to digital converter using sample hold circuit | |
| CN203423670U (en) | Variable-gain analog adder | |
| CN1271788C (en) | A/D converter of adopting improved type fold circuit | |
| CN206711075U (en) | A kind of four-quadrant analog divider | |
| CN101387895A (en) | Current mirror and novel non-linearity multiplier composed of the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| ASS | Succession or assignment of patent right |
Owner name: LVDA OPTO-ELECTRICAL ( SUZHOU) CO., LTD. Free format text: FORMER OWNER: KAIYUAN IC (SUZHOU) CO., LTD. Effective date: 20080111 |
|
| C10 | Entry into substantive examination | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20080111 Address after: Room 1610, international science and Technology Park, 328 Airport Road, Suzhou Industrial Park, Jiangsu Province, China: 215021 Applicant after: Grenergy Opto. (Suzhou) Inc. Address before: Room 1610, international science and Technology Park, 328 Airport Road, Suzhou Industrial Park, Jiangsu Province, China: 215021 Applicant before: Supec (Suzhou) Co., Ltd. |
|
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |