CN103414442B - High accuracy fully-differential amplifier based on wave chopping technology - Google Patents

Abstract

The present invention relates to integrated circuit technique, particularly relate to a kind of high accuracy fully-differential amplifier based on wave chopping technology, adopt common-mode feedback technology and wave chopping technology to reduce imbalance and noise. High accuracy fully-differential amplifier based on wave chopping technology of the present invention, mainly have employed wave chopping technology and electric capacity common-mode feedback technology, copped wave module is by two multipliers and two operational amplifier compositions, wherein, two are subject to same clock control, and input signal VIN enters the first multiplier and is modulated; Signal after modulation enters the first operational amplifier and amplifies; Enter the second multiplier after the signals reverse of output to be demodulated; The signal finally demodulated enters the second operational amplifier reduction and amplifies. Beneficial effects of the present invention is, compared with existing fully-differential amplifier circuit, due to the fact that and have employed electric capacity common-mode feedback technology and wave chopping technology, it is achieved that low noise in frequency band, low maladjustment voltage and high accuracy. Present invention is particularly suitable for fully-differential amplifier.

Description

High accuracy fully-differential amplifier based on wave chopping technology

Technical field

The present invention relates to integrated circuit technique, particularly relate to a kind of high accuracy fully-differential amplifier based on wave chopping technology, adopt common-mode feedback technology and wave chopping technology to reduce imbalance and noise.

Background technology

Along with the development of Analogous Integrated Electronic Circuits technology, at a high speed, high precision operating amplifier is used widely. Full differential operational amplifier in output voltage swing, input dynamic range etc. relatively Single-end output amplifier have great advantage, become the very wide circuit unit of application. But there is the problem that output common mode level is unstable in Full differential operational amplifier, it is necessary to design common mode feedback circuit ensures operational amplifier normal operation. Common-mode feedback is frequently with two ways: a kind of mode is to adopt resistance to detect the common-mode voltage of output, but this mode can significantly reduce the differential voltage gain of circuit; Another mode is to adopt source follower and variable-resistance detection technique, but can limit the range of linearity.

Along with Digital Signal Processing develops rapidly, the situation that digital display circuit processes analogue signal is utilized to become more general, this is because the adaptive algorithm that Digital Signal Processing can conveniently realize various advanced person completes the function that analog circuit cannot realize. But, the signal that we run in actual life is continually varying analog quantity mostly, is at this moment accomplished by an interface circuit and analog quantity is converted to digital quantity, and the interface unit that can complete this task is exactly A/D converter. Traditional A/D converter is mainly made up of analog circuit, and the precision of A/D converter is had a significant impact by circuit components matching error, and can introduce noise in signal band. The Design of Amplifiers used in A/D converter, in order to avoid introducing noise, it is necessary to use circuit to reduce the impact of the nonideal characteristic such as input offset voltage and 1/f noise in signal channel.High-gain, low imbalance operational amplifier adopt double-width grinding both-end output fully-differential amplifier, in the impregnable situations of condition such as amplifier gain, bandwidth and range of linearity, it is necessary to output common mode level is compensated.

Summary of the invention

The technical problem to be solved, it is aiming at the problems referred to above, a kind of high accuracy fully-differential amplifier based on wave chopping technology is provided, when not changing differential voltage gain and the range of linearity of circuit, reduces or eliminate nonideal characteristic (1/f noise and input offset voltage).

This invention address that above-mentioned technical problem be the technical scheme is that the high accuracy fully-differential amplifier based on wave chopping technology, it is characterised in that include the first to the second multiplier, the first to the 3rd operational amplifier, the first to the second electric capacity; Wherein, two inputs of the first multiplier connect the first voltage input end and the second voltage input end, the first outfan connect the in-phase input end of the first operational amplifier, the second outfan connects the inverting input of the first operational amplifier respectively; The reversed-phase output of the first operational amplifier connects the first input end of the second multiplier, in-phase output end connects the second input of the second multiplier; First outfan of the second multiplier connects the in-phase input end of the second operational amplifier, the second outfan connects the inverting input of the second operational amplifier; The reversed-phase output of the second operational amplifier as the first voltage output end of difference amplifier, in-phase output end as the second voltage output end of difference amplifier; One end of first electric capacity connects the reversed-phase output of the second operational amplifier, one end of second electric capacity connects the in-phase output end of the second operational amplifier, and the other end of the first electric capacity and the other end of the second electric capacity connect and input the inverting input of the 3rd operational amplifier; 3rd operational amplifier in-phase input end connect reference voltage, outfan and connect the 3rd input of the first operational amplifier; Described first operational amplifier and the second operational amplifier are chopper-stabilized operational amplifiers, and wherein the 3rd operational amplifier output is common mode feedback signal, and the feedback end inputting the first operational amplifier controls the first operational amplifier.

Concrete, described first operational amplifier includes the first PMOS, the 5th PMOS, the 6th PMOS, the first NMOS tube and the second NMOS tube, described second operational amplifier includes the second PMOS, the 3rd PMOS, the 3rd NMOS tube, the 4th NMOS tube, first to fourth electric capacity, the first to the second resistance, and described 3rd operational amplifier includes the 4th PMOS, the 7th PMOS, the 8th PMOS, the 5th NMOS tube and the 6th NMOS tube;

The source electrode of first to fourth PMOS all connects power supply, grid and all connects a reference source voltage signal;

The drain electrode of the first PMOS is connected with the source electrode of the 5th PMOS and the 6th PMOS, the grid of the 5th PMOS and the first outfan of the first multiplier connect, draining is connected with the drain electrode of the first NMOS tube and the second input of the second multiplier, and the grid of the 6th PMOS and the second outfan of the first multiplier connect, draining is connected with the drain electrode of the second NMOS tube and the first input end of the second multiplier;

The grid of the first NMOS tube and the second NMOS tube is connected with the drain and gate of the drain electrode of the 7th PMOS, the 5th NMOS tube after connecting;

The drain electrode of the second PMOS is connected the second voltage output end as difference amplifier with one end of the 3rd electric capacity and the drain electrode of the 3rd NMOS tube, and is connected with one end of the second electric capacity;

The other end of the 3rd electric capacity and one end of the first resistance connect, and the other end of the first resistance and the grid of the 3rd NMOS tube are connected with the second outfan of the second multiplier after connecting;

One end of second resistance is connected with the first outfan of the second multiplier after being connected with the grid of the 4th NMOS tube, and the other end of the second resistance and one end of the 4th electric capacity connect;

The drain electrode of the other end of the 4th electric capacity and the drain electrode of the 3rd PMOS, the 4th NMOS tube connects the first voltage output end as difference amplifier, and is connected with one end of the first electric capacity;

The other end of the first electric capacity and the other end of the second electric capacity are connected with the grid of the 7th PMOS after connecting, and the drain electrode of the source electrode of the 7th PMOS and the source electrode of the 8th PMOS and the 4th PMOS connects;

The grid of the 8th PMOS connects reference voltage, drain electrode is connected with the drain and gate of the 6th NMOS tube;

The source ground of the first to the 6th NMOS tube.

Beneficial effects of the present invention is, suitable in fields of measurement such as high-precision a/d converters, compared with existing fully-differential amplifier, adopt electric capacity common-mode feedback technology, the resistance impact on system stability can be reduced compared with feedback circuit, thus improving bandwidth and the gain of amplifier with adopting resistance; Adopt wave chopping technology, compared with the circuit adopting the design of high matching layout, it is possible to reduce, from circuit aspect, the mismatch condition that device causes manufacturing process affects, and can reduce to a great extent or eliminate noise; So that Full differential operational amplifier is operated in duty more accurately, precision is also greatly improved.

Accompanying drawing explanation

Fig. 1 is the wave chopping technology analysis circuit figure of analogue noise and imbalance;

Fig. 2 is the system design circuit theory diagrams of wave chopping technology;

Fig. 3 is the system block diagram of the high accuracy fully-differential amplifier based on wave chopping technology that the present invention proposes;

Fig. 4 is the integrated circuit structural representation of the high accuracy fully-differential amplifier based on wave chopping technology that the present invention proposes;

Fig. 5 is the electric capacity common-mode feedback technology loop schematic equivalent circuit that the present invention proposes.

Detailed description of the invention

Below in conjunction with accompanying drawing, technical scheme is described in detail:

In the design of Full differential operational amplifier, compared to single-ended duty, advantage is in that effectively to suppress common-mode noise, and bigger output voltage swing, biasing circuit are simpler, output linearity Du Genggao. The Full differential operational amplifier of ideal situation can reach significantly high precision. But in actual applications, owing to not the mating of differential pair tube, current mirror error etc. all can introduce offset voltage and 1/f noise at the nonideal characteristic of low frequency or dc noise category at differential input end. In high gain amplifier, output common mode level is quite sensitive to characteristic and the mismatch of device, and can not be reached stable by differential feedback, it is therefore desirable to high-gain differential circuit does the process of common-mode feedback. Sampling compared to traditional electric resistance partial pressure and variable resistance form is sampled, electric capacity sampling is without influence on the differential voltage gain of circuit and the range of linearity. Therefore the circuit of the present invention when not affecting gain, can have better capacity of resisting disturbance.

For convenient narration, hereinafter the first to the 8th PMOS is successively respectively with PM1, PM2, PM3, PM4, PM5, PM6, PM7, PM8 replaces, first to the 6th NMOS tube is successively respectively with NM1, NM2, NM3, NM4, NM5, NM6 replaces, first to fourth electric capacity is successively respectively with C1, C2, C3, C4 replaces, the first to the second resistance is successively respectively with R1, R2 replaces, the first to the second operational amplifier is successively respectively with op_chopper1, op_chopper2 replaces, 3rd operational amplifier replaces with op_cm, the first to the second multiplier is successively respectively with multiplier 1, multiplier 2 replaces.

Wave chopping technology side circuit system block diagram of the present invention is as in figure 2 it is shown, be left out the problem of circuit design and compensation, and system is mainly made up of four parts: multiplier 1, op_chopper1, multiplier 2, op_chopper2 form; Wherein, multiplier 1, multiplier 2 are by same clock control, and amplitude is the chopping square-wave control of+1 and-1. Wave chopping technology principle analysis figure is as it is shown in figure 1, VIN is after multiplier 1, and input signal Va is moved in the odd harmonic frequencies of chopping square-wave by modulation. At Vb place, it is undesirable to the interference signal Vos such as the imbalance of appearance, noise source or distortion is added in frequency. After multiplier 2, part corresponding with input signal Va in Vc signal is demodulated in input signal frequency originally, reduces, and the interference signal in Vc signal is then modulated onto on the odd harmonic frequency spectrum of chopping square-wave. Thus realizing input signal and separating on interference signal spectrum. If chopping frequency is much larger than signal bandwidth, then the interference signal in signal passband will be greatly reduced. Therefore interference signal is modulated onto and wishes beyond the frequency range of work. Bandwidth to be accounted for by design objective, by the method adding low pass filter, it is possible to reduce imbalance and effect of noise.

As it is shown on figure 3, VP, VN are corresponding to the positive and negative terminal of the VIN of Fig. 1, S1 to S4, the S5 to S8 of four on-off control corresponds respectively to the multiplier 1 of Fig. 2, multiplier 2. Common-mode feedback technology is to feed back to the operational amplifier of input from outfan, is mainly made up of three parts: sampling capacitance C1, sampling capacitance C2 and operational amplifier op_cm. Wherein, difference output VOUTP and VOUTN is after C1 and C2 samples, and Vsample and VREF is compared by op_cm, thus controlling the electric current of op_chopper1, plays the effect of common-mode feedback.

As described in Figure 4, op_chopper1 is by PMOS for particular circuit configurations: PM1, PM5, PM6, NMOS tube: NM1, NM2 form. Pipe is that PMOS PM5 and PM6, VIN are modulated and are input to the grid of differential pair tube PM5 and PM6 by multiplier 1 by op_chopper1 input difference. PM1 is based on the enantiomorphous part of current reference, and grid connects VB current potential, and source electrode connects supply voltage, and drain electrode connects with PM5, PM6 source electrode; NM1, NM2 are as the load of differential pair tube, and grid is controlled by feedback node C, source ground, and drain electrode connects with PM5, PM6 drain electrode respectively, and output node is A, B. Output node A, B of op_chopper1 is input to the grid of common-source stage amplifier NM3, NM4 of op_chopper2 by multiplier 2 demodulation. Op_chopper2 is by PMOS: PM2, PM3 manage, NMOS tube: NM3, NM4 form. The source ground of NM3, NM4. PM2, PM3 and PM1 are based on the enantiomorphous part of current reference, and grid connects VB current potential, and source electrode connects supply voltage, and drain electrode connects with the drain electrode of NM3, NM4 respectively. One end of multiplier 2 is concatenated into output negative terminal VOUTN by resistance R1, electric capacity C3. The other end of multiplier 2 is concatenated into output plus terminal VOUTP by resistance R2, electric capacity C4.

A kind of circuit implementing scheme of electric capacity common-mode feedback as shown in Figure 4, by PMOS: PM4, PM7, PM8, NMOS tube: NM5, NM6, electric capacity: C1, C2 form. Output VOUTP, VOUTN of chopping operational amplifier concatenates dividing potential drop by C1, C2, and the D point of sampling is input to the grid of the PM7 of op_cm amplifier, and PM7 and PM8 is the input of differential pair, and the grid of PM8 is connected to reference voltage V REF.NM5 and NM6 diode type of attachment is respectively as the load of PM7 and PM8, source ground, and drain electrode connects respectively at the drain electrode of PM7, PM8; PM4 and PM1, PM2, PM3 are based on the enantiomorphous part of current reference, and grid connects VB current potential, and source electrode connects supply voltage, and drain electrode connects with the source electrode of PM7, PM8. Op_cm amplifier adopts the form of double-width grinding Single-end output, feeds back to NM1 and the NM2 grid of op_chopper1 from outfan C point.

The operation principle of the present invention is:

1) wave chopping technology

Realizing as it is shown on figure 3, S1, S3 and S2, S4 are the switch controlled by the complementary clock of two non-overlapping copies respectively specific to multiplier, controls two cross-linked switches and constitutes first multiplier. S5, S7 and S4, S6 are the switch controlled by the complementary clock of two non-overlapping copies respectively, control two cross-linked switches and constitute second multiplier. Two cross-linked switch S1, S3 and S5, S7 Guan Bis, S2, S4 and S6, S8 disconnect+1 in interval scale square wave, and switch S1, S3 and S5, S7 disconnect, during S2, S4 and S6, S8 Guan Bi, represent-1 in square wave, thus realizing input signal to carry out multiplying with square wave. Operation principle is from time domain angle: input signal is multiplied with square-wave signal; From frequency domain angle: input signal is by convolution square-wave frequency modulation, demodulation and frequency domain. The frequency spectrum of square wave is:

$m\left(t\right)=\frac{4}{\mathrm{\π}}\underset{k=1}{\overset{\∞}{\mathrm{\Σ}}}\frac{\sin \left({\mathrm{kw}}_{0}t\right)}{k}$ (1)

$=\frac{4}{\mathrm{\π}}({\sin w}_{0}t+\frac{1}{3}\sin 3w_{0}t+\frac{1}{5}\sin {5w}_{0}t+...+\frac{1}{k}\sin k{w}_{0}t+...)$

Wherein, k=1,3,5 ..., w0=2 �� fchop, fchop are switching frequency. From the frequency spectrum of formula (1) known square wave containing only having 1,3,5 ... odd harmonic component.

Carrying out the obtained frequency spectrum of multiplication operation again is:

$m^2\left(t\right)={\left[\frac{4}{\mathrm{\π}}\underset{k=1}{\overset{\∞}{\mathrm{\Σ}}}\frac{\sin \left({\mathrm{kw}}_{0}t\right)}{k}\right]}^2$ (2)

$=a_1+b_1(\sin 2w_{0}t+\sin {4w}_{0}t+{\sin 6w}_{0}t+...+\sin \mathrm{kt}+...)$

Wherein, k=2,4,6 ..., w0=2 �� fchop, fchop are switching frequency, and a1, b1 are constant. It is modulated rear frequency spectrum containing only having 2,4,6 ... even-order harmonic component from formula (2) known square wave.

Wave chopping technology principle is such as shown in figure Fig. 1, at the input of op_chopper1, realizes signal multiplication by switch switching and modulates input signal VIN, then be exaggerated together with the interference signal such as offset voltage and noise by signal VIN*m (t) after modulation. Represent interference signal with Vos, then now the output of op_chopper1 can be expressed as:

Vout1=A₁*[VIN*m(t)+V_OS] (3)

Wherein, m(t) for the spectrum of clock CLOCK, A1 is the gain of op_chopper1. By formula (1) with (3) it can be seen that the odd harmonic component only having fchop is left. After op_chopper1, at its outfan, signal is demodulated, namely carries out multiplying with multiplier 2, so time:

Vout2={A₁*[VIN*m(t)+V_OS]*m(t)}*A₂

=A₁*A₂*VIN*m²(t)+A₁*A₂*V_OS* m (t) (4)

Wherein, A2 is the gain of op_chopper2. From formula (4), VIN is modulated, is demodulated, signal VIN*m (t) after amplification is demodulated to the even-order harmonic component only carrying fchop, but for Vos its by modulated once, therefore only Vos is shifted in the odd harmonic of fchop. And form equivalence bulky capacitor by C3 and C4 in miller-compensated network, constitute low pass filter with the output resistance of first order amplifier op_chopper1, its radio-frequency component is filtered, finally leaves useful signal component.

Compensate network except can filtering radio-frequency component, system stability is also played vital effect, namely the zero pole point of system is compensated.

For op_chopper1 gain it is:

A₁=-g_mpm5R_out1=-g_mpm5(rp_o5//rn_o1) (5)

Wherein, Rout1 is the output impedance of first order amplifier op_chopper1, and gmpm5 is the mutual conductance of PM5 pipe, and rpo5 is the channel modulation resistance of PM5 pipe, and rno1 is the channel modulation resistance of NM1 pipe.

For op_chopper2 gain it is:

A₂=-g_mnm3R_out2=-g_mnm3(rp_o2//rn_o3) (6)

Wherein, Rout2 is the output impedance of second level amplifier op_chopper2, and gmnm3 is the mutual conductance of NM3 pipe, and rpo2 is the channel modulation resistance of PM2 pipe, and rno3 is the channel modulation resistance of NM3 pipe.

Can be released whole system gain by formula (5) (6) is:

A_v=A₁*A₂=g_mpm5(rp_o5//rn_o1)*gmnm₃(rp_o2//rn_o3) (7)

And can obtain two-stage calculation amplifier by the zero pole point after compensating is:

$p1=-\frac{g_{\mathrm{mpm}5}}{A_v{C}_3}=-\frac{1}{R_{\mathrm{out}1}{g}_{\mathrm{mnm}3}{R}_{\mathrm{out}2}{C}_3}---\left(8\right)$

$p2=-\frac{g_{\mathrm{mnm}3}{C}_3}{C_{\mathrm{out}1}{C}_{\mathrm{out}2}+C_3{C}_{\mathrm{out}1}+C_3{C}_{\mathrm{out}2}}=-\frac{g_{\mathrm{mnm}3}}{C_{\mathrm{out}2}}---\left(9\right)$

$p3=-\frac{1}{R_1{C}_{\mathrm{out}1}}---\left(10\right)$

$z1=\frac{1}{C_3(1/g_{\mathrm{mnm}3}-R_1)}---\left(11\right)$

Wherein, p1, p2, p3 are limit, and z1 is zero point, and C3 is miller-compensated electric capacity, and resistance R1 be used to eliminate Right-half-plant zero zero-regulator resistor, Cout1, Cout2 respectively first order, the second level output capacitance. By formula (8), (9), (10) and (11) it is recognised that the zero pole point acting primarily as decisive action during system stability is p1, p2 and z1, p1 is the dominant pole of Left half-plane, and p2 is the secondary limit of Left half-plane, and z1 is zero point. Zero-regulator resistor R1 can independently control zero point. In order to move Right-half-plant zero, R1 is necessarily equal to 1/gmnm3; Or zero point is moved to from RHP the position of Left half-plane limit p2, by the pole cancellation relevant with output load capacitance, makes phase margin increase, thus improving the stability of system. The other branch road being made up of PM3, PM6, NM2, NM4, R2, C4, derivation keeps consistent with said process.

2) electric capacity common-mode feedback technology

In high gain amplifier, output common mode level is very sensitive to characteristic and the mismatch of device, and can not be reached stable by differential feedback. Therefore, it is necessary to detect the common mode electrical level of two outfans by increasing common-mode feedback network, and there is the offset current regulating amplifier of foundation. Common-mode feedback technology is divided into three steps: 1, detection output common mode level; 2, same reference voltage compares; 3, error is sent amplifier biasing network back to. So needing in the design output common mode point is sampled, and by comparator, sampled point and reference voltage are compared, thus exporting a signal to control biasing networks.

In the present invention, op_cm is the fully-differential amplifier of a kind of double-width grinding Single-end output, as shown in Figure 3, gain can regard infinitely great as in the ideal situation, the anode of amplifier is fixed on reference voltage V REF, by Vcm clamper at VREF current potential, the size of your required common mode output level can be controlled with this under steady statue. But in actual applications, gain can not reach infinity, as shown in Figure 4, the common mode feedback amplifier gain designed by the present invention is:

$A_{\mathrm{cmfb}}=-\frac{g_{\mathrm{mpm}7}}{g_{\mathrm{mnm}5}}---\left(12\right)$

Wherein, gmpm7 is the mutual conductance of PM7, and gmnm5 is the mutual conductance of NM5.

Common-mode feedback network limit is: $p4=-\frac{1}{R_C\mathrm{Cc}}=-\frac{g_{\mathrm{mnm}5}}{\mathrm{Cc}}---\left(13\right)$

Wherein, Rc is the equivalent resistance entered in terms of C point, and Cc is the parasitic capacitance entered in terms of C point, forms a Left half-plane limit. As it is shown in figure 5, the transfer function Acm(s of common mode feedback loop gain) it is:

$A_{\mathrm{cm}}\left(s\right)=\frac{A_{\mathrm{cmfb}}\left(0\right)A_b\left(0\right)A_2\left(0\right)(1+\frac{s}{z})}{(1+\frac{s}{\mathrm{pA}})(1+\frac{s}{\mathrm{pB}})(1+\frac{s}{\mathrm{pC}})}=\frac{A_{\mathrm{cmfb}}\left(0\right)A_b\left(0\right)A_2\left(0\right)(1+\frac{s}{z1})}{(1+\frac{s}{p1})(1+\frac{s}{p2})(1+\frac{s}{p4})}---\left(14\right)$

Wherein Acmfb(0), Ab(0), A2(0) DC current gain of respectively corresponding part. Analyzed it can be seen that pA=p1 is dominant pole by wave chopping technology, pC=p2 is time limit, and pC=p4 is high frequency poles, and z=z1 is zero point, it is possible to zero point is transferred in time same frequency of limit, increases system stability, i.e. p1 < p2=z1 < p4. If z1=p2, then loop gain becomes:

$A_{\mathrm{cm}}\left(s\right)=\frac{A_{\mathrm{cmfb}}\left(0\right)A_b\left(0\right)A_2\left(0\right)}{(1+\frac{s}{p1})(1+\frac{s}{p4})}---\left(15\right)$

Only need to meet:Common mode feedback loop just can reach steady statue.

As it is shown on figure 3, adopt at difference output end electric capacity C1 and the C2 of chopping operational amplifier, then the value of sampling output Vsample is:

V_sample=(VOUTN+VOUTP)/2(16)

The Vsample produced after capacitance partial pressure is:

V_sample=(C1*VOUTN+C2*VOUTP)/(C1+C2) (17)

From formula (17), it is not difficult to find out that working as C1=C2, Vsample is (VOUTN+VOUTP)/2, is the meansigma methods of differential output voltage.And owing to adopting electric capacity sampling, gain is unaffected.

By Fig. 4, common-mode feedback technology is analyzed, the VOUTN sampled out, the meansigma methods of VOUTP and VREF compare, owing to PM4 is fixed value from current reference mirror image gained electric current, when the VD of sampling raises, differential pair tube PM7 gate source voltage reduces, the voltage making C point can reduce, so that the NM1 controlled, the grid of NM2 drags down, and NM1, NM2 gate source voltage reduces, make A, the voltage that B is 2 is driven high, NM3, NM4 works in common source state, grid is driven high, owing to gate source voltage increases, VOUTN, VOUTP is pulled low, D point is dragged down again, recover normal duty, play the effect of common-mode feedback. contrary, when the VD of sampling declines, differential pair tube PM7 gate source voltage increases, the voltage making C point can be elevated, so that the grid of NM1, NM2 of controlling raises, and NM1, NM2 gate source voltage increases, the voltage making A, B 2 is pulled low, NM3, NM4 work in common source state, and grid is pulled low, owing to gate source voltage reduces, VOUTN, VOUTP are driven high, D point is drawn high again, recovers normal duty, also can play the effect of common-mode feedback.

The present invention has good practicality for the low imbalance of needs, low noise, high accuracy Full differential operational amplifier, but also there will be some problems when using wave chopping technology and electric capacity common-mode feedback technology. Wave chopping technology can eliminate the noise of operational amplifier, but switch switching can introduce kT/C thermal noise, and along with the increase of number of switches, thermal noise level will increase, therefore according to application demand, it is necessary to weigh between 1/f noise and thermal noise.

Claims (1)

1. based on the high accuracy fully-differential amplifier of wave chopping technology, it is characterised in that include the first to the second multiplier, the first to the 3rd operational amplifier, the first to the second electric capacity; Wherein, two inputs of the first multiplier connect the first voltage input end and the second voltage input end, the first outfan connect the in-phase input end of the first operational amplifier, the second outfan connects the inverting input of the first operational amplifier respectively; The reversed-phase output of the first operational amplifier connects the first input end of the second multiplier, in-phase output end connects the second input of the second multiplier; First outfan of the second multiplier connects the in-phase input end of the second operational amplifier, the second outfan connects the inverting input of the second operational amplifier; The reversed-phase output of the second operational amplifier as the first voltage output end of difference amplifier, in-phase output end as the second voltage output end of difference amplifier; One end of first electric capacity connects the reversed-phase output of the second operational amplifier, one end of second electric capacity connects the in-phase output end of the second operational amplifier, and the other end of the first electric capacity and the other end of the second electric capacity connect and input the inverting input of the 3rd operational amplifier; 3rd operational amplifier in-phase input end connect reference voltage, outfan and connect the 3rd input of the first operational amplifier; Described first operational amplifier and the second operational amplifier are chopper-stabilized operational amplifiers;

Described first operational amplifier includes the first PMOS, the 5th PMOS, the 6th PMOS, the first NMOS tube and the second NMOS tube, described second operational amplifier includes the second PMOS, the 3rd PMOS, the 3rd NMOS tube, the 4th NMOS tube, first to fourth electric capacity, the first to the second resistance, and described 3rd operational amplifier includes the 4th PMOS, the 7th PMOS, the 8th PMOS, the 5th NMOS tube and the 6th NMOS tube;

The source electrode of first to fourth PMOS all connects power supply, grid and all connects a reference source voltage signal;

The drain electrode of the first PMOS is connected with the source electrode of the 5th PMOS and the 6th PMOS, the grid of the 5th PMOS and the first outfan of the first multiplier connect, draining is connected with the drain electrode of the first NMOS tube and the second input of the second multiplier, and the grid of the 6th PMOS and the second outfan of the first multiplier connect, draining is connected with the drain electrode of the second NMOS tube and the first input end of the second multiplier;

The grid of the first NMOS tube and the second NMOS tube is connected with the drain and gate of the drain electrode of the 7th PMOS, the 5th NMOS tube after connecting;

The drain electrode of the second PMOS is connected the second voltage output end as difference amplifier with one end of the 3rd electric capacity and the drain electrode of the 3rd NMOS tube, and is connected with one end of the second electric capacity;

The other end of the 3rd electric capacity and one end of the first resistance connect, and the other end of the first resistance and the grid of the 3rd NMOS tube are connected with the second outfan of the second multiplier after connecting;

One end of second resistance is connected with the first outfan of the second multiplier after being connected with the grid of the 4th NMOS tube, and the other end of the second resistance and one end of the 4th electric capacity connect;

The drain electrode of the other end of the 4th electric capacity and the drain electrode of the 3rd PMOS, the 4th NMOS tube connects the first voltage output end as difference amplifier, and is connected with one end of the first electric capacity;

The other end of the first electric capacity and the other end of the second electric capacity are connected with the grid of the 7th PMOS after connecting, and the drain electrode of the source electrode of the 7th PMOS and the source electrode of the 8th PMOS and the 4th PMOS connects;

The grid of the 8th PMOS connects reference voltage, drain electrode is connected with the drain and gate of the 6th NMOS tube;

The source ground of the first to the 6th NMOS tube.