CN207427125U

CN207427125U - One kind is based on DSP parallel data mouth AD analog-digital conversion data sampling systems

Info

Publication number: CN207427125U
Application number: CN201720567072.3U
Authority: CN
Inventors: 李科奕; 侯斌
Original assignee: WUXI OPTIMUM TECHNOLOGY Co Ltd
Current assignee: WUXI OPTIMUM TECHNOLOGY Co Ltd
Priority date: 2017-05-22
Filing date: 2017-05-22
Publication date: 2018-05-29
Anticipated expiration: 2027-05-22

Abstract

One kind the utility model discloses data sampling techniques field is based on DSP parallel data mouth AD analog-digital conversion data sampling systems,Including SB3500 chip modules,Data sync clock module,Serial AD analog-digital conversion data sampling module and voltage input module,The input terminal of the serial AD analog-digital conversion data sampling module is electrically connected the output terminal of data sync clock module,The output terminal of the data sync clock module is electrically connected the input terminal of SB3500 chip modules,The utility model proposes one kind be based on DSP parallel data mouth AD analog-digital conversion data sampling systems,Simultaneously and concurrently data-interface based on SB3500,Extend the application of serial date transfer,It is simple in structure,It is easy to use,The effective application system for extending exploitation SB3500 chip PSD interface incoming serial AD modulus data sampling Designs.

Description

One kind is based on DSP parallel data mouth AD analog-digital conversion data sampling systems

Technical field

The utility model is related to data sampling techniques fields, are specially that one kind is based on DSP parallel data mouth AD analog-to-digital conversions Sampled-data system.

Background technology

SB3500 chips are the communication dsp chips of a low-power consumption, and there are three DSP core and an ARM cores, tools for the chip There is powerful data-handling capacity.And how to be a key point by the input and output of big data.The chip devises four simultaneously Row high speed interface.How reasonably to receive serial data using the parallel data port becomes an expansion of the chip application Open up key applications.For this purpose, it is proposed that a kind of be based on DSP parallel data mouth AD analog-digital conversion data sampling systems.

Utility model content

The purpose of this utility model is to provide one kind to be based on DSP parallel data mouth AD analog-digital conversion data sampling systems, To solve the problems mentioned in the above background technology.

To achieve the above object, the utility model provides following technical solution：One kind is based on DSP parallel data mouth AD moduluses Change data sampling system, including SB3500 chip modules, data sync clock module, serial AD analog-digital conversion data sampling mould Block and voltage input module, the output terminal of the voltage input module are electrically connected serial AD analog-digital conversion data sampling module Input terminal, the input terminal of the serial AD analog-digital conversion data sampling module are electrically connected the output of data sync clock module End, the output terminal of the data sync clock module are electrically connected the input terminal of SB3500 chip modules, the SB3500 chips Module and the two-way electric connection of serial AD analog-digital conversion data sampling module.

Preferably, the SB3500 chip modules lead to including the first DSP core, the second DSP core, the 3rd DSP core and 4 PSD Road, and 4 PSD passages connect each DSP core respectively.

Preferably, every group of PSD passage has 16 data lines, a direction line and a synchrodata clock line.

Preferably, the serial AD analog-digital conversion data sampling module is 24 Bits Serial of single channel sigma-delta type synchronized sampling The analog-digital converter of data output.

Compared with prior art, the beneficial effects of the utility model are：The utility model proposes one kind be based on DSP it is parallel Data port AD analog-digital conversion data sampling systems, the simultaneously and concurrently data-interface based on SB3500 extend serial date transfer Application, it is simple in structure, easy to use, effectively extend exploitation SB3500 chip PSD interface incoming serial AD modulus datas The application system of sampling Design.

Description of the drawings

Fig. 1 is the utility model principle block diagram；

Fig. 2 is that the serial AD modulus conversion chip of the utility model samples schematic diagram；

Fig. 3 is the serial data output timing diagram of the serial AD analog-digital conversion data sampling module of the utility model；

Fig. 4 is the serial AD analog-digital conversion data sampling module schematic diagram of the utility model；

Fig. 5 is the data sync clock module principle figure of the utility model.

In figure：When 1 SB3500 chip modules, 11 first DSP cores, 12 second DSP cores, 13 the 3rd DSP cores, 2 data synchronization Clock module, 3 serial AD analog-digital conversion data sampling modules, 4 voltage input modules.

Specific embodiment

The following is a combination of the drawings in the embodiments of the present utility model, and the technical scheme in the embodiment of the utility model is carried out It clearly and completely describes, it is clear that the described embodiments are only a part of the embodiments of the utility model rather than whole Embodiment.Based on the embodiment in the utility model, those of ordinary skill in the art are without making creative work All other embodiments obtained shall fall within the protection scope of the present invention.

- 5 are please referred to Fig.1, the utility model provides a kind of technical solution：One kind is turned based on DSP parallel data mouth AD moduluses Sampled-data system is changed, including SB3500 chip modules 1, data sync clock module 2, serial AD analog-digital conversion data sampling mould Block 3 and voltage input module 4, the output terminal of the voltage input module 4 are electrically connected serial AD analog-digital conversion data sampling mould The input terminal of block 3, the input terminal of the serial AD analog-digital conversion data sampling module 3 are electrically connected data sync clock module 2 Output terminal, the output terminal of the data sync clock module 2 is electrically connected the input terminal of SB3500 chip modules 1, described The 3 two-way electric connection of SB3500 chip modules 1 and serial AD analog-digital conversion data sampling module, the data sync clock module 2 are used to data sync clock being sent to SB3500 chip modules 1 and serial AD analog-digital conversion data sampling module 3, the string Voltage input signal is changed into serial digital signal and exports by row AD analog-digital conversion datas sampling module 3 gives SB3500 chip modules 1。

SB3500 chip modules 1 are to utilize a previously designed SB3500 minimum systematic module, can be directly from market Upper purchase obtains, it has drawn PSD interfaces, and PSD interface sections are only drawn in order to simplify, and there are three DSP for SB3500 chip modules Core, chip have 4 PSD passages, connect each DSP core respectively, and each PSD passages have 16 data lines, a direction line and one Root clock line.Each PSD passage provides two kinds of functions：

1. in the rising edge and trailing edge of PSD_CLK, the data input channel of 16bit；

2. in the rising edge and trailing edge of PSD_CLK, the data output channel of 16bit；

The input and output direction of direction line control passage, PSD passages 1 and passage 2 distribute to the first DSP core 13, PSD passages 3 and PSD passages 4 distribute to the second DSP core 12 and the 3rd DSP core 13, and PSD_CLK frequencies reach as high as 50MHz.

The serial AD analog-digital conversion data sampling module 3 is defeated for single channel sigma-delta type 24 Bits Serial data of synchronized sampling The analog-digital converter gone out, the principles of input and output method as shown in Figure 2.

Input voltage is between 0~+Vref.Here Vref is designed as 1.024V, when control source is 0V, serial AD Analog-to-digital conversion sampling output is 0,24 edges of data sync clock in a manner of serial data, in the low period of FSO Between output on a data lines SDO, it is high-order preceding, the sequence diagram of serial data output as shown in Figure 3, when control source is During 1.024V, the sampling output of serial AD analog-to-digital conversion is 0xFFFFFF, by 24 edges of data sync clock with serial data Mode, between the low period of FSO, export on a data lines SDO, high-order preceding, remaining median is continuously linear Binary coding, physical circuit figure are shown in Fig. 4, PSD4 mouthfuls of high-order PSD_4_15 are connected on the output SDO of AD7764, by PSD4 The high-order PSD_4_14 of mouth is connected on the FSO of AD7764, and CLK meets the SCO of AD7764.

In Fig. 5, data sync clock module 2 is using number of the identical frequency to AD7764 for being externally supplied a 4.56MHz According to the data sync clock mouth PSD_CLK_4 of synchronised clock mouth SCO and PSD4.

While there has been shown and described that the embodiment of the utility model, for the ordinary skill in the art, It is appreciated that in the case where not departing from the principle of the utility model and spirit can these embodiments be carried out with a variety of variations, repaiied Change, replace and modification, the scope of the utility model are defined by the appended claims and the equivalents thereof.

Claims

1. one kind is based on DSP parallel data mouth AD analog-digital conversion data sampling systems, including SB3500 chip modules（1）, data Synchronised clock module（2）, serial AD analog-digital conversion data sampling module（3）And voltage input module（4）, it is characterised in that：Institute State voltage input module（4）Output terminal be electrically connected serial AD analog-digital conversion data sampling module（3）Input terminal, the string Row AD analog-digital conversion data sampling modules（3）Input terminal be electrically connected data sync clock module（2）Output terminal, the number According to synchronised clock module（2）Output terminal be electrically connected SB3500 chip modules（1）Input terminal, the SB3500 chip modules （1）With serial AD analog-digital conversion data sampling module（3）Two-way electric connection.

2. according to claim 1 a kind of based on DSP parallel data mouth AD analog-digital conversion data sampling systems, feature exists In：The SB3500 chip modules（1）Including the first DSP core（11）, the second DSP core（12）, the 3rd DSP core（13）With 4 PSD Passage, and 4 PSD passages connect each DSP core respectively.

3. according to claim 2 a kind of based on DSP parallel data mouth AD analog-digital conversion data sampling systems, feature exists In：Every group of PSD passage has 16 data lines, a direction line and a synchrodata clock line.

4. according to claim 1 a kind of based on DSP parallel data mouth AD analog-digital conversion data sampling systems, feature exists In：The serial AD analog-digital conversion data sampling module（3）For the output of 24 Bits Serial data of single channel sigma-delta type synchronized sampling Analog-digital converter.