CN205450869U - Clock synchronization circuit between multimode group - Google Patents
Clock synchronization circuit between multimode group Download PDFInfo
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- CN205450869U CN205450869U CN201620232269.7U CN201620232269U CN205450869U CN 205450869 U CN205450869 U CN 205450869U CN 201620232269 U CN201620232269 U CN 201620232269U CN 205450869 U CN205450869 U CN 205450869U
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Abstract
The utility model relates to a clock synchronization circuit between multimode group, include: fundamental mode group and a plurality of module of following, fundamental mode group is provided with CPU chip and the RTC chip that is connected, and each all is provided with the CPU chip from the module, COM communication interface and each of the fundamental mode CPU of group chip are connected from the COM communication interface homogeneous phase of module CPU chip, RTC chip INT interrupt signal output interface and each of fundamental mode group are connected from the CPU chip INT signal interface homogeneous phase of module. The utility model discloses a synchronous to the time circuit structure simple, with low costs, to the time precision high, resource consumption is little, little to the communication influence, the reliability is high.
Description
Technical field
This utility model relates to the clock synchronization circuit carrying out collaborative work between a kind of many modules.
Background technology
Common many module devices, need collaborative work between module, need to accomplish that clock synchronizes between the most multiple modules.
During the transmissions pair such as clock between existing many modules synchronizes, and is mostly to use common communication channel such as RS232, RS485, Ethernet, information completes Clock Synchronization Procedure, or when using special clock synchronization mode such as IRIG-B pair.When using common communication channel pair, easily being blocked by communication time delay and communication and affected, cause clock synchronization accuracy to reduce, its reliability is relatively low, simultaneously higher to communication apparatus resource occupation, affects the mutual of other information between module.And mode when using special IRIG-B pair, it is greatly increased again cost.Improve system complexity, plant maintenance is run and adversely affects.
Utility model content
The purpose of this utility model be to provide a kind of low cost, pair time precision is high, resource occupation is little, reliability is high clock synchronization circuit.
The technical scheme that this utility model is taked is: clock synchronization circuit between a kind of many modules, and including: main module and some from module, main module is provided with the cpu chip and RTC chip being connected, and is respectively provided with cpu chip from module；The COM communication interface of described main module cpu chip be respectively all connected from the COM communication interface of module cpu chip；The RTC chip INT interrupt signal output interface of described main module be respectively all connected from the cpu chip INT signal interface of module.
Described main module RTC chip has alarm clock function.
Described have INT interrupt signal receive capabilities from module cpu chip.
Described have information temporary storage and clocking capability from module CPU.
Principle of the present utility model: the cpu chip of main module is first to all time values when module cpu chip sends preparation pair by COM communication interface, again by main module RTC chip to from module CPU tranmitting data register lock-out pulse, clock sync pulse is received from module, it is time value during preparation pair by clock setting, completes clock and synchronize to arrange.
Synchronization time setting circuit simple in construction of the present utility model, low cost, pair time precision high, resource occupation is little, and little on communication impact, reliability is high.
Accompanying drawing explanation
Fig. 1 is the functional block diagram of one detailed description of the invention of this utility model.
Fig. 2 is workflow diagram of the present utility model.
Detailed description of the invention
Fig. 1 is the schematic block circuit diagram of one detailed description of the invention of this utility model, including being arranged at cpu chip and the RTC chip (having alarm clock function) of main module and being arranged atnThe individual cpu chip from module.The COM communication interface of described main module cpu chip is connected from module cpu chip COM communication interface with described, and the RTC chip INT interrupt signal output interface of described main module is connected with the described cpu chip INT signal interface from module (having INT interrupt signal receive capabilities)；The cpu chip of described main module is connected with RTC chip.
Fig. 2 is the working method flow chart of above-mentioned detailed description of the invention, and it is as follows that its clock synchronizes flow process:
The cpu chip of the main module of S1 passes through the infomational message of COM communication interface time point t0 to respectively from the transmission preparation pair of module cpu chip time；
S2 is respectively after module CPU receives this information, by time point t0 information temporary storage；
The cpu chip of the main module of S3 arranges RTC chip alarm clock function, and its alarm clock opening time point is set to t0；
S4 is when time point t0 arrives, and RTC chip alarm clock is opened；The INT signal interface level conversion of RTC chip, produces clock sync pulse, exports to each from the INT signal interface of module cpu chip；
S5 respectively from the INT signal interface of module cpu chip to after the clock sync pulse interrupt signal that main module RTC chip produces, make an immediate response, will receive in advance t0 time point information write timer；Complete and the Clock Synchronization Procedure of main module.
Claims (4)
1. clock synchronization circuit between module more than a kind, it is characterised in that including: main module and some from module, main module is provided with the cpu chip and RTC chip being connected, and is respectively provided with cpu chip from module；The COM communication interface of described main module cpu chip be respectively all connected from the COM communication interface of module cpu chip；The RTC chip INT interrupt signal output interface of described main module be respectively all connected from the cpu chip INT signal interface of module.
Clock synchronization circuit between many modules the most according to claim 1, it is characterised in that described main module RTC chip has alarm clock function.
Clock synchronization circuit between many modules the most according to claim 1, it is characterised in that described have INT interrupt signal receive capabilities from module cpu chip.
Clock synchronization circuit between many modules the most according to claim 1 and 2, it is characterised in that described have information temporary storage and clocking capability from module CPU.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620232269.7U CN205450869U (en) | 2016-03-24 | 2016-03-24 | Clock synchronization circuit between multimode group |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620232269.7U CN205450869U (en) | 2016-03-24 | 2016-03-24 | Clock synchronization circuit between multimode group |
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| Publication Number | Publication Date |
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| CN205450869U true CN205450869U (en) | 2016-08-10 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201620232269.7U Active CN205450869U (en) | 2016-03-24 | 2016-03-24 | Clock synchronization circuit between multimode group |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112558685A (en) * | 2020-12-11 | 2021-03-26 | 南京四方亿能电力自动化有限公司 | Time synchronization method for power distribution terminal modules |
-
2016
- 2016-03-24 CN CN201620232269.7U patent/CN205450869U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112558685A (en) * | 2020-12-11 | 2021-03-26 | 南京四方亿能电力自动化有限公司 | Time synchronization method for power distribution terminal modules |
| CN112558685B (en) * | 2020-12-11 | 2024-05-10 | 南京四方亿能电力自动化有限公司 | Method for synchronizing time between power distribution terminal modules |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 410205 No. 468 west slope, Changsha hi tech Industrial Development Zone, Changsha, Hunan, Yuelu District, Tongzi Patentee after: WILLFAR INFORMATION TECHNOLOGY Co.,Ltd. Address before: 410205 No. 468 west slope, Changsha hi tech Industrial Development Zone, Changsha, Hunan, Yuelu District, Tongzi Patentee before: HUNAN WEISHENG INFORMATION TECHNOLOGY CO.,LTD. |
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| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: 410205 No. 468 west slope, Changsha hi tech Industrial Development Zone, Changsha, Hunan, Yuelu District, Tongzi Patentee after: HUNAN WEISHENG INFORMATION TECHNOLOGY CO.,LTD. Address before: 410205 Tongzi, Changsha, Changsha hi tech Development Zone, west slope road, No. 468, Patentee before: CHANGSHA WASION INFORMATION TECHNOLOGY Co.,Ltd. |