CN204180093U

CN204180093U - A kind of PPS system balance device based on FPGA

Info

Publication number: CN204180093U
Application number: CN201420657203.3U
Authority: CN
Inventors: 王波; 史亚萍; 涂桂旺; 邱旭强
Original assignee: YANTAI CHIJIU CLOCK-WATCH Co Ltd
Current assignee: YANTAI CHIJIU CLOCK-WATCH Co Ltd
Priority date: 2014-11-06
Filing date: 2014-11-06
Publication date: 2015-02-25
Anticipated expiration: 2024-11-06

Abstract

The utility model relates to a kind of PPS system balance device based on FPGA, comprise time source and receive Synchronization Component, the output that time source receives Synchronization Component is connected to time delay adjustment assembly, Time delay measurement assembly, the output of time delay adjustment assembly is connected with multichannel PPS in-out box, multichannel PPS in-out box is connected with user side, the signal of user side input is connected with Time delay measurement assembly through multichannel PPS in-out box, and Time delay measurement assembly and time delay adjust between assembly and be connected with parameter memory module.This compensation arrangement when in use only need time source place arrange 1, just exportable multichannel is through compensated PPS signal, without the need to a large amount of test, the various user terminal of automatic adaptation, automatic identification, calculating, compensation PPS, just can improve its precision, when making PPS arrive user terminal, just in time eliminate the time delay transmitted and bring, thus ensure that the clock of whole system obtains stringent synchronization; Be convenient to maintenance, management simultaneously, control.

Description

A kind of PPS system balance device based on FPGA

Technical field

The utility model relates to a kind of clock compensation device, is a kind of PPS system balance device based on fpga chip specifically.

Background technology

Base station digital trunk network needs PPS Timing Synchronization, and requires high accuracy, and PPS directly transmits, and will produce time delay, and cause digital trunk network asynchronous when arriving user terminal.General solution increases PPS synchronous compensator plant at user terminal.

Existing PPS synchronous compensator plant structure, the transmission of PPS is generally by various transmission medium, is transported to each user terminal.And because medium kind, loss, transmission range different, after clock arrives each user terminal, can there is the time delay skew of distinct program in PPS.Traditional solution is artificial injecting compensating.But this method has three weak points, the first, need a large amount of measurement data, and be positioned at the different user terminals of different location, all need to retest, reset compensating parameter, workload is large, and relate to region wide, human cost is high.The second, because the difference of user terminal, the parameter of injection is excessive at reference time delay, and the parameters precision arranged after resulting through artificial measurement is too low.3rd, each user terminal needs to arrange a PPS synchronous compensator plant, system complex, involves great expense.

Summary of the invention

The purpose of this utility model be to solve in prior art user terminal increase measurement data that PPS synchronous compensator plant brings often, workload is large, precision is low, cost is high deficiency, a kind of reasonable in design is provided, system is simple, be easy to operation, improve precision, the PPS system balance device based on FPGA field-programmable reduced costs.

This PPS system balance device based on FPGA is achieved through the following technical solutions:

A kind of PPS system balance device based on FPGA, its special character is that the time source comprising reception source PPS signal receives Synchronization Component 1, the output that time source receives Synchronization Component 1 is connected to time delay adjustment assembly 2, Time delay measurement assembly 3, the output of time delay adjustment assembly 2 is connected with multichannel PPS in-out box 4, multichannel PPS in-out box 4 is connected with user side, the signal of user side input is connected with Time delay measurement assembly 3 through multichannel PPS in-out box 4, and Time delay measurement assembly 3 and time delay adjust between assembly 2 and be connected with parameter memory module 5;

In order to compensate while realizing multiple user, one of the present utility model is improved and is: described multichannel PPS in-out box 4 is PPS in-out box more than 72 roads or 72 tunnels.

A kind of PPS system balance device based on FPGA of the present utility model, only need time source place 1 PPS synchronous compensator plant is set, the exportable multichannel of this device, through compensated PPS signal, without the need to a large amount of test, the various user terminal of automatic adaptation, automatic identification, calculating, compensation PPS, just can improve its precision greatly, when making PPS arrive user terminal, just in time eliminate the time delay transmitted and bring, thus ensure that the clock of whole system obtains stringent synchronization; Be convenient to maintenance, management simultaneously, control.

Accompanying drawing explanation

Fig. 1: structural representation of the present utility model.

Embodiment

Provide embodiment of the present utility model below with reference to accompanying drawing, be used for being described further the utility model.

Embodiment 1: with reference to figure 1.A kind of PPS system balance device based on FPGA, the time source comprising reception source PPS signal receives Synchronization Component 1, the output that time source receives Synchronization Component 1 is connected to time delay adjustment assembly 2, Time delay measurement assembly 3, the output of time delay adjustment assembly 2 is connected with 72 road PPS in-out boxs 4, 72 road PPS in-out boxs 4 are connected with user side, the signal of user side input is connected with Time delay measurement assembly 3 through 72 road PPS in-out boxs 4, Time delay measurement assembly 3 and time delay adjust between assembly 2 and are connected with parameter memory module 5, different assembly is connected by the mutual communication of the hardware circuit of FPGA field programmable gate array.

Using method of the present utility model: after PPS synchronous compensator plant of the present utility model initially powers on, receive Synchronization Component 1 by time source and receive source PPS signal, and simultaneously by synchronous for source PPS signal, then time delay adjustment assembly 2 and Time delay measurement assembly 3 is sent to respectively by by the PPS signal after synchronous, time delay adjustment assembly 2 reads the parameter in parameter memory module 5, then adjust different sequential PPS signal according to the different delay parameter of each passage to export, then output to different user terminals by multichannel in-out box 4.Each passage PPS signal outputs to user terminal, and carry out being looped back to multichannel in-out box 4 at user terminal, multichannel in-out box 4 sends to Time delay measurement assembly 3 after receiving the PPS signal of loopback, PPS signal after synchronous with source for the loopback signal received contrasts by Time delay measurement assembly 3, automatic measurement, filtration, calculating, draw the delay data of different passage.After measurement completes, be just automatically recorded in parameter memory module 5, be convenient to time delay adjustment assembly read latch parameter next time.Time delay adjustment assembly 2 can constantly to PPS signal, read parameter adjustment output → loopback → measurement → write parameters → reading parameter adjustment output again, repeat above process, finally obtain highly stable, accurate, a reliable time delay synchronous, use the synchronization accuracy of user terminal to obtain and promote greatly.

Protection range of the present utility model is not limited to above embodiment; such as multiple-channel output input module 4 is the output input module on more than 72 tunnels; every PPS system balance device based on FPGA identical or equivalent with utility model technical scheme structure, all belongs to protection range of the present utility model.

Claims

1. the PPS system balance device based on FPGA, it is characterized in that the time source comprising reception source PPS signal receives Synchronization Component (1), the output that time source receives Synchronization Component (1) is connected to time delay adjustment assembly (2), Time delay measurement assembly (3), the output of time delay adjustment assembly (2) is connected with multichannel PPS in-out box (4), multichannel PPS in-out box (4) is connected with user side, the signal of user side input is connected with Time delay measurement assembly (3) through multichannel PPS in-out box (4), Time delay measurement assembly (3) and time delay adjust between assembly (2) and are connected with parameter memory module (5).

2., according to the PPS system balance device based on FPGA a kind of described in claim 1, it is characterized in that described multichannel PPS in-out box (4) is the PPS in-out box on >=72 tunnels.