CN204859318U - A video acquisition , processing and intensifier circuit for medical endoscope - Google Patents
A video acquisition , processing and intensifier circuit for medical endoscope Download PDFInfo
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- CN204859318U CN204859318U CN201520470700.7U CN201520470700U CN204859318U CN 204859318 U CN204859318 U CN 204859318U CN 201520470700 U CN201520470700 U CN 201520470700U CN 204859318 U CN204859318 U CN 204859318U
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Abstract
The utility model relates to a video acquisition, processing and intensifier circuit for medical endoscope, its characterized in that: including video acquisition chip, image manipulation chip and image enhancement chip, video data after the video acquisition chip will be gathered sends to image manipulation chip and handles, image manipulation chip handles the back to image data, redispatches to the image enhancement chip and carries out the humidifying treatment. Compared with the prior art, the utility model discloses a divide a plurality of functional modules into in the video acquisition chip, distinguish and by the independent coordination work of each functional module, can realize low -power consumption, low light level to and can the picture high definition more of output. It is further the utility model discloses an increase by an image manipulation chip in camera lens part, handle the image of gathering, increase by an image enhancement chip on the host computer backstage, carry out second grade image enhancement, make the image of last output more clear.
Description
Technical field
The utility model relates to a kind of video capture circuit, particularly a kind of video acquisition process for medical endoscope and intensifier circuit.
Background technology
Endoscope is a kind of conventional medicine equipment, is become by flexible part, light source and an arrangement of mirrors head group.Through the natural hole of human body, or the minimal incision * that underwent operative is done enters in human body, during use, endoscope is imported the organ of preliminary examination, directly can spy on the change of relevant portion.
Wherein, the quality of picture quality directly affects the result of use of endoscope.Existing general use fujinon electronic video endoscope is observed.Electronic imaging element-CCD (charge coupled device) that common fujinon electronic video endoscope adopts size minimum, object in the chamber that will observe is imaged onto on CCD by small objective lens optical system, then as fibre bundle, the picture signal received is delivered on image processing system by leading, image after last output processing on a monitor, observes and diagnosis for doctor.But still there is the defect that power consumption is too high, image quality is clear not in existing CCD chip.
Meanwhile, existing general use fujinon electronic video endoscope is observed, and the treatment system image after observation being sent to outside connection carries out image procossing.But, during owing to carrying out IMAQ in human body, can due to a variety of causes of inside of human body, and cause occurring noise jamming, brightness cannot regulate or cause due to the color of light image to occur aberration automatically, so cause in the image procossing in later stage, being difficult to the image of rediscover, making doctor be difficult to identification when observing.
Utility model content
The utility model is to overcome the shortcoming of prior art with not enough, provides a kind of high definition, low-power consumption, the video acquisition for medical endoscope of low-light (level), process and intensifier circuit.
The utility model is achieved through the following technical solutions: a kind of video acquisition for medical endoscope, process and intensifier circuit, comprise video capture processor, picture processing chip and image enhaucament chip, the video data after collection is sent to picture processing chip and processes by described video capture processor; After described picture processing chip processes view data, then be sent to image enhaucament chip carry out enhancing process;
Described video capture processor inside comprises: controller, driver, photoreceptor, sampler and follower;
---described controller, it sends triggering signal to driver for receiving outside triggering signal;
---described driver, it for receiving the triggering signal of controller, and drives photoreceptor work;
---described photoreceptor, this light signal for receiving extraneous light signal, and is converted to the signal of telecommunication by it;
---described sampler, the signal of telecommunication processed for carrying out sampling process to the signal of telecommunication of photoreceptor, and is sent to follower by it;
---described follower, it is for being converted to digital signal by this signal of telecommunication, line output of going forward side by side picture processing chip;
Described picture processing chip comprises: data sink, master controller, image processor, data logger;
---described data sink, it is for receiving outside view data;
---described master controller, it is for receiving outside triggering signal, and the operating state of the described data sink of corresponding control, image processor and data logger;
---described image processor, it is for processing image; Described image processor comprises a white balance permanent circuit, and it, for according to the parameter preset, carries out the fixed adjustment of white balance;
---described data logger, it is for exporting the view data after process;
Described image enhaucament chip comprises: data sink, controller, static memory, image intensifier, data logger and clock generator;
---described data sink, it is for receiving viewdata signal, and is sent to this image intensifier;
---described controller, it is for receiving outer triggering signal, and the operating state of corresponding control data receiver, image enhaucament itself and data logger;
---described static memory, it is for the driving data of memory image booster, to drive the work of this image intensifier;
---described image intensifier, it comprises an image border intensifier circuit; Described image border intensifier circuit is for strengthening the definition of image border;
---described data logger, it for receiving the view data after image intensifier process, and carries out data output;
---described clock generator, it is for being image enhaucament chip clocking.
Compared to prior art, the utility model by being divided into multiple functional module in video capture processor, and difference also by each functional module independence co-ordination, can realize low-power consumption, low-light (level), and can be the picture high definition more exported.
Further the utility model, by increasing by a picture processing chip in camera lens part, processes the image gathered, main frame backstage increases an image enhaucament chip, carries out level image enhancing, makes the last image exported more clear.
First, in picture processing chip, be divided into multiple functional module, difference also by each functional module independence co-ordination, can realize low-power consumption, low-light (level), and can be the picture high definition more exported.Meanwhile, a white balance permanent circuit being set in this image processor further, for being fixed by this white balance parameter, without the need to operationally carrying out the adjustment of white balance, thus preventing the phenomenon of aberration interference.
Then, in image enhaucament chip, be also divided into multiple functional module, difference also by each functional module independence co-ordination, can realize the enhancing process to image.Meanwhile, an image border intensifier circuit is set in this image intensifier further, in order to strengthen the definition of image border.
Further, described video capture processor also comprises a frequency multiplier, and its frequency for the triggering signal inputted outside carries out doubling process, then is sent to controller;
Described picture processing chip also comprises a frequency multiplier, and its frequency for the triggering signal inputted outside carries out doubling process, then is sent to master controller; Described image enhaucament chip also comprises a de-noising processor; The viewdata signal that described data sink receives, is sent to de-noising processor and carries out noise reduction process, then be forwarded to image intensifier.
Further, the image processor in described picture processing chip also comprises an exposure gain circuit, for increasing exposure gain size;
Described image enhaucament chip also comprises a dynamic memory; View data after described de-noising processor process, is first sent to dynamic memory and stores, then be forwarded to image intensifier.
Further, described image processor also comprises an optical detection circuit and flash detection circuit, its brightness for detection image and flashing state, and result of detection is sent to exposure gain circuit;
Described image enhaucament chip also comprises a vision signal multiplier and a storage signal multiplier; Described clock generator, the clock signal of generation is sent to respectively vision signal multiplier and storage signal multiplier, and by this vision signal multiplier, clock signal is sent to data sink, by this storage signal multiplier, clock signal is sent to dynamic memory and static memory.
Further, described video capture processor outside is provided with: for receive supply power voltage power port, for outputting video signal video signal port, for export row field signal row field signal port, for receiving reference voltage electricity reference signal port and frequently for receiving the clock signal port of external timing signal;
Described picture processing chip outside is provided with: for receive supply power voltage power port, for receive picture signal receiver port, for outputting video signal video signal port, for export row field signal row field signal port, for receive external timing signal clock signal port, store the data receiver port and of data for receiving the PORT COM of external communication order for receiving;
Described image enhaucament chip exterior is provided with: for receive supply power voltage power port, for receive picture signal receiver port, for outputting video signal video signal port, for export row field signal row field signal port, for receiving the clock signal port of external timing signal and storing the data receiver port of data for receiving.
Further, the power port of described video capture processor is circumscribed with one for the filter circuit of voltage stabilizing; Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity;
The power port of described picture processing chip is circumscribed with one for the filter circuit of voltage stabilizing; Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity;
The power port of described image enhaucament chip is circumscribed with one for the filter circuit of voltage stabilizing; Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity.
Further, the row field signal port of described video capture processor is circumscribed with one for providing the resistance of signal strength signal intensity.
Further, the reference signal port of described video capture processor is circumscribed with the electric capacity as voltage electricity frequency reference data.
Further, the external clock circuit of clock signal port of described video capture processor, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port by a debug circuit; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock shake chip power end with to be connected and between inductance and electric capacity; Described debug circuit is made up of resistance and electric capacity; One end of the resistance of this debug circuit is connected with the output of Zhong Zhen, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock signal port is connected between this resistance and electric capacity;
The external clock circuit of described picture processing chip clock signal port, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port by a debug circuit; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock shake chip power end with to be connected and between inductance and electric capacity; Described debug circuit is made up of resistance and electric capacity; One end of the resistance of this debug circuit is connected with the output of Zhong Zhen, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock signal port is connected between this resistance and electric capacity;
The external clock circuit of clock signal port of described image enhaucament chip, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity.
Further, described picture processing chip also comprises communication command port, and it is circumscribed with a mode of operation configuration circuit; Described configuration circuit is made up of two resistant series, and described communication command port is connected between two resistance.
In order to understand better and implement, describe the utility model in detail below in conjunction with accompanying drawing.
Accompanying drawing explanation
Fig. 1 is video capture processor of the present utility model, picture processing chip and image enhaucament chip connection diagram.
Fig. 2 is the internal module connection diagram of video capture processor.
Fig. 3 is the outside port connecting circuit figure of video capture processor.
Fig. 4 is the circuit diagram that the power unit of video capture processor connects.
The voltage place in circuit figure of the 2.7V of Fig. 5 video capture processor.
Fig. 6 is the voltage place in circuit figure of the 1.8V of video capture processor.
Fig. 7 is the voltage place in circuit figure of the 1.2V of video capture processor.
Fig. 8 is the partial enlarged drawing of the row field signal of video capture processor.
Fig. 9 is the partial enlarged drawing of the reference signal port of video capture processor.
Figure 10 is the circuit diagram of the clock circuit of video capture processor.
Figure 11 is the circuit diagram of the configuration circuit of video capture processor.
Figure 12 is the internal module connection diagram of picture processing chip.
Figure 13 is the circuit module schematic diagram of the image processor of picture processing chip.
Figure 14 is the voltage segment circuit diagram of picture processing chip.
Figure 15 is the outside port circuit diagram of picture processing chip.
Figure 16 is the circuit diagram of the filter circuit of the 3.3V voltage of picture processing chip.
Figure 17 is the circuit diagram of the filter circuit of the 1.8V voltage of picture processing chip.
Figure 18 is the circuit diagram of the filter circuit of the 1.2V voltage of picture processing chip.
Figure 19 is the partial enlarged drawing of the receiver port of picture processing chip.
Figure 20 is the partial enlarged drawing of the video signal port of picture processing chip.
Figure 21 is the partial enlarged drawing of the row field signal port of picture processing chip.
Figure 22 is the schematic diagram of the clock circuit of picture processing chip.
Figure 23 is the schematic diagram of the memory circuit of picture processing chip.
Figure 24 is the partial enlarged drawing of the PORT COM of picture processing chip.
Figure 25 is the internal module connection diagram of image enhaucament chip.
Figure 26 is the outside connecting circuit figure of Part I of image enhaucament chip.
Figure 27 is the outside connecting circuit figure of Part II of image enhaucament chip.
Figure 28 is the circuit diagram of the filter circuit of pressure-stabilizing of the 3.3V voltage of image enhaucament chip.
Figure 29 is the power-switching circuit figure that the 3.3V of image enhaucament chip is converted to 1.8V.
Figure 30 is the power-switching circuit figure that the 3.3V of image enhaucament chip is converted to 1.2V.
Figure 31 is the partial enlarged drawing of the receiver port of image enhaucament chip.
Figure 32 is the partial enlarged drawing of the video signal port of image enhaucament chip.
Figure 33 is the circuit diagram of the clock circuit of image enhaucament chip.
Figure 34 is the partial enlarged drawing of the row field signal port of image enhaucament chip.
Embodiment
Refer to Fig. 1, it is video capture processor of the present utility model, picture processing chip and image enhaucament chip connection diagram.The utility model provides a kind of video acquisition for medical endoscope, process and intensifier circuit, comprise video capture processor 10, picture processing chip 20 and image enhaucament chip 30, the video data after collection is sent to picture processing chip 20 and processes by described video capture processor 10; After described picture processing chip 20 pairs of view data process, then be sent to image enhaucament chip 30 carry out enhancing process.
Refer to Fig. 2, it is the internal module connection diagram of video capture processor.Described video capture processor 10 inside comprises: controller 11, driver 12, photoreceptor 13, sampler 14, follower 15 and frequency multiplier 16;
Described controller 11, it sends triggering signal to driver for receiving outside triggering signal;
Described driver 12, it for receiving the triggering signal of controller, and drives photoreceptor work;
Described photoreceptor 13, this light signal for receiving extraneous light signal, and is converted to the signal of telecommunication by it;
Described sampler 14, the signal of telecommunication processed for carrying out sampling process to the signal of telecommunication of photoreceptor, and is sent to follower by it;
Described follower 15, it is for being converted to digital signal by this signal of telecommunication, line output of going forward side by side.
Described frequency multiplier 16, its frequency for the triggering signal inputted outside carries out doubling process, then is sent to controller.Further, conveniently in the requirement of the frequency of utilization of video capture processor, the adjustment being realized frequency by frequency multiplier is amplified.
Please refer to Fig. 3, it is the outside port circuit diagram of video capture processor.In addition in order to adapt to the application of this video capture processor, be provided with in described video capture processor outside: the power port 101 for receiver voltage, the video signal port 102 for outputting video signal, for export row field signal row field signal port one 03, for receiving reference voltage electricity reference signal port one 04 frequently, for receiving the clock signal port 105 of external timing signal and the communication command port one 06 for receiving operate outside mode command.
Please refer to Fig. 4, it is the circuit diagram of the power unit of video capture processor.Concrete, the power unit in video capture processor adopts three kinds of voltages simultaneously, is respectively 2.7V, 1.8V, and 1.2V.
Please refer to Fig. 5-7, it is respectively the circuit diagram of 2.7V, 1.8V and 1.2V of video capture processor.Concrete, the input port 101 of three kinds of voltages of video capture processor is all circumscribed with one for the filter circuit of voltage stabilizing; Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity.Wherein, the voltage place in circuit of 2.7V and 1.8V comprises four electric capacity, and the voltage place in circuit of 1.2V comprises three electric capacity, to filter the interference signal of different frequency.
Refer to Fig. 8, it is the interface enlarged drawing of row field signal.Further, described row field signal port one 03 is circumscribed with one for providing the resistance of signal strength signal intensity.By this row field signal, for controlling frequency and the order of video frequency output.Such as: the display frequency of vision signal on screen and DISPLAY ORDER can be controlled, can be from every line output under upper, also can be export from left to right.
Refer to Fig. 9, it is the partial enlarged drawing of the reference signal port of video capture processor.Further, described reference signal port one 04 is circumscribed with the electric capacity as voltage electricity frequency reference data.In the present embodiment, described reference signal port has 7, the electric capacity of the external 1uF of each port.
Refer to Figure 10, it is the circuit diagram of the clock circuit of video capture processor.The external clock circuit of described clock signal port 105, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port by a debug circuit; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock shake chip power end with to be connected and between inductance and electric capacity; Described debug circuit is made up of resistance and electric capacity; One end of the resistance of this debug circuit is connected with the output of Zhong Zhen, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock signal port is connected between this resistance and electric capacity.
Refer to Figure 11, it is the circuit diagram of the configuration circuit of video capture processor.Further, described communication command port one 06, it is circumscribed with a mode of operation configuration circuit; Described configuration circuit is made up of two resistant series, and described communication command port is connected between two resistance.
Refer to Figure 12, it is the internal module connection diagram of picture processing chip.Described picture processing chip 20 comprises: data sink 21, master controller 22, image processor 23, data logger 24.
Described data sink 21, it is for receiving outside view data;
Described master controller 22, it is for receiving outside triggering signal, and the operating state of the described data sink of corresponding control, image processor and data logger;
Described image processor 23, it is for processing image.
Described data logger 24, it is for exporting the view data after process.
Further, described video capture processor also comprises a frequency multiplier 25, and its frequency for the triggering signal inputted outside carries out doubling process, then is sent to master controller 22.
Refer to Figure 13, it is the circuit module schematic diagram of the image processor of picture processing chip.Concrete, described image processor 23 comprises a Lens Shading Compensation circuit 231, optical detection circuit 232, flash detection circuit 233, exposure gain circuit 234 and white balance permanent circuit 235.
Described Lens Shading Compensation circuit 231, it compensates process for the shade produced by camera lens.
Described optical detection circuit 232 and flash detection circuit 233, its brightness for detection image and flashing state, and result of detection is sent to exposure gain circuit.
Described exposure gain circuit 234, for increasing exposure gain size.
Described white balance permanent circuit 235, it, for according to the parameter preset, carries out the fixed adjustment of white balance.
Please refer to Figure 14 and Figure 15, it is respectively voltage segment and other outside port circuit diagrams of the video capture processor of picture processing chip.In addition, in order to the application in order to adapt to this video capture processor, be provided with in described video capture processor outside further: for receive supply power voltage power port 201, for receive picture signal receiver port 202, for outputting video signal video signal port 203, for export row field signal row field signal port 204, for receive external timing signal clock signal port 205, for receive store data data receiver port 206 and one for receiving the PORT COM 207 of external communication order.
Refer to Figure 16-18, its power supply being respectively picture processing chip is the circuit diagram of 3.3V, 1.8V and 1.2V.Further, described power port 201 is circumscribed with one for the filter circuit of voltage stabilizing; Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity.Concrete, the external voltage of video capture processor of the present utility model comprises: 3.3V, 1.8V and 1.2V tri-kinds.Wherein, 3.3V voltage place in circuit comprises 2 electric capacity, and 1.8V voltage place in circuit comprises 5 electric capacity, and the voltage place in circuit of 1.2V comprises 6 electric capacity, to filter the interference signal of different frequency respectively.
Refer to Figure 19, it is the partial enlarged drawing of the receiver port of picture processing chip.Described receiver port 202 comprises 8 pins, for receiving outside video signal.
Refer to Figure 20, it is the partial enlarged drawing of the video signal port of picture processing chip.Described video signal port 203 comprises the vision signal of two groups of different-formats, carries out doubleway output, plays in real time respectively to facilitate and records.
Refer to Figure 21, it is the partial enlarged drawing of the row field signal port of picture processing chip.Described row field signal port 204 is for controlling frequency and the order of video frequency output.Such as: the display frequency of vision signal on screen and DISPLAY ORDER can be controlled, can be from every line output under upper, also can be export from left to right.
Refer to Figure 22, it is the schematic diagram of the clock circuit of picture processing chip.The external clock circuit of described clock signal port 205, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port by a debug circuit; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock shake chip power end with to be connected and between inductance and electric capacity; Described debug circuit is made up of resistance and electric capacity; One end of the resistance of this debug circuit is connected with the output of Zhong Zhen, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock signal port is connected between this resistance and electric capacity.
Refer to Figure 23, it is the schematic diagram of the memory circuit of picture processing chip.Further, described data receiver port 206 is circumscribed with a memory circuitry, and it comprises a memory, is connected to the filter circuit of the voltage port of this memory, and is connected to the resistance of output port of this memory.
Refer to Figure 24, it is the partial enlarged drawing of the PORT COM of picture processing chip.Described PORT COM 207, for receiving the trigger command of external transmission, carries out work with what trigger this picture processing chip.
Refer to Figure 25, it is the internal module connection diagram of image enhaucament chip.Described image enhaucament chip 30 comprises: data sink 31, de-noising processor 32, dynamic memory 33, image intensifier 34, pixel self adaptation proofreading equipment 35, data logger 36, static memory 37, controller 38, vision signal multiplier 39, storage signal multiplier 310, clock generator 311.
Described data sink 31, it is for receiving viewdata signal, and is sent to de-noising processor 32;
The viewdata signal that described data sink 31 receives, is sent to de-noising processor 32 and carries out noise reduction process, then be forwarded to dynamic memory 33.
After the view data of described dynamic memory 33 after receiving de-noising processor 32 process, then be forwarded to image intensifier 34.
Described image intensifier 34, it comprises an image border intensifier circuit; Described image border intensifier circuit is for strengthening the definition of image border.Further, the view data after process is first sent to described pixel self adaptation proofreading equipment 35 by described image intensifier, carries out pixel and adapts to check and correction, then be sent to data logger 36 by this pixel self adaptation proofreading equipment 25.
Described data logger 36, it for receiving the view data after image intensifier process, and carries out data output;
Described static memory 37, it is for the driving data of memory image booster, to drive the work of this image intensifier;
Described controller 38, it is for receiving outer triggering signal, and the operating state of corresponding control data receiver, image enhaucament itself and data logger;
Described clock generator 311, it is for being image enhaucament chip clocking.Further, described clock generator, the clock signal of generation is sent to respectively vision signal multiplier 39 and storage signal multiplier 310, and by this vision signal multiplier 39, clock signal is sent to data sink, by this storage signal multiplier 310, clock signal is sent to dynamic memory and static memory.
Please refer to Figure 26 and Figure 27, it is respectively the outside connecting circuit figure of image enhaucament chip.
Further, described image enhaucament chip exterior is provided with: for receive supply power voltage power port, for receive picture signal receiver port 301, for outputting video signal video signal port 302, for receive external timing signal clock signal port 303, for exporting the row field signal port 304 of row field signal.
Concrete, in the present embodiment, the external voltage of described power port comprises 3.3V, 1.8V and 1.2V tri-kinds of voltages.Refer to Figure 28, it is the circuit diagram of the filter circuit of pressure-stabilizing of 3.3V voltage.Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity.
Refer to Figure 29-30, it is respectively the change-over circuit figure that power-switching circuit figure and 3.3V that 3.3V is converted to 1.8V is converted to 1.2V.In the present embodiment, by a power-switching circuit, the voltage of 3.3V is converted to respectively the voltage of 1.8V and 1.2V.Concrete, described power-switching circuit comprises a power conversion chip; The voltage of the input access 3.3V of described power conversion chip, output exports the voltage of 1.8V and 1.2V respectively, to power to image enhaucament chip.
Refer to Figure 31, it is the partial enlarged drawing of the receiver port of image enhaucament chip.Described receiver port 301 comprises 20 signal pins, is connected with the data sink 1 of inside, for receiving the picture signal of input.
Refer to Figure 32, it is the partial enlarged drawing of the video signal port of image enhaucament chip.Described video signal port 302 comprises 20 signal pins, and it is connected, for output image signal with inner data logger 6.
Refer to Figure 33, it is the circuit diagram of the clock circuit of image enhaucament chip.Further, the external clock circuit of described clock signal port 303, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity.
Refer to Figure 34, it is the partial enlarged drawing of the row field signal port of image enhaucament chip.Described row field signal port 304 comprises a row signal pins and a field signal pin.Described row field signal port 304 is for controlling frequency and the order of video frequency output.Such as: the display frequency of vision signal on screen and DISPLAY ORDER can be controlled, can be from every line output under upper, also can be export from left to right.
Below the course of work of video acquisition treatment circuit of the present utility model is described:
S11: carry out circuit access according to above-mentioned requirement by the outside port of this video capture processor and picture processing chip;
S12: when video capture processor is energized, first carries out multiplication by this frequency multiplier by input voltage frequency and regulates, to adapt to current operating frequency;
S13: described controller 11 sends triggering signal to driver 12, drives photoreceptor 13 to work by driver 12;
S14: when light is irradiated on photoreceptor 13, is converted to the signal of telecommunication by this photoreceptor 13 by light signal, and transfers to sampler 14;
S15: when sampler 14 receives the signal of telecommunication from photoreceptor 13, carries out sampling process to this signal of telecommunication, and the signal of telecommunication processed is sent to follower 15;
S16: finally by described follower 15, this signal of telecommunication is converted to digital signal, line output of going forward side by side is to picture processing chip.
S17: described data sink 21 receives outside view data;
S18: described image processor 23 pairs of images process.Specifically respectively by described Lens Shading Compensation circuit 231, the shade that camera lens produces is compensated process; By brightness and the flashing state of described optical detection circuit 232 and flash detection circuit 233 detection image, and result of detection is sent to exposure gain circuit; Then exposure gain size is increased by described exposure gain circuit 234.Last again by described white balance permanent circuit 35 according to default parameter, carry out the fixed adjustment of white balance.
S19: the view data after process exports by described data logger 24.
S20: receive outside view data by the data sink 31 of image enhaucament chip;
S21: described data sink 31, receives viewdata signal, and is sent to de-noising processor 32;
S22: described de-noising processor 32 carries out noise reduction process, then is forwarded to dynamic memory 33.
S23: after the view data of described dynamic memory 33 after receiving de-noising processor 32 process, then be forwarded to image intensifier 34.
S24: described image intensifier 34, it comprises an image border intensifier circuit; Described image border intensifier circuit strengthens the definition of image border.View data after process is first sent to described pixel self adaptation proofreading equipment 35 by described image intensifier.
S25: described pixel self adaptation proofreading equipment 35 carries out pixel and adapts to check and correction, then is sent to data logger 36.
S26: the view data after process exports by described data logger 36.
Compared to prior art, the utility model by being divided into multiple functional module in video capture processor, and difference also by each functional module independence co-ordination, can realize low-power consumption, low-light (level), and can be the picture high definition more exported.
Further by being divided into multiple functional module in picture processing chip, difference also by each functional module independence co-ordination, can realize low-power consumption, low-light (level), and can be the picture high definition more exported.Meanwhile, a white balance permanent circuit being set in this image processor further, for being fixed by this white balance parameter, without the need to operationally carrying out the adjustment of white balance, thus preventing the phenomenon of aberration interference.
The utility model is not limited to above-mentioned execution mode, if do not depart from spirit and scope of the present utility model to various change of the present utility model or distortion, if these are changed and distortion belongs within claim of the present utility model and equivalent technologies scope, then the utility model is also intended to comprise these changes and distortion.
Claims (10)
1. the video acquisition for medical endoscope, process and intensifier circuit, it is characterized in that: comprise video capture processor, picture processing chip and image enhaucament chip, the video data after collection is sent to picture processing chip and processes by described video capture processor; After described picture processing chip processes view data, then be sent to image enhaucament chip carry out enhancing process;
Described video capture processor inside comprises: controller, driver, photoreceptor, sampler and follower;
---described controller, it sends triggering signal to driver for receiving outside triggering signal;
---described driver, it for receiving the triggering signal of controller, and drives photoreceptor work;
---described photoreceptor, this light signal for receiving extraneous light signal, and is converted to the signal of telecommunication by it;
---described sampler, the signal of telecommunication processed for carrying out sampling process to the signal of telecommunication of photoreceptor, and is sent to follower by it;
---described follower, it is for being converted to digital signal by this signal of telecommunication, line output of going forward side by side picture processing chip;
Described picture processing chip comprises: data sink, master controller, image processor, data logger;
---described data sink, it is for receiving outside view data;
---described master controller, it is for receiving outside triggering signal, and the operating state of the described data sink of corresponding control, image processor and data logger;
---described image processor, it is for processing image; Described image processor comprises a white balance permanent circuit, and it, for according to the parameter preset, carries out the fixed adjustment of white balance;
---described data logger, it is for exporting the view data after process;
Described image enhaucament chip comprises: data sink, controller, static memory, image intensifier, data logger and clock generator;
---described data sink, it is for receiving viewdata signal, and is sent to this image intensifier;
---described controller, it is for receiving outer triggering signal, and the operating state of corresponding control data receiver, image enhaucament itself and data logger;
---described static memory, it is for the driving data of memory image booster, to drive the work of this image intensifier;
---described image intensifier, it comprises an image border intensifier circuit; Described image border intensifier circuit is for strengthening the definition of image border;
---described data logger, it for receiving the view data after image intensifier process, and carries out data output;
---described clock generator, it is for being image enhaucament chip clocking.
2. according to claim 1 for the video acquisition of medical endoscope, process and intensifier circuit, it is characterized in that: described video capture processor also comprises a frequency multiplier, its frequency for the triggering signal inputted outside carries out doubling process, then is sent to controller;
Described picture processing chip also comprises a frequency multiplier, and its frequency for the triggering signal inputted outside carries out doubling process, then is sent to master controller; Described image enhaucament chip also comprises a de-noising processor; The viewdata signal that described data sink receives, is sent to de-noising processor and carries out noise reduction process, then be forwarded to image intensifier.
3., according to claim 2 for the video acquisition of medical endoscope, process and intensifier circuit, it is characterized in that: the image processor in described picture processing chip also comprises an exposure gain circuit, for increasing exposure gain size;
Described image enhaucament chip also comprises a dynamic memory; View data after described de-noising processor process, is first sent to dynamic memory and stores, then be forwarded to image intensifier.
4. according to claim 3 for the video acquisition of medical endoscope, process and intensifier circuit, it is characterized in that: described image processor also comprises an optical detection circuit and flash detection circuit, its brightness for detection image and flashing state, and result of detection is sent to exposure gain circuit;
Described image enhaucament chip also comprises a vision signal multiplier and a storage signal multiplier; Described clock generator, the clock signal of generation is sent to respectively vision signal multiplier and storage signal multiplier, and by this vision signal multiplier, clock signal is sent to data sink, by this storage signal multiplier, clock signal is sent to dynamic memory and static memory.
5., according to claim 1 for the video acquisition of medical endoscope, process and intensifier circuit, it is characterized in that: described video capture processor outside is provided with: for receive supply power voltage power port, for outputting video signal video signal port, for export row field signal row field signal port, for receiving reference voltage electricity reference signal port and frequently for receiving the clock signal port of external timing signal;
Described picture processing chip outside is provided with: for receive supply power voltage power port, for receive picture signal receiver port, for outputting video signal video signal port, for export row field signal row field signal port, for receive external timing signal clock signal port, store the data receiver port and of data for receiving the PORT COM of external communication order for receiving;
Described image enhaucament chip exterior is provided with: for receive supply power voltage power port, for receive picture signal receiver port, for outputting video signal video signal port, for export row field signal row field signal port, for receiving the clock signal port of external timing signal and storing the data receiver port of data for receiving.
6. according to claim 5 for the video acquisition of medical endoscope, process and intensifier circuit, it is characterized in that: the power port of described video capture processor is circumscribed with one for the filter circuit of voltage stabilizing; Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity;
The power port of described picture processing chip is circumscribed with one for the filter circuit of voltage stabilizing; Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity;
The power port of described image enhaucament chip is circumscribed with one for the filter circuit of voltage stabilizing; Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity.
7., according to claim 5 for the video acquisition of medical endoscope, process and intensifier circuit, it is characterized in that: the row field signal port of described video capture processor is circumscribed with one for providing the resistance of signal strength signal intensity.
8. according to claim 5 for the video acquisition of medical endoscope, process and intensifier circuit, it is characterized in that: the reference signal port of described video capture processor is circumscribed with the electric capacity as voltage electricity reference data frequently.
9. according to claim 5 for the video acquisition of medical endoscope, process and intensifier circuit, it is characterized in that: the external clock circuit of clock signal port of described video capture processor, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port by a debug circuit; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock shake chip power end with to be connected and between inductance and electric capacity; Described debug circuit is made up of resistance and electric capacity; One end of the resistance of this debug circuit is connected with the output of Zhong Zhen, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock signal port is connected between this resistance and electric capacity;
The external clock circuit of described picture processing chip clock signal port, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port by a debug circuit; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock shake chip power end with to be connected and between inductance and electric capacity; Described debug circuit is made up of resistance and electric capacity; One end of the resistance of this debug circuit is connected with the output of Zhong Zhen, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock signal port is connected between this resistance and electric capacity;
The external clock circuit of clock signal port of described image enhaucament chip, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port;
Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity.
10., according to claim 5 for the video acquisition of medical endoscope, process and intensifier circuit, it is characterized in that: described picture processing chip also comprises communication command port, it is circumscribed with a mode of operation configuration circuit; Described configuration circuit is made up of two resistant series, and described communication command port is connected between two resistance.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520470700.7U CN204859318U (en) | 2015-06-30 | 2015-06-30 | A video acquisition , processing and intensifier circuit for medical endoscope |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520470700.7U CN204859318U (en) | 2015-06-30 | 2015-06-30 | A video acquisition , processing and intensifier circuit for medical endoscope |
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| CN204859318U true CN204859318U (en) | 2015-12-09 |
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| CN201520470700.7U Expired - Fee Related CN204859318U (en) | 2015-06-30 | 2015-06-30 | A video acquisition , processing and intensifier circuit for medical endoscope |
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| CN (1) | CN204859318U (en) |
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