CN204795327U - Medical endoscope's video acquisition reinforcing means - Google Patents
Medical endoscope's video acquisition reinforcing means Download PDFInfo
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- CN204795327U CN204795327U CN201520474611.XU CN201520474611U CN204795327U CN 204795327 U CN204795327 U CN 204795327U CN 201520474611 U CN201520474611 U CN 201520474611U CN 204795327 U CN204795327 U CN 204795327U
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Abstract
The utility model relates to a medical endoscope's video acquisition reinforcing means, it includes medical endoscope, optics adapter, camera and backstage host computer, be equipped with a video acquisition treatment circuit in the camera, the backstage host computer is equipped with an image enhancement circuit, the optics adapter transmits the light of endoscope conduction extremely the video acquisition treatment circuit gathers that it erupts simultaneously to handle delivers to this image enhancement circuit, video acquisition chip includes: controller, driver, photoreceptor, sampler and follower, the image enhancement chip includes: acceptor of data, central controller, image processor, data output unit. Compared with the prior art, the utility model discloses a set up video acquisition chip and image enhancement chip simultaneously, handle the image of the collection of endoscope, make image output more clear.
Description
Technical field
The utility model relates to a kind of video capture circuit, particularly a kind of video acquisition intensifier for medical endoscope.
Background technology
Endoscope is a kind of conventional medicine equipment, is become by flexible part, light source and an arrangement of mirrors head group.Through the natural hole of human body, or the minimal incision * that underwent operative is done enters in human body, during use, endoscope is imported the organ of preliminary examination, directly can spy on the change of relevant portion.
Wherein, the quality of picture quality directly affects the result of use of endoscope.Existing general use fujinon electronic video endoscope is observed.Electronic imaging element-CCD (charge coupled device) that common fujinon electronic video endoscope adopts size minimum, object in the chamber that will observe is imaged onto on CCD by small objective lens optical system, then as fibre bundle, the picture signal received is delivered on image processing system by leading, image after last output processing on a monitor, observes and diagnosis for doctor.But still there is the defect that power consumption is too high, image quality is clear not in existing CCD chip.
Meanwhile, existing general use fujinon electronic video endoscope is observed, and the treatment system image after observation being sent to outside connection carries out image procossing.But, during owing to carrying out IMAQ in human body, can due to a variety of causes of inside of human body, and cause occurring noise jamming, brightness cannot regulate or cause due to the color of light image to occur aberration automatically, so cause in the image procossing in later stage, being difficult to the image of rediscover, making doctor be difficult to identification when observing.
Utility model content
The utility model is to overcome the shortcoming of prior art with not enough, provides the video acquisition intensifier of medical endoscope of a kind of high definition, low-power consumption, low-light (level).
The utility model is achieved through the following technical solutions: a kind of video acquisition intensifier of medical endoscope, and it comprises medical endoscope, optics adapter, camera and background host computer; Be provided with a video acquisition treatment circuit in described camera, described background host computer is provided with an Image Enhancement Circuit; The light transmission that endoscope conducts by described optics adapter, to described video acquisition treatment circuit, is carried out acquisition process and is sent to this Image Enhancement Circuit;
Described optics adapter, comprises dop holder assembly, focusing ring, camera lens, protheca and nested; Described camera lens is high pass light quantity camera lens, and the leading edge of its this high pass light quantity camera lens is provided with focusing jack; The camera lens chamber suitable with high pass light quantity lens shape is provided with in described protheca, the position of its corresponding focusing jack is provided with focusing groove, and protheca is provided with protheca support lugn in the outside, front of focusing groove, described nested corresponding protheca support lugn is provided with nested support lugn, form passage of focusing between protheca support lugn with nested support lugn, this focusing passage is built-in is equipped with slip lens screw; Described focusing ring is set in protheca support lugn and nested support lugn is outside, and focusing ring is connected by the focusing jack of slip lens screw with high pass light quantity camera lens;
Described video capture circuit comprises a video capture processor, and its inside comprises: controller, driver, photoreceptor, sampler and follower;
---described controller, it sends triggering signal to driver for receiving outside triggering signal;
---described driver, it for receiving the triggering signal of controller, and drives photoreceptor work;
---described photoreceptor, this light signal for receiving extraneous light signal, and is converted to the signal of telecommunication by it;
---described sampler, the signal of telecommunication processed for carrying out sampling process to the signal of telecommunication of photoreceptor, and is sent to follower by it;
---described follower, it is for being converted to digital signal by this signal of telecommunication, line output of going forward side by side image enhaucament chip;
Described Image Enhancement Circuit comprises an image enhaucament chip, and its inside comprises: data sink, master controller, image processor, data logger;
---described data sink, it is for receiving outside view data;
---described master controller, it is for receiving outside triggering signal, and the operating state of the described data sink of corresponding control, image processor and data logger;
---described image processor, it is for processing image; Described image processor comprises a white balance permanent circuit, and it, for according to the parameter preset, carries out the fixed adjustment of white balance;
---described data logger, it is for exporting the view data after process.
Compared to prior art, the utility model by being divided into multiple functional module in video capture processor, and difference also by each functional module independence co-ordination, can realize low-power consumption, low-light (level), and can be the picture high definition more exported.
Further, the utility model by being divided into multiple functional module in control chip, and difference also by each functional module independence co-ordination, can realize the enhancing process to image.Meanwhile, an image border intensifier circuit is set in this image intensifier further, in order to strengthen the definition of image border.
Be divided into multiple functional module further by image enhaucament chip, difference also by each functional module independence co-ordination, can realize low-power consumption, low-light (level), and can be the picture high definition more exported.Meanwhile, a white balance permanent circuit being set in this image processor further, for being fixed by this white balance parameter, without the need to operationally carrying out the adjustment of white balance, thus preventing the phenomenon of aberration interference.
Further, described video capture processor also comprises a frequency multiplier, and its frequency for the triggering signal inputted outside carries out doubling process, then is sent to controller;
Described image enhaucament chip also comprises a frequency multiplier, and its frequency for the triggering signal inputted outside carries out doubling process, then is sent to master controller.
Further, the image processor in described image enhaucament chip also comprises an exposure gain circuit, for increasing exposure gain size.
Further, described image processor also comprises an optical detection circuit and flash detection circuit, its brightness for detection image and flashing state, and result of detection is sent to exposure gain circuit.
Further, described video capture processor outside is provided with: for receive supply power voltage power port, for outputting video signal video signal port, for export row field signal row field signal port, for receiving reference voltage electricity reference signal port and frequently for receiving the clock signal port of external timing signal;
Described image enhaucament chip exterior is provided with: for receive supply power voltage power port, for receive picture signal receiver port, for outputting video signal video signal port, for export row field signal row field signal port, for receive external timing signal clock signal port, store the data receiver port and of data for receiving the PORT COM of external communication order for receiving.
Further, the power port of described video capture processor is circumscribed with one for the filter circuit of voltage stabilizing; Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity;
The power port of described image enhaucament chip is circumscribed with one for the filter circuit of voltage stabilizing; Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity.
Further, the row field signal port of described video capture processor is circumscribed with one for providing the resistance of signal strength signal intensity.
Further, the reference signal port of described video capture processor is circumscribed with the electric capacity as voltage electricity frequency reference data.
Further, the external clock circuit of clock signal port of described video capture processor, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port by a debug circuit; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock shake chip power end with to be connected and between inductance and electric capacity; Described debug circuit is made up of resistance and electric capacity; One end of the resistance of this debug circuit is connected with the output of Zhong Zhen, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock signal port is connected between this resistance and electric capacity;
The external clock circuit of described image enhaucament clock signal chip port, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port by a debug circuit; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock shake chip power end with to be connected and between inductance and electric capacity; Described debug circuit is made up of resistance and electric capacity; One end of the resistance of this debug circuit is connected with the output of Zhong Zhen, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock signal port is connected between this resistance and electric capacity.
Further, described video capture processor also comprises communication command port, and it is circumscribed with a mode of operation configuration circuit; Described configuration circuit is made up of two resistant series, and described communication command port is connected between two resistance.
In order to understand better and implement, describe the utility model in detail below in conjunction with accompanying drawing.
Accompanying drawing explanation
Fig. 1 is the structural representation of video acquisition intensifier of the present utility model.
Fig. 2 is the section of structure of optics adaptive mirror of the present utility model.
Fig. 3 is video capture processor of the present utility model and image enhaucament chip connection diagram.
Fig. 4 is the internal module connection diagram of video capture processor.
Fig. 5 is the outside port connecting circuit figure of video capture processor.
Fig. 6 is the circuit diagram that the power unit of video capture processor connects.
The voltage place in circuit figure of the 2.7V of Fig. 7 video capture processor.
Fig. 8 is the voltage place in circuit figure of the 1.8V of video capture processor.
Fig. 9 is the voltage place in circuit figure of the 1.2V of video capture processor.
Figure 10 is the partial enlarged drawing of the row field signal of video capture processor.
Figure 11 is the partial enlarged drawing of the reference signal port of video capture processor.
Figure 12 is the circuit diagram of the clock circuit of video capture processor.
Figure 13 is the circuit diagram of the configuration circuit of video capture processor.
Figure 14 is the internal module connection diagram of image enhaucament chip.
Figure 15 is the outside connecting circuit figure of Part I of image enhaucament chip.
Figure 16 is the outside connecting circuit figure of Part II of image enhaucament chip.
Figure 17 is the circuit diagram of the filter circuit of pressure-stabilizing of the 3.3V voltage of image enhaucament chip.
Figure 18 is the power-switching circuit figure that the 3.3V of image enhaucament chip is converted to 1.8V.
Figure 19 is the power-switching circuit figure that the 3.3V of image enhaucament chip is converted to 1.2V.
Figure 20 is the partial enlarged drawing of the receiver port of image enhaucament chip.
Figure 21 is the partial enlarged drawing of the video signal port of image enhaucament chip.
Figure 22 is the circuit diagram of the clock circuit of image enhaucament chip.
Figure 23 is the partial enlarged drawing of the row field signal port of image enhaucament chip.
Embodiment
Refer to Fig. 1, it is the structural representation of video acquisition intensifier of the present utility model.The utility model provides a kind of video acquisition intensifier of medical endoscope, and it comprises medical endoscope 1, optics adapter 3, camera 2 and background host computer 4; Be provided with a video acquisition treatment circuit in described camera 2, described background host computer 4 is provided with an Image Enhancement Circuit; The light transmission that endoscope conducts by described optics adapter, to described video acquisition treatment circuit, is carried out acquisition process and is sent to this Image Enhancement Circuit.
Refer to Fig. 2, it is the section of structure of optics adapter of the present utility model.Described optics adapter 3, comprise dop holder assembly 31, focusing ring 32, camera lens, protheca 34, nested 35, slip lens screw 36, front seal glass 37 and rear seal glass 38, concrete structure is as follows:
Described camera lens is high pass light quantity camera lens 33, and the leading edge of its this high pass light quantity camera lens 33 is provided with focusing jack 331, and described high pass light quantity camera lens 33 is existing industrial high pass light quantity camera lens, and it specifically can adopt Japanese CBCComputarFALENS industrial lens HF series.
Described protheca 34 is connected with dop holder assembly 31, is provided with the camera lens chamber 343 suitable with high pass light quantity camera lens 33 shape in this protheca 34.Further, the position of protheca 34 correspondence focusing jack 331 is provided with focusing groove 342, and it is provided with protheca support lugn 341 in the outside, front of focusing groove 342.Described nested 35 are set in protheca 34 outside, and its corresponding protheca support lugn 341 is provided with nested support lugn 351, forms passage 30 of focusing between protheca support lugn 341 with nested support lugn 351, and this focusing passage is built-in is equipped with slip lens screw 36; Described focusing ring 32 is set in protheca support lugn 341 and nested support lugn 351 is outside, and focusing ring 32 is connected by the focusing jack 331 of slip lens screw 36 with high pass light quantity camera lens 33.The utility model adopts focusing ring 32 directly to realize by slip lens screw 36 pairs of high pass light quantity camera lenses locking of focusing, and focusing precisely flexibly, prevents existing traditional focusing mode from easily skidding and instability.
Further, in order to the embedded sealing realizing high pass light quantity camera lens 33 is installed, the utility model by the following technical solutions:
Described focusing ring 32 is provided with between protheca support lugn 341 and nested support lugn 351 sealing ring 391 that focuses.
Be provided with front seal glass 37 between described protheca and dop holder assembly, and be provided with front sealing ring 392 between this front seal glass 37 and dop holder assembly 31; The front portion of described protheca 34 is provided with for supporting Sealing shield ring 344 before front seal glass 27.
Described protheca 34 rear portion is provided with rear seal glass 38 with between rear portion in nested 35, and is provided with rear sealing ring 393 between this rear seal glass 38 with rear portion in nested 35; The rear portion of described protheca 34 is provided with the rear Sealing shield ring 345 for supporting rear seal glass.
The utility model is by passing through structural improvement, increase focusing ring sealing ring 391, front seal glass 37, front sealing ring 392, rear seal glass 38 and rear sealing ring 393, realize optics adapter to install the embedded sealing of high pass light quantity camera lens 33, effectively prevent camera lens from entering dust or water inlet is hazed.
Refer to Fig. 3, it is video capture processor of the present utility model and image enhaucament chip connection diagram.Video data after collection is sent to image enhaucament chip 20 and processes by described video capture processor 10.
Refer to Fig. 4, it is the internal module connection diagram of video capture processor.Described video capture processor 10 inside comprises: controller 11, driver 12, photoreceptor 13, sampler 14, follower 15 and frequency multiplier 16;
Described controller 11, it sends triggering signal to driver for receiving outside triggering signal;
Described driver 12, it for receiving the triggering signal of controller, and drives photoreceptor work;
Described photoreceptor 13, this light signal for receiving extraneous light signal, and is converted to the signal of telecommunication by it;
Described sampler 14, the signal of telecommunication processed for carrying out sampling process to the signal of telecommunication of photoreceptor, and is sent to follower by it;
Described follower 15, it is for being converted to digital signal by this signal of telecommunication, line output of going forward side by side.
Described frequency multiplier 16, its frequency for the triggering signal inputted outside carries out doubling process, then is sent to controller.Further, conveniently in the requirement of the frequency of utilization of video capture processor, the adjustment being realized frequency by frequency multiplier is amplified.
Please refer to Fig. 5, it is the outside port circuit diagram of video capture processor.In addition in order to adapt to the application of this video capture processor, be provided with in described video capture processor outside: the power port 101 for receiver voltage, the video signal port 102 for outputting video signal, for export row field signal row field signal port one 03, for receiving reference voltage electricity reference signal port one 04 frequently, for receiving the clock signal port 105 of external timing signal and the communication command port one 06 for receiving operate outside mode command.
Please refer to Fig. 6, it is the circuit diagram of the power unit of video capture processor.Concrete, the power unit in video capture processor adopts three kinds of voltages simultaneously, is respectively 2.7V, 1.8V, and 1.2V.
Please refer to Fig. 7-9, it is respectively the circuit diagram of 2.7V, 1.8V and 1.2V of video capture processor.Concrete, the input port 101 of three kinds of voltages of video capture processor is all circumscribed with one for the filter circuit of voltage stabilizing; Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity.Wherein, the voltage place in circuit of 2.7V and 1.8V comprises four electric capacity, and the voltage place in circuit of 1.2V comprises three electric capacity, to filter the interference signal of different frequency.
Refer to Figure 10, it is the interface enlarged drawing of row field signal.Further, described row field signal port one 03 is circumscribed with one for providing the resistance of signal strength signal intensity.By this row field signal, for controlling frequency and the order of video frequency output.Such as: the display frequency of vision signal on screen and DISPLAY ORDER can be controlled, can be from every line output under upper, also can be export from left to right.
Refer to Figure 11, it is the partial enlarged drawing of the reference signal port of video capture processor.Further, described reference signal port one 04 is circumscribed with the electric capacity as voltage electricity frequency reference data.In the present embodiment, described reference signal port has 7, the electric capacity of the external 1uF of each port.
Refer to Figure 12, it is the circuit diagram of the clock circuit of video capture processor.The external clock circuit of described clock signal port 105, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port by a debug circuit; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock shake chip power end with to be connected and between inductance and electric capacity; Described debug circuit is made up of resistance and electric capacity; One end of the resistance of this debug circuit is connected with the output of Zhong Zhen, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock signal port is connected between this resistance and electric capacity.
Refer to Figure 13, it is the circuit diagram of the configuration circuit of video capture processor.Further, described communication command port one 06, it is circumscribed with a mode of operation configuration circuit; Described configuration circuit is made up of two resistant series, and described communication command port is connected between two resistance.
Refer to Figure 14, it is the internal module connection diagram of image enhaucament chip.Described image enhaucament chip comprises: data sink 21, de-noising processor 2, dynamic memory 23, image intensifier 24, pixel self adaptation proofreading equipment 25, data logger 26, static memory 27, controller 28, vision signal multiplier 29, storage signal multiplier 210, clock generator 211.
Described data sink 21, it is for receiving viewdata signal, and is sent to de-noising processor 22;
The viewdata signal that described data sink 21 receives, is sent to de-noising processor 22 and carries out noise reduction process, then be forwarded to dynamic memory 23.
After the view data of described dynamic memory 23 after receiving de-noising processor 22 process, then be forwarded to image intensifier 24.
Described image intensifier 24, it comprises an image border intensifier circuit; Described image border intensifier circuit is for strengthening the definition of image border.Further, the view data after process is first sent to described pixel self adaptation proofreading equipment 5 by described image intensifier, carries out pixel and adapts to check and correction, then be sent to data logger 26 by this pixel self adaptation proofreading equipment 25.
Described data logger 26, it for receiving the view data after image intensifier process, and carries out data output;
Described static memory 27, it is for the driving data of memory image booster, to drive the work of this image intensifier;
Described controller 28, it is for receiving outer triggering signal, and the operating state of corresponding control data receiver, image enhaucament itself and data logger;
Described clock generator 211, it is for being image enhaucament chip clocking.Further, described clock generator, the clock signal of generation is sent to respectively vision signal multiplier 29 and storage signal multiplier 210, and by this vision signal multiplier 29, clock signal is sent to data sink, by this storage signal multiplier 210, clock signal is sent to dynamic memory and static memory.
Please refer to Figure 15 and Figure 16, it is respectively the outside connecting circuit figure of image enhaucament chip.
Further, described image enhaucament chip exterior is provided with: for receive supply power voltage power port, for receive picture signal receiver port 201, for outputting video signal video signal port 202, for receive external timing signal clock signal port 203, for exporting the row field signal port 204 of row field signal.
Concrete, in the present embodiment, the external voltage of described power port comprises 3.3V, 1.8V and 1.2V tri-kinds of voltages.Refer to Figure 17, it is the circuit diagram of the filter circuit of pressure-stabilizing of 3.3V voltage.Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity.
Refer to Figure 18-19, it is respectively the change-over circuit figure that power-switching circuit figure and 3.3V that 3.3V is converted to 1.8V is converted to 1.2V.In the present embodiment, by a power-switching circuit, the voltage of 3.3V is converted to respectively the voltage of 1.8V and 1.2V.Concrete, described power-switching circuit comprises a power conversion chip; The voltage of the input access 3.3V of described power conversion chip, output exports the voltage of 1.8V and 1.2V respectively, to power to image enhaucament chip.
Refer to Figure 20, it is the partial enlarged drawing of the receiver port of image enhaucament chip.Described receiver port 201 comprises 20 signal pins, is connected with the data sink 1 of inside, for receiving the picture signal of input.
Refer to Figure 21, it is the partial enlarged drawing of the video signal port of image enhaucament chip.Described video signal port 202 comprises 20 signal pins, and it is connected, for output image signal with inner data logger 6.
Refer to Figure 22, it is the circuit diagram of the clock circuit of image enhaucament chip.Further, the external clock circuit of described clock signal port 203, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity.
Refer to Figure 23, it is the partial enlarged drawing of the row field signal port of image enhaucament chip.Described row field signal port 204 comprises a row signal pins and a field signal pin.Described row field signal port one 04 is for controlling frequency and the order of video frequency output.Such as: the display frequency of vision signal on screen and DISPLAY ORDER can be controlled, can be from every line output under upper, also can be export from left to right.
Below the course of work of video acquisition treatment circuit of the present utility model is described:
S11: carry out circuit access according to above-mentioned requirement by the outside port of this video capture processor and image enhaucament chip;
S12: when video capture processor is energized, first carries out multiplication by this frequency multiplier by input voltage frequency and regulates, to adapt to current operating frequency;
S13: described controller 11 sends triggering signal to driver 12, drives photoreceptor 13 to work by driver 12;
S14: when light is irradiated on photoreceptor 13, is converted to the signal of telecommunication by this photoreceptor 13 by light signal, and transfers to sampler 14;
S15: when sampler 14 receives the signal of telecommunication from photoreceptor 13, carries out sampling process to this signal of telecommunication, and the signal of telecommunication processed is sent to follower 15;
S16: finally by described follower 15, this signal of telecommunication is converted to digital signal, line output of going forward side by side is to image enhaucament chip.
S17: described data sink 21 receives outside view data;
S8: described image processor 23 pairs of images process.Specifically respectively by described Lens Shading Compensation circuit 231, the shade that camera lens produces is compensated process; By brightness and the flashing state of described optical detection circuit 232 and flash detection circuit 233 detection image, and result of detection is sent to exposure gain circuit; Then exposure gain size is increased by described exposure gain circuit 234.Last again by described white balance permanent circuit 35 according to default parameter, carry out the fixed adjustment of white balance.
S19: the view data after process exports by described data logger 24.
Compared to prior art, the utility model by being divided into multiple functional module in video capture processor, and difference also by each functional module independence co-ordination, can realize low-power consumption, low-light (level), and can be the picture high definition more exported.
Be divided into multiple functional module further by image enhaucament chip, difference also by each functional module independence co-ordination, can realize low-power consumption, low-light (level), and can be the picture high definition more exported.Meanwhile, a white balance permanent circuit being set in this image processor further, for being fixed by this white balance parameter, without the need to operationally carrying out the adjustment of white balance, thus preventing the phenomenon of aberration interference.
The utility model is not limited to above-mentioned execution mode, if do not depart from spirit and scope of the present utility model to various change of the present utility model or distortion, if these are changed and distortion belongs within claim of the present utility model and equivalent technologies scope, then the utility model is also intended to comprise these changes and distortion.
Claims (10)
1. a video acquisition intensifier for medical endoscope, is characterized in that: comprise medical endoscope, optics adapter, camera and background host computer; Be provided with a video acquisition treatment circuit in described camera, described background host computer is provided with an Image Enhancement Circuit; The light transmission that endoscope conducts by described optics adapter, to described video acquisition treatment circuit, is carried out acquisition process and is sent to this Image Enhancement Circuit;
Described optics adapter, comprises dop holder assembly, focusing ring, camera lens, protheca and nested; Described camera lens is high pass light quantity camera lens, and the leading edge of its this high pass light quantity camera lens is provided with focusing jack; The camera lens chamber suitable with high pass light quantity lens shape is provided with in described protheca, the position of its corresponding focusing jack is provided with focusing groove, and protheca is provided with protheca support lugn in the outside, front of focusing groove, described nested corresponding protheca support lugn is provided with nested support lugn, form passage of focusing between protheca support lugn with nested support lugn, this focusing passage is built-in is equipped with slip lens screw; Described focusing ring is set in protheca support lugn and nested support lugn is outside, and focusing ring is connected by the focusing jack of slip lens screw with high pass light quantity camera lens;
Described video capture circuit comprises a video capture processor, and its inside comprises: controller, driver, photoreceptor, sampler and follower;
---described controller, it sends triggering signal to driver for receiving outside triggering signal;
---described driver, it for receiving the triggering signal of controller, and drives photoreceptor work;
---described photoreceptor, this light signal for receiving extraneous light signal, and is converted to the signal of telecommunication by it;
---described sampler, the signal of telecommunication processed for carrying out sampling process to the signal of telecommunication of photoreceptor, and is sent to follower by it;
---described follower, it is for being converted to digital signal by this signal of telecommunication, line output of going forward side by side image enhaucament chip; Described Image Enhancement Circuit comprises an image enhaucament chip, and its inside comprises: data sink, controller, static memory, image intensifier, data logger and clock generator;
---described data sink, it is for receiving viewdata signal, and is sent to this image intensifier;
---described controller, it is for receiving outer triggering signal, and the operating state of corresponding control data receiver, image enhaucament itself and data logger;
---described static memory, it is for the driving data of memory image booster, to drive the work of this image intensifier;
---described image intensifier, it comprises an image border intensifier circuit; Described image border intensifier circuit is for strengthening the definition of image border;
---described data logger, it for receiving the view data after image intensifier process, and carries out data output;
---described clock generator, it is for being image enhaucament chip clocking.
2. the video acquisition intensifier of medical endoscope according to claim 1, it is characterized in that: described video capture processor also comprises a frequency multiplier, its frequency for the triggering signal inputted outside carries out doubling process, then is sent to controller; Described image enhaucament chip also comprises a de-noising processor; The viewdata signal that described data sink receives, is sent to de-noising processor and carries out noise reduction process, then be forwarded to image intensifier.
3. the video acquisition intensifier of medical endoscope according to claim 1, is characterized in that: described image enhaucament chip also comprises a dynamic memory; View data after described de-noising processor process, is first sent to dynamic memory and stores, then be forwarded to image intensifier.
4. the video acquisition intensifier of medical endoscope according to claim 3, is characterized in that: described image enhaucament chip also comprises a pixel self adaptation proofreading equipment; View data after process is first sent to described pixel self adaptation proofreading equipment by described image intensifier, carries out pixel and adapts to check and correction, then be sent to data logger by this pixel self adaptation proofreading equipment.
5. the video acquisition intensifier of medical endoscope according to claim 3, is characterized in that: described image enhaucament chip also comprises a vision signal multiplier and a storage signal multiplier; Described clock generator, the clock signal of generation is sent to respectively vision signal multiplier and storage signal multiplier, and by this vision signal multiplier, clock signal is sent to data sink, by this storage signal multiplier, clock signal is sent to dynamic memory and static memory.
6. the video acquisition intensifier of medical endoscope according to claim 1, is characterized in that: described video capture processor outside is provided with: for receive supply power voltage power port, for outputting video signal video signal port, for export row field signal row field signal port, for receiving reference voltage electricity reference signal port and frequently for receiving the clock signal port of external timing signal;
Described image enhaucament chip exterior is provided with: for receive supply power voltage power port, for receive picture signal receiver port, for outputting video signal video signal port, for export row field signal row field signal port, for receiving the clock signal port of external timing signal and storing the data receiver port of data for receiving.
7. the video acquisition intensifier of medical endoscope according to claim 6, is characterized in that: the power port of described video capture processor is circumscribed with one for the filter circuit of voltage stabilizing; Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity;
The power port of described image enhaucament chip is circumscribed with one for the filter circuit of voltage stabilizing; Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity.
8. the video acquisition intensifier of medical endoscope according to claim 6, is characterized in that: the reference signal port of described video capture processor is circumscribed with the electric capacity as voltage electricity reference data frequently.
9. the video acquisition intensifier of medical endoscope according to claim 6, is characterized in that: the external clock circuit of clock signal port of described video capture processor, and it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port by a debug circuit; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock shake chip power end with to be connected and between inductance and electric capacity; Described debug circuit is made up of resistance and electric capacity; One end of the resistance of this debug circuit is connected with the output of Zhong Zhen, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock signal port is connected between this resistance and electric capacity;
The external clock circuit of described image enhaucament clock signal chip port, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity.
10. the video acquisition intensifier of medical endoscope according to claim 6, it is characterized in that: described video capture processor also comprises communication command port, it is circumscribed with a mode of operation configuration circuit; Described configuration circuit is made up of two resistant series, and described communication command port is connected between two resistance.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201520474611.XU CN204795327U (en) | 2015-06-30 | 2015-06-30 | Medical endoscope's video acquisition reinforcing means |
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|---|---|---|---|
| CN201520474611.XU CN204795327U (en) | 2015-06-30 | 2015-06-30 | Medical endoscope's video acquisition reinforcing means |
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