CN104853133A - Method and system for converting LVDS video signals into 8Lane V-BY-ONE video signals - Google Patents
Method and system for converting LVDS video signals into 8Lane V-BY-ONE video signals Download PDFInfo
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Abstract
The invention relates to a method and system for converting LVDS video signals into 8Lane V-BY-ONE video signals. The method comprises receiving and demodulating the LVDS video signals transmitted through a double-Link mode, and generating LVDS parallel demodulation data and LVDS pixel clock; according to the LVDS video signals, decoding control signals, performing video decoding on the LVDS parallel demodulation data, and generating LVDS video source data and LVDS video source synchronization signals; according to LVDS video conversion control signals, converting the LVDS video source data and the LVDS video source synchronization signals into RGB video signals; and after a V-BY-ONE video conversion starting command is received, converting the RGB video signals into the 8Lane V-BY-ONE video signals. The method and system provided by the invention can detect the quality of the LVDS video signals and the correctness of image data and have the advantages of high reliability, zero misjudgement, simple operation, high detection efficiency and low cost.
Description
Technical field
The present invention relates to the generation of V-BY-ONE vision signal, referring to a kind of method and system for LVDS vision signal being converted to V-BY-ONE vision signal particularly, belonging to display and the field tests of liquid crystal module.
Background technology
Liquid crystal display module (Liquid Crystal Display Module, hereinafter referred to as liquid crystal module) is the critical component that liquid crystal display can normally show, and it is made up of liquid crystal display screen, backlight original paper, Graphics Processing chip and circuit.Liquid crystal display module structure is accurate, processing procedure is complicated, manufacturing technique requirent is high, in order to guarantee yields when producing, need to produce various test video signal by special liquid crystal module testing apparatus to be input in liquid crystal module and to show, thus strictly, comprehensively detect its display effect.At present, its display interface of common liquid crystals module on TV, display product and inner Graphics Processing circuit use LVDS (Low-Voltage Differential Signaling, Low Voltage Differential Signal) signal carrys out work, and existing liquid crystal module testing device also corresponding output be that LVDS vision signal is to realize the test of module, because common liquid crystals module production time is of a specified duration, output large, therefore its module testing apparatus also uses in a large number.
But, significantly increase along with people constantly pursue more high definition, display effect more true to nature and biography bandwidth requirements on liquid crystal display module, be used for the increase in number materially of the LVDS circuit of supporting these frequency ranges, cause TV manufacturer to undertake more production costs and complexity, therefore common liquid crystals module cannot meet the need gradually.So market occurs a kind of novel liquid crystal module with ultrahigh resolution and very-high solution density is meeting the demand of people, this liquid crystal module adopts V-BY-ONE signaling interface, there is better transmission speed, better transmission range, better EMI is compatible, and better price advantage, the liquid crystal module therefore with V-BY-ONE interface becomes development trend.
But the testing apparatus of V-BY-ONE liquid crystal module needs to export same V-BY-ONE test signal, but existing common liquid crystals module testing apparatus does not have this function, and common liquid crystals module also continue production, its testing apparatus do not enter yet the replacement cycle will continue use.Although module manufacturer also produces V-BY-ONE liquid crystal module, in order to protect investment, reduce production cost, existing equipment can not be eliminated, again make a big purchase expensive V-BY-ONE module Special testing device in large quantities.In order to can within short-term low cost production in enormous quantities V-BY-ONE liquid crystal module and ensure its yields, just still reuse existing common module testing apparatus on a large scale.
Therefore, need to study a kind of conversion equipment and LVDS vision signal can be converted to V-BY-ONE vision signal, common liquid crystals module testing apparatus can be tested V-BY-ONE module by this conversion equipment, and this conversion equipment is not only wanted dependable performance, integrated efficient but also is wanted low price, easy and simple to handle simultaneously.
Summary of the invention
The object of the invention is overcome above-mentioned the deficiencies in the prior art and provide a kind of LVDS vision signal to be converted to the method and system of 8Lane V-BY-ONE vision signal, the present invention can to LVDS video signal quality, view data correctness detects, have reliability high, without erroneous judgement, feature simple to operate, detection efficiency is high, cost is low.
The technical scheme realizing the object of the invention employing is: a kind of LVDS vision signal is converted to the method being applicable to 8LaneV-BY-ONE vision signal, and the method comprises:
LVDS vision signal is converted to rgb video signal;
Configuration and the conversion that starting command controls to carry out V-BY-ONE conversion is changed according to the order of V-BY-ONE conversion configurations and V-BY-ONE.
In addition, the present invention also provides a kind of LVDS vision signal to be converted to the system being applicable to 8LaneV-BY-ONE vision signal, and this system comprises:
LVDS vision signal converting unit, for being converted to rgb video signal by LVDS vision signal;
V-BY-ONE vision signal converting unit, for changing according to the order of V-BY-ONE conversion configurations and V-BY-ONE configuration and the conversion that starting command controls to carry out V-BY-ONE conversion.
The present invention has the following advantages:
(1) the present invention can detect the V-BY-ONE vision signal of the 8Lane that video source produces, the present invention, by arranging, well can be adapted to the different qualities such as color range, transmission means, coded system of different V-BY-ONE transmission characteristics, vision signal.
(2) the present invention can detect the electrical characteristic of the V-BY-ONE vision signal that video source produces, and by input V-BY-ONE electric parameter standard, obtains testing result and output display in the present invention through comparison.
(3) the present invention can detect the view data of the V-BY-ONE vision signal that video source produces, by the every frame image data of buffer memory in advance and and raw video image contrast, thus judge whether each pixel exports correctly, and every two field picture all can detect.
(4) the present invention can detect the highest V-BY-ONE video resolution, not only integrated level is high, reliable operation, antijamming capability are strong, and it is simple to operate, economical and practical, detecting reliability and the efficiency of V-BY-ONE liquid crystal module can not only be promoted, reduce its equipment cost and production cost, also will improve the universal of related display device further.
(5) the present invention is by realizing described repertoire with FPGA (field programmable logic array) chip, DDR (DoubleDate Rate double data rate) storage chip, A/D (analog/digital) conversion chip; Above-mentioned device is all the common chips in market, they not only working stability, realize easily, and low price, avoid the problem such as design complexity, poor stability, design cost height caused because using various special chip.
Accompanying drawing explanation
Fig. 1 is that LVDS vision signal of the present invention is converted to the apparatus structure block diagram being applicable to 8LaneV-BY-ONE vision signal.
Fig. 2 is the circuit block diagram of LVDS video reception unit and LVDS video signal decoding unit in Fig. 1;
Fig. 3 is the circuit block diagram of rgb video signal converting unit in Fig. 1, V-BY-ONE vision signal converting unit and Video Quality Metric dispensing unit;
Fig. 4 is the method flow diagram that LVDS vision signal of the present invention is converted to V-BY-ONE vision signal.
Fig. 5 is 8lane not split screen LVDS vision signal schematic diagram;
Fig. 6 is 8lane2 split screen LVDS vision signal schematic diagram, and wherein, Fig. 6-1 is the upper and lower 2 split screen LVDS vision signal schematic diagrames of 8lane, and Fig. 6-2 is about 8lane 2 split screen LVDS vision signal schematic diagram;
Fig. 7 is 8lane4 split screen LVDS vision signal schematic diagram, and wherein, Fig. 7-1 is the upper and lower 4 split screen LVDS vision signal schematic diagrames of 8lane, and Fig. 7-2 is about 8lane 4 split screen LVDS vision signal schematic diagram;
In figure: 1.LVDS video reception unit, 1-1.LVDS video signal interface, 1-2.LVDS video reception termination module, the LVDS clock signal demodulation module of the two LINK of 1-3., the LVDS demodulated data signal module of the two LINK of 1-4., 1-5.LVDS demodulation dynamic calibration module;
2.LVDS video signal decoding unit, 2-1.LVDS audio video synchronization buffer module, the LVDS video signal cable sequence control module of the two LINK of 2-2., 2-3.LVDS video synchronization signal decoder module, the LVDS video data decoding module of the two LINK of 2-4.;
3.RGB vision signal converting unit, 3-1.RGB video signal self-adaptive control module, 3-2.RGB video clock adaptive configuration module, 3-3RGB. video clock generation module, 3-4.RGB video clock exports adjusting module, 3-5. dual link pattern rgb video modular converter, about 3-6. span mode rgb video modular converter, 3-7. odd even span mode rgb video modular converter, 3-8.RGB vision signal output module;
4.V-BY-ONE vision signal converting unit, 4-1.V-BY-ONE register module, 4-2. left 8LANE V-BY-ONE vision signal modular converter, 4-3. right wing 8LANE V-BY-ONE vision signal modular converter, 4-4.V-BY-ONE shows module connector;
5. Video Quality Metric dispensing unit, the manual toggle switch of 5-1., 5-2.JTAG interface, 5-3.V-BY-ONE Video Quality Metric configuration module.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
As shown in Figures 1 to 3, LVDS vision signal of the present invention is converted to the system being applicable to 8LaneV-BY-ONE vision signal and comprises LVDS vision signal converting unit, V-BY-ONE vision signal converting unit 4 and Video Quality Metric dispensing unit 5 for LVDS vision signal being converted to rgb video signal.Wherein, LVDS vision signal converting unit comprises LVDS video reception unit 1, LVDS video signal decoding unit 2 and rgb video signal converting unit 3.
The invention described above LVDS vision signal is converted to the course of work of the system being applicable to 8LaneV-BY-ONE vision signal as shown in Figure 4, comprises following concrete steps:
S100, LVDS video reception unit 1 receives LVDS vision signal, produces LVDS parallel demodulation data and LVDS pixel clock to the LVDS vision signal demodulation received.The present embodiment LVDS video reception unit 1 comprises: LVDS video signal interface 1-1, LVDS video reception termination module 1-2, LVDS clock signal demodulation module 1-3, LVDS demodulated data signal module 1-4 and LVDS demodulation dynamic calibration module 1-5, wherein, LVDS video reception termination module 1-2 is connected with LVDS video signal interface 1-1, LVDS clock signal demodulation module 1-3 is connected with LVDS video reception termination module 1-2 respectively with LVDS demodulated data signal module 1-4, LVDS demodulation dynamic calibration module 1-5 is connected with LVDS clock signal demodulation module 1-3 and LVDS demodulated data signal module 1-4 respectively.To being described in detail as follows of each module:
LVDS video signal interface 1-1 receives LVDS vision signal, and LVDS vision signal comprises the LVDS vision signal of single LINK, two LINK, four LINK, and the LVDS vision signal of single LINK and LINK1 transmit all video pixels; The LVDS vision signal of two LINK comprises LINK1, LINK2 bis-links, transmits odd even video pixel respectively; The LVDS vision signal of four LINK comprises four links, according to transmitting successively at LINK1, LINK2, LINK3, LINK4 of video pixel order.V-BY-ONE vision signal of the present invention comprise 8Lane2 split screen type, 8Lane not split screen type, 8Lane 4 split screen type V-BY-ONE show module, when the V-BY-ONE vision signal that will change exports to the V-BY-ONE liquid crystal display module of 8Lane 4 split screen type, 8Lane 2 split screen type, 8Lane not split screen type, LVDS vision signal is only transmitted in two LINK mode.The LVDS vision signal of each link comprises LVDS receive clock and LVDS data, and LVDS data are by LVDS data bus transmission, and LVDS data/address bus comprises some root holding wires, and every root holding wire transmits serial code signal.LVDS video signal interface 1-1 inputs LVDS vision signal by connecting LVDS transmission line interface, interface comprises two kinds of input pads: industrial standard ox horn seat connector and Miniature high-density business connector, to guarantee that the present invention all can be suitable in industrial environment and business environment, when some connectors have LVDS signal to input, interface can export from this connector automatically, when two connectors have signal to input, interface acquiescence exports from Miniature high-density business connector.
LVDS video reception termination module 1-2 to be terminated operation to the LVDS vision signal that LVDS video signal interface 1-1 receives, and then sends LVDS receive clock and LVDS data to LVDS clock signal demodulation module 1-3 and LVDS signal receiving module 1-4 respectively.Terminated operation comprises: LVDS terminating resistor coupling, LVDS signal level coupling, LVDS signal equalization with postemphasis, signal cushion with reconstruction, compensate because of signal distortion that long range propagation causes, decay, reduce transmission disturbance, guarantee received LVDS signal quality.The process of termination comprises: before receiving LVDS signal, carry out ESD (Electro Static Discharge static discharge) protective treatment to eliminate the strong discharge impact interference of moment, then carry out common-mode noise filtering process to suppress line noise, to improve anti-electromagnetic interference capability.The distortion caused is transmitted in the impedance matching process that is terminated when a signal is received with erasure signal, also the additional interference of further erasure signal, carries out equilibrium and process of postemphasising to signal, to eliminate the signal attenuation because loss causes simultaneously.Afterwards again to signal Hyblid Buffer Amplifier, and reconstruct high-quality LVDS vision signal through the judgement of reference level.
The LVDS receive clock of LVDS clock signal demodulation module 1-3 to each LINK received carries out demodulation, produces demodulation clock and demodulation enable signal; Demodulating process comprises: LVDS receive clock is input to PLL (Phase Locked Loop phase-locked loop) by its frequency multiplication to LVDS frequency data signal through High-speed I/O buffering, and carry out high-frequency clock conversion process, produce the LVDS demodulation clock with LVDS data same frequency, with LVDS receive clock with LVDS pixel clock frequently and LVDS demodulation gating signal, and output in high-frequency clock network, make them have very low delay and jitter, very strong driving force, guarantee reliable and stable to carry out demodulation to LVDS data.When carrying out frequency multiplication operation with PLL to LVDS receive clock, clock jitter removing from LVDS demodulation dynamic calibration module 1-5 moves calibrating signal and also sends into PLL to shake control to this operating process is counter simultaneously, make it produce not affect by input jiffer, stable frequency-doubled signal, guarantee that demodulation operation can not made mistakes without interruption.
LVDS demodulated data signal module 1-4 becomes parallel data by the demodulation clock of each LINK with the LVDS data demodulates of demodulation enable signal to this LINK, and LVDS receive clock is demodulated into LVDS pixel clock simultaneously.Its process comprises: to each data demodulation independently in LVDS serial data bus.Each LVDS data-signal is first buffered in the high speed signal network of low delay, low jitter, postponed half data bit bit period again, make LVDS demodulation clock correct can sample this data value at the center of each LVDS data bit, and according to demodulation gating signal, it is periodically blocked bunchiness data, do string with LVDS video source pixel clock again turn and process the parallel demodulation data obtaining this LVDS signal, by trigger Buffer output to guarantee signal stabilization, reliably.The demodulation that each LVDS holding wire is all run simultaneously, makes each holding wire how all can not mutually disturb regardless of data and causes demodulation mistake.
When the bit value by LVDS demodulation clock sampling LVDS data, data dithering removal calibrating signal from LVDS demodulation dynamic calibration module 1-5 simultaneously also shakes control to this operating process is counter, makes it produce not affect by input jiffer, reliable and stable demodulating data.
All the time the LVDS data flow phase alignment signal controlling of LVDS demodulation dynamic calibration module 1-5 is subject in the phase delay process of data input, when phase place when between demodulation clock and LVDS data has a deviation, phase alignment signal makes its delay contrary with phase deviation adjustment on data delay half period basis, data center is alignd along maintenance with the sampling of demodulation clock all the time, guarantees correctly to sample data.
While demodulation gating signal carries out blocking serial data, the bit being also subject to the demodulation byte-aligned of LVDS demodulation dynamic calibration module 1-5 moves calibrating signal and controls, and makes it the start bit of the parallel data of segmentation move on next serial data position.
LVDS demodulation dynamic calibration module 1-5 carries out dynamic calibration in real time to the string signal of LVDS receive clock and LVDS data respectively respectively in demodulating process.
S200, LVDS video signal decoding unit 2, according to LVDS video decode control signal, carries out video decode to LVDS parallel demodulation data, produces LVDS video source data and LVDS video source synchronizing signal.The present embodiment LVDS video signal decoding unit 2 comprises: LVDS audio video synchronization buffer module 2-1, LVDS vision signal order module 2-2, LVDS video synchronization signal decoder module 2-3 and LVDS video data decoding module 2-4, to being described in detail as follows of each module:
The LVDS pixel clock of LINK1 is become LVDS video source pixel clock by global clock path integration by LVDS audio video synchronization buffer module 2-1, with the LVDS pixel clock of each LINK inputted, respective LVDS parallel demodulation data are write DC-FIFO (First Input FirstOutput respectively simultaneously, First Input First Output) in after buffer memory, read one by one with LVDS video source pixel clock, make it to become synchrodata, avoid postponing inconsistent caused read error between signal in the transmission.The buffer memory degree of depth is large as far as possible, has abundant data to be buffered offset maximum delay between them to make all LINK.
The data of LINK1 and LINK2 in two links exchange when receiving LVDS odd even pixel reverse control signal by LVDS vision signal order module 2-2.
LVDS video synchronization signal decoder module 2-3, according to the LVDS parallel demodulation decoding data of the LVDS video decode control signal received from Video Quality Metric dispensing unit 5 to the synchronous each LINK read, decodes LVDS video source synchronizing signal; Carry out decoding to the LINK1 LVDS video source pixel clock after sequence with sequential logic mode of operation according to VESA and the JEIDA transfer encoding standard in LVDS video decode control signal recover LVDS video source synchronizing signal and export, synchronizing signal comprises: video level line synchronizing signal (Hsync), video vertical field sync signal (Vsync), video data useful signal (DE).
LVDS video data decoding module 2-4, according to the LVDS parallel demodulation decoding data of the LVDS video decode control signal received from Video Quality Metric dispensing unit 5 to the synchronous each LINK read, decodes the LVDS video source data signal of each LINK.
LVDS video source data and LVDS video source synchronizing signal, according to LVDS Video Quality Metric control signal, are converted to rgb video signal by S300, rgb video signal converting unit 3; V-BY-ONE Video Quality Metric enabling signal is sent to Video Quality Metric dispensing unit 5 after converting.The present embodiment rgb video signal converting unit 3 comprises: rgb video signal self-adaptive control module 3-1, rgb video clock adaptive configuration module 3-2, rgb video clock generating module 3-3, rgb video clock export adjusting module 3-4, dual link pattern rgb video modular converter 3-5, left and right span mode rgb video modular converter 3-6, odd even span mode rgb video modular converter 3-7 and rgb video signal output module 3-8, to being described in detail as follows of each module:
Rgb video signal self-adaptive control module 3-1 produces the rgb video clock configuration signal of the two LINK patterns matched according to LVDS Video Quality Metric control signal, send rgb video clock adaptive configuration module 3-2 to together with LVDS video source pixel clock; Produce RGB modulus of conversion block selection signal according to LVDS Video Quality Metric control signal and send dual link pattern rgb video modular converter 3-5, left and right span mode rgb video modular converter 3-6, odd even span mode rgb video modular converter 3-7 together with the LVDS video source data signal of each LINK, LVDS video source synchronizing signal to together with rgb video clock, detect LVDS video synchronization signal calculated level resolution value, horizontal resolution value is sent to dual link pattern rgb video modular converter 3-5.
Rgb video clock adaptive configuration module 3-2 is according to the rgb video clock configuration signal of produced two LINK patterns, configuration parameter and the configuration enable signal of corresponding two LINK pattern is produced by local clock pulses, dynamic recognition operation is carried out to clock generating module, rgb video clock generating module 3-3 is made automatically to produce required rgb video clock signal, when being configured to two LINK pattern, LVDS video source pixel clock is converted into the rgb video pixel clock (hereinafter referred to as RGB clock) of its two frequency multiplication.
Rgb video clock generating module 3-3 produces rgb video clock according to configurable clock generator and enable signal and sends rgb video signal self-adaptive control module 3-1 and rgb video clock output adjusting module 3-4 to.PLL configuration parameter is carried out reconfiguration operation according to ordered pair PLL during its dynamic recognition, LVDS pixel clock is made it to carry out corresponding frequency multiplication operation, the frequency-doubled signal produced adjusts its phase place again and makes it to keep phase place strictly identical with LVDS pixel clock, (to guarantee to sample LVDS data correctly, reliably in the operation of the follow-up sequential logic in conversion process), after de-jitter, enter global clock path that is stable, nothing swing again, thus produce rgb video clock.
Rgb video clock exports adjusting module 3-4, due to rgb video source data signals and rgb video clock synchronous, therefore using input half clock cycle of rgb video clock phase delay as RGB clock signal, make it effectively along the center that can be in rgb video source data, thus guarantee that follow-up conversion operations correctly to be sampled RGB data by this clock, this signal carries out de-jitter more afterwards, and output it to rgb video signal output module 3-10 by high speed signal Buffer Unit, to guarantee that this output clock has higher stability and good signal quality.
With RGB clock, LVDS video source synchronizing signal is become rgb video synchronizing signal and data with data transaction; When V-BY-ONE liquid crystal display module is the whole screen type of 8Lane, carry out separately the Video Quality Metric of the two LINK pattern of LVDS according to LINK translative mode control signal; Carry out separately the Video Quality Metric of left and right span mode and odd even span mode according to changeover control signal when V-BY-ONE display module is 8LANE split screen type.
The LVDS video source synchronizing signal of two LINK and LVDS video source data are converted to rgb video signal and send rgb video signal output module 3-10 to by dual link pattern rgb video modular converter 3-5;
The LVDS video source synchronizing signal of two LINK and LVDS video source data are converted to left half screen rgb video signal by left and right span mode rgb video modular converter 3-6, right half screen rgb video signal sends rgb video signal output module 3-8 to, the Video Quality Metric process of carrying out left and right span mode is: left and right span mode rgb video modular converter 3-6 by the LVDS data of two LINK according to " LINK1, LINK2 " form composition parallel data, determine when first complete video line is initial according to inputted LVDS synchronizing signal, according to aforementioned middle drawn row resolution value, with LVDS clock by front, the LINK parallel data of rear hemistich is sampled and writes a left side respectively, in right half screen DC-FIFO, buffer memory is also read on the other hand respective data cached and be separated into left half screen RGB data simultaneously by the rgb video clock of two frequencys multiplication, right half screen RGB data and synchronizing signal, form left half screen rgb video signal and right half screen rgb video signal, because the throughput of data and synchronizing signal read-write operation is equal, therefore the carrying out of conversion operations energy continous-stable.
The LVDS video source synchronizing signal of two LINK and LVDS video source data are converted to strange pixel rgb video signal by odd even span mode rgb video modular converter 3-7, dual pixel rgb video signal sends rgb video signal output module 3-8 to; The Video Quality Metric process of carrying out odd even span mode is: odd even span mode rgb video modular converter 3-7 first detects the LINK of two strange pixels and two dual pixels in the LVDS data of two LINK, again LVDS synchronizing signal and odd, even each two LINK data are formed respectively parallel data to process according to the two LINK patten transformation modes in aforementioned, thus the rgb video data of the strange pixel of respective generation, dual pixel and RGB synchronizing signal, form strange pixel rgb video signal and dual pixel rgb video signal.
Rgb video signal output module 3-8 selects the corresponding rgb video signal of signal behavior to send V-BY-ONE vision signal converting unit 4 to together with RGB output clock according to RGB modular converter.When producing synchronous mode and controlling then to video synchronization signal reverse operating; Phase place between effective edge of contrast RGB output clock and the sampling center of RGB data, and respectively fine delay process is done to eliminate phase difference between the two to output clock and data by signal lag assembly, guarantee output clock effectively along the sampling center being in data all the time.
S400, after receiving V-BY-ONE Video Quality Metric starting command from Video Quality Metric dispensing unit 5 V-BY-ONE vision signal converting unit 4 rgb video signal is converted to V-BY-ONE vision signal send to V-BY-ONE show module.The present embodiment V-BY-ONE vision signal converting unit 4, comprise: V-BY-ONE register module 4-1, left V-BY-ONE vision signal modular converter 4-2 and right wing V-BY-ONE vision signal modular converter 4-3 and V-BY-ONE liquid crystal display module connector 4-4, to being described in detail as follows of each module:
V-BY-ONE register module 4-1 controls according to the V-BY-ONE register command of write configuration and the operation that left V-BY-ONE vision signal modular converter 4-2 and right wing V-BY-ONE vision signal modular converter 4-3 carries out V-BY-ONE conversion simultaneously, and these V-BY-ONE register command comprise: the order of V-BY-ONE conversion configurations, V-BY-ONE change starting command.
Left V-BY-ONE vision signal modular converter 4-2 receives rgb video signal, perform configuration and the conversion operations of V-BY-ONE vision signal rgb video signal being converted to left passage 8lane, send the V-BY-ONE vision signal of the left passage 8lane after conversion to V-BY-ONE liquid crystal display module connector 4-4, corresponding configuration is completed when receiving V-BY-ONE conversion configurations order from V-BY-ONE register module 4-1, conversion operations, be transferred to V-BY-ONE when receiving V-BY-ONE from V-BY-ONE register module 4-1 and showing module initialization command by V-BY-ONE liquid crystal display module connector 4-4 and show module, conversion operations is started when receiving from V-BY-ONE register module 4-1 when V-BY-ONE changes starting command.
Right wing V-BY-ONE vision signal modular converter 4-3 receives rgb video signal, perform configuration and the conversion operations of V-BY-ONE vision signal rgb video signal being converted to right passage 8lane, send the 8lane right passage V-BY-ONE vision signal after conversion to V-BY-ONE liquid crystal display module connector 4-4, corresponding configuration is completed when receiving V-BY-ONE conversion configurations order from V-BY-ONE register module 4-1, conversion operations, be transferred to V-BY-ONE when receiving V-BY-ONE from V-BY-ONE register module 4-1 and showing module initialization command by V-BY-ONE liquid crystal display module connector 4-4 and show module, conversion operations is started when receiving from V-BY-ONE register module 4-1 when V-BY-ONE changes starting command.
When modulus of conversion block selection signal is two LINK pattern, then its RGB data and synchronizing signal (whole screen signal) is copied into two-way and exports to V-BY-ONE vision signal converting unit 4; When selection left and right split screen translative mode, then left and right half screen data and synchronizing signal export left half screen rgb video signal, right half screen rgb video signal respectively to left V-BY-ONE vision signal modular converter 4-2 and right wing V-BY-ONE vision signal modular converter 4-3; When selection odd even split screen translative mode, then strange pixel-parallel data, dual pixel parallel data and synchronizing signal export the strange split screen vision signal of RGB and the even split screen vision signal of RGB respectively to V-BY-ONE vision signal converting unit 4.
V-BY-ONE liquid crystal display module connector 4-4 receives left passage V-BY-ONE vision signal and right passage V-BY-ONE vision signal simultaneously, and show module 6 with V-BY-ONE and be connected, left passage V-BY-ONE vision signal and right passage V-BY-ONE vision signal are sent to V-BY-ONE and show module.
Video Quality Metric dispensing unit 5, the characteristic of the 8lane that will receive according to the present invention not split screen, 8lane2 split screen, 8lane4 split screen LVDS vision signal, LVDS vision signal decoding parametric is set, produce LVDS video decode control signal, send to LVDS video signal decoding unit 2,8lane not split screen, 8lane2 split screen, 8lane4 split screen LVDS vision signal respectively as shown in Fig. 5, Fig. 6 and Fig. 7; LVDS Video Quality Metric parameter is set, produces LVDS Video Quality Metric control signal, send rgb video signal converting unit 3 to; Read V-BY-ONE Video Quality Metric configuration parameter and the order of V-BY-ONE conversion configurations, V-BY-ONE display module initialization command are sent to V-BY-ONE vision signal converting unit 4; V-BY-ONE vision signal converting unit 4 is sent to from sending V-BY-ONE Video Quality Metric starting command after rgb video signal converting unit 3 receives V-BY-ONE Video Quality Metric enabling signal.The present embodiment Video Quality Metric dispensing unit 5 comprises: manual toggle switch 5-1, jtag interface 5-2 and V-BY-ONE Video Quality Metric configuration module 5-3, to being described in detail as follows of each module:
Manual toggle switch 5-1 arranges LVDS vision signal decoding parametric and LVDS Video Quality Metric parameter, jtag interface 5-2 receives V-BY-ONE Video Quality Metric configuration parameter, LVDS vision signal decoding parametric is converted to LVDS video decode control signal and sends LVDS video signal decoding unit 2 to by V-BY-ONE Video Quality Metric configuration module 5-3, be LVDS Video Quality Metric control signal by LVDS Video Quality Metric Parameter Switch, send rgb video signal converting unit 3 to, read V-BY-ONE Video Quality Metric configuration parameter and the order of V-BY-ONE conversion configurations is sent to V-BY-ONE vision signal converting unit 4, V-BY-ONE shows module initialization command, after receiving V-BY-ONE Video Quality Metric enabling signal from rgb video signal converting unit 3, produce V-BY-ONE Video Quality Metric starting command send V-BY-ONE vision signal converting unit 4 to.
Before powering on, first toggle switch 5-1 is manually set to the configuration of LVDS video decode and conversion, after powering on, produce LVDS video decode control signal and LVDS Video Quality Metric control signal by V-BY-ONE Video Quality Metric configuration module 5-3 according to its dial-up state, V-BY-ONE Video Quality Metric configuration parameter is read afterwards from jtag interface 5-2, and it is written in V-BY-ONE vision signal converting unit 4 in the mode of register command one by one, first write the order of V-BY-ONE conversion configurations, start and write V-BY-ONE again after normal work to show module initialization command when confirmation V-BY-ONE vision signal converting unit 4 completes configuration, the state value of its register is then read after often writing an order, to guarantee that command execution completes, V-BY-ONE Video Quality Metric control signal ought be received afterwards and then V-BY-ONE is changed starting command write register, V-BY-ONE Video Quality Metric is operated start to carry out.
Each functional module of the present invention all realizes by FPGA, also its function can be realized with common MCU, for the conversion of V-BY-ONE vision signal converting unit 4 also by using two special V-BY-ONE bridging chips to realize V-BY-ONE signal respectively for V-BY-ONE Video Quality Metric configuration module 5-3.
Therefore; the present invention is not limited to above-mentioned execution mode; for those skilled in the art, be also considered as within the protection range of patent of the present invention according to know-why of the present invention and scheme or the some improvement made under enlightenment of the present invention, change, retouching, distortion, replacement.
Claims (15)
1. LVDS vision signal is converted to the method being applicable to 8LaneV-BY-ONE vision signal, it is characterized in that:
LVDS vision signal is transmitted in two Link mode, is converted to rgb video signal;
Configuration and the conversion that starting command controls to carry out V-BY-ONE conversion is changed according to the order of V-BY-ONE conversion configurations and V-BY-ONE.
2. LVDS vision signal is converted to the method being applicable to 8LaneV-BY-ONE vision signal according to claim 1, it is characterized in that LVDS vision signal is converted to rgb video signal to be comprised:
Receive LVDS vision signal, and the LVDS vision signal that demodulation receives, produce LVDS parallel demodulation data and LVDS pixel clock;
According to LVDS video decode control signal, video decode is carried out to LVDS parallel demodulation data, produce LVDS video source data and LVDS video source synchronizing signal; And
According to LVDS Video Quality Metric control signal, LVDS video source data and LVDS video source synchronizing signal are converted to rgb video signal.
3. LVDS vision signal is converted to the method being applicable to 8LaneV-BY-ONE vision signal according to claim 2, it is characterized in that described reception LVDS vision signal and described in demodulation, the LVDS vision signal that receives comprises:
Receive LVDS vision signal, described LVDS vision signal comprises LVDS receive clock and LVDS data;
Received LVDS vision signal is terminated operation, LVDS receive clock and LVDS data are exported;
Demodulation is carried out to the LVDS receive clock of each LINK, produces demodulation clock and demodulation enable signal;
With demodulation enable signal, the LVDS data demodulates of this LINK is become parallel data by the demodulation clock of each LINK, LVDS receive clock is demodulated into LVDS pixel clock simultaneously.
4. LVDS vision signal is converted to the method being applicable to 8LaneV-BY-ONE vision signal according to claim 2, it is characterized in that describedly carrying out video decode to LVDS parallel demodulation data and comprising:
LVDS pixel clock is become LVDS video source pixel clock by global clock path integration, respective LVDS parallel demodulation data to be write respectively in DC-FIFO after buffer memory with the LVDS pixel clock of each LINK of input simultaneously, read one by one with LVDS video source pixel clock, make it to become synchrodata;
When receiving LVDS odd even pixel reverse control signal, the data of LINK1 and LINK2 in two links are exchanged;
According to the LVDS parallel demodulation decoding data of the LVDS video decode control signal received to the synchronous each LINK read, decode LVDS video source synchronizing signal;
According to the LVDS parallel demodulation decoding data of the LVDS video decode control signal received to the synchronous each LINK read, decode the LVDS video source data signal of each LINK.
5. LVDS vision signal is converted to the method being applicable to 8LaneV-BY-ONE vision signal according to claim 2, it is characterized in that rgb video signal conversion comprises:
The rgb video clock configuration signal of the two LINK patterns matched is produced according to LVDS Video Quality Metric control signal;
According to the rgb video clock configuration signal of produced two LINK patterns, produced configuration parameter and the configuration enable signal of corresponding two LINK pattern by local clock pulses;
Rgb video clock is produced according to configurable clock generator and enable signal;
Using half clock cycle of rgb video clock phase delay of input as RGB clock signal;
The LVDS video source synchronizing signal of two LINK and LVDS video source data are converted to rgb video signal to export;
The LVDS video source synchronizing signal of two LINK and LVDS video source data are converted to left half screen rgb video signal, right half screen rgb video signal exports;
The LVDS video source synchronizing signal of two LINK and LVDS video source data are converted to strange pixel rgb video signal, dual pixel rgb video signal send to rgb video signal export;
The corresponding rgb video signal of signal behavior is selected to carry out the conversion of V-BY-ONE vision signal together with the output of RGB output clock according to RGB modular converter.
6. LVDS vision signal is converted to the method being applicable to 8LaneV-BY-ONE vision signal according to claim 5, it is characterized in that the conversion of described V-BY-ONE vision signal comprises:
The configuration changed according to the V-BY-ONE register command control V-BY-ONE of write and operation;
Receive rgb video signal, perform the configuration and conversion operations that rgb video signal are converted to 8Lane left passage V-BY-ONE vision signal;
Receive rgb video signal, perform the configuration and conversion operations that rgb video signal are converted to 8Lane right passage V-BY-ONE vision signal;
Receive left passage 8Lane V-BY-ONE vision signal and right passage 8Lane V-BY-ONE vision signal simultaneously, and show module with V-BY-ONE and be connected, left passage 8Lane V-BY-ONE vision signal and right passage 8Lane V-BY-ONE vision signal are sent to V-BY-ONE and show module.
7. LVDS vision signal is converted to the method being applicable to 8LaneV-BY-ONE vision signal according to claim 1, it is characterized in that the configuration that described V-BY-ONE changes and conversion comprise:
LVDS vision signal decoding parametric and LVDS Video Quality Metric parameter are set;
Receive V-BY-ONE Video Quality Metric configuration parameter;
LVDS vision signal decoding parametric is converted to LVDS video decode control signal and sends LVDS video signal decoding unit to; Be LVDS Video Quality Metric control signal by LVDS Video Quality Metric Parameter Switch; Reading V-BY-ONE Video Quality Metric configuration parameter and send the order of V-BY-ONE conversion configurations, V-BY-ONE display module initialization command, sending V-BY-ONE vision signal converting unit to when producing V-BY-ONE Video Quality Metric starting command after reception V-BY-ONE Video Quality Metric enabling signal.
8. LVDS vision signal is converted to the system being applicable to 8LaneV-BY-ONE vision signal, it is characterized in that, comprising:
LVDS vision signal converting unit, for being converted to rgb video signal by LVDS vision signal;
V-BY-ONE vision signal converting unit, for changing according to the order of V-BY-ONE conversion configurations and V-BY-ONE configuration and the conversion that starting command controls to carry out V-BY-ONE conversion.
9. LVDS vision signal is converted to the system being applicable to 8LaneV-BY-ONE vision signal according to claim 8, it is characterized in that described LVDS vision signal converting unit comprises:
LVDS video reception unit, for receiving LVDS vision signal, and the LVDS vision signal that demodulation receives, produce LVDS parallel demodulation data and LVDS pixel clock;
LVDS video signal decoding unit, for carrying out video decode according to LVDS video decode control signal to LVDS parallel demodulation data, produces LVDS video source data and LVDS video source synchronizing signal; And
Rgb video signal converting unit, for being converted to rgb video signal according to LVDS Video Quality Metric control signal by LVDS video source data and LVDS video source synchronizing signal.
10. LVDS vision signal is converted to the system being applicable to 8LaneV-BY-ONE vision signal according to claim 9, characterized by further comprising Video Quality Metric dispensing unit, and described Video Quality Metric dispensing unit comprises:
Manual toggle switch, for arranging LVDS vision signal decoding parametric and LVDS Video Quality Metric parameter;
Jtag interface, for receiving V-BY-ONE Video Quality Metric configuration parameter;
V-BY-ONE Video Quality Metric configuration module, sends LVDS video signal decoding unit to for LVDS vision signal decoding parametric is converted to LVDS video decode control signal; Be LVDS Video Quality Metric control signal by LVDS Video Quality Metric Parameter Switch, send rgb video signal converting unit to; Read V-BY-ONE Video Quality Metric configuration parameter and the order of V-BY-ONE conversion configurations, V-BY-ONE display module initialization command are sent to V-BY-ONE vision signal converting unit, after receiving V-BY-ONE Video Quality Metric enabling signal from rgb video signal converting unit, produce V-BY-ONE Video Quality Metric starting command send V-BY-ONE vision signal converting unit to.
11. according to claim 9 LVDS vision signal be converted to the system being applicable to 8LaneV-BY-ONE vision signal, it is characterized in that described LVDS video reception unit comprises:
LVDS video signal interface, for receiving LVDS vision signal, described LVDS vision signal comprises LVDS receive clock and LVDS data;
LVDS video reception termination module, for the operation that is terminated to received LVDS vision signal, exports LVDS receive clock and LVDS data;
LVDS clock signal demodulation module, for carrying out demodulation to the LVDS receive clock of each LINK, produces demodulation clock and demodulation enable signal; And
LVDS demodulated data signal module, become parallel data for the demodulation clock according to each LINK with the LVDS data demodulates of demodulation enable signal to this LINK, LVDS receive clock is demodulated into LVDS pixel clock simultaneously.
12. are converted to according to LVDS vision signal described in claim 11 system being applicable to 8LaneV-BY-ONE vision signal, it is characterized in that described LVDS video reception unit also comprises:
LVDS demodulation dynamic calibration module, for carrying out dynamic calibration in real time to the string signal of LVDS receive clock and LVDS data respectively respectively in demodulating process.
13. according to claim 9 LVDS vision signal be converted to the system being applicable to 8LaneV-BY-ONE vision signal, it is characterized in that described LVDS video signal decoding unit comprises:
LVDS audio video synchronization buffer module, the LVDS pixel clock of LINK1 is become LVDS video source pixel clock by global clock path integration, respective LVDS parallel demodulation data to be write respectively in DC-FIFO after buffer memory with the LVDS pixel clock of each LINK inputted simultaneously, read one by one with LVDS video source pixel clock, make it to become synchrodata;
LVDS vision signal order module, for exchanging the data of LINK1 and LINK2 in two links when receiving LVDS odd even pixel reverse control signal;
LVDS video synchronization signal decoder module, for according to the LVDS parallel demodulation decoding data of the LVDS video decode control signal received from Video Quality Metric dispensing unit to the synchronous each LINK read, decodes LVDS video source synchronizing signal;
LVDS video data decoding module, according to the LVDS parallel demodulation decoding data of the LVDS video decode control signal received from Video Quality Metric dispensing unit to the synchronous each LINK read, decodes the LVDS video source data signal of each LINK.
14. according to claim 9 LVDS vision signal be converted to the system being applicable to 8LaneV-BY-ONE vision signal, it is characterized in that described rgb video signal converting unit comprises:
Rgb video signal self-adaptive control module, produces the rgb video clock configuration signal of the two LINK patterns matched according to LVDS Video Quality Metric control signal;
Rgb video clock adaptive configuration module, for the rgb video clock configuration signal according to produced two LINK patterns, is produced configuration parameter and the configuration enable signal of corresponding two LINK pattern by local clock pulses;
Rgb video clock generating module, for producing rgb video clock according to configurable clock generator and enable signal;
Rgb video clock export adjusting module, for will input half clock cycle of rgb video clock phase delay as RGB clock signal;
Dual link pattern rgb video modular converter, exports for the LVDS video source synchronizing signal of two LINK and LVDS video source data being converted to rgb video signal;
Left and right span mode rgb video modular converter, for the LVDS video source synchronizing signal of two LINK and LVDS video source data being converted to left half screen rgb video signal, right half screen rgb video signal exports;
Odd even span mode rgb video modular converter, for the LVDS video source synchronizing signal of two LINK and LVDS video source data are converted to strange pixel rgb video signal, dual pixel rgb video signal send to rgb video signal export;
Rgb video signal output module, for selecting the corresponding rgb video signal of signal behavior to send V-BY-ONE vision signal converting unit to together with RGB output clock according to RGB modular converter.
Described in 15. according to Claim 8 ~ 14 any one, LVDS vision signal is converted to the system being applicable to 8LaneV-BY-ONE vision signal, it is characterized in that described V-BY-ONE vision signal converting unit comprises:
V-BY-ONE register module, for configuration and the operation of the V-BY-ONE register command control V-BY-ONE conversion according to write;
Left V-BY-ONE vision signal modular converter, for receiving rgb video signal, performs the configuration and conversion operations that rgb video signal are converted to left passage V-BY-ONE vision signal;
Right wing V-BY-ONE vision signal modular converter, for receiving rgb video signal, performs the configuration and conversion operations that rgb video signal are converted to right passage V-BY-ONE vision signal;
V-BY-ONE liquid crystal display module connector, for receiving left passage V-BY-ONE vision signal and right passage V-BY-ONE vision signal simultaneously, and show module with V-BY-ONE and be connected, left passage V-BY-ONE vision signal and right passage V-BY-ONE vision signal are sent to V-BY-ONE and show module.
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