CN203574614U - Variable gain amplifier with low power consumption - Google Patents

Abstract

The utility model relates to the field of analogue integrated circuits. The utility model discloses a variable gain amplifier with low power consumption, and the variable gain amplifier comprises a differential source-electrode-sharing amplification unit, a variable load resistor array Rd1 to Rdn-1, a first digital control switch array A1 to An-1, a second digital control switch array (shown in the patent specification), a variable current source array I1 to In-1, a variable source electrode feedback resistor array Rs1 to Rsn-1, a switch array K1 to Kn-1, fixed current sources I0 and ISS, and fixed resistor Rd0 and Rs0. The effective resistance values of the variable load resistor array Rd1 to Rdn-1 are respectively controlled by the first digital control switch array A1 to An-1. The current sources of the variable current source array I1 to In-1 are respectively controlled by the second digital control switch array (shown in the patent specification). The effective resistance values of the variable source electrode feedback resistor array Rs1 to Rsn-1 are respectively controlled by the switch array K1 to Kn-1, and the output common-mode voltage of the variable gain amplifier is enabled to meet a conditional expression (shown in the patent specification). Through the above designed method, a common-mode feedback circuit is saved while the stable output common-mode voltage is achieved, thereby reducing the complexity of circuit design and the power consumption.

Description

A kind of low-power consumption variable gain amplifier

Technical field

The utility model relates to field of analog integrated circuit, is especially specifically related to a kind of short-distance wireless that is applied to and connects the low-power consumption variable gain amplifier without common mode feedback circuit in transceiver.

Background technology

Variable gain amplifier (VGA) is the key components in AGC (automatic gain control) system (AGC), be mainly used in wireless interface transmitting-receiving machine system, can according to signal power, to signal, amplify or decay, dropout in the time of a little less than causing receiver obstruction or signal to cross while avoiding overflow, is conducive to improve the dynamic range that whole wireless interface is received and dispatched machine system.In AGC system, the design performance of VGA directly affects selectivity and the sensitivity of AGC.In modern receiver structure, conventionally the detection of signal power is all placed in numeric field and is carried out, this makes numerically controlled VGA obtain applying more and more widely.Common digital control VGA structure has two kinds: a kind of is closed-loop structure, by degenerative method, can accurately set gain, have the higher linearity, but its bandwidth is little, circuit design more complicated, and power consumption is larger; Another kind of open loop structure, is with roomyly by changing the mutual conductance of open loop circuit and the variation that load value (A=gmRL) is realized gain, having, and circuit is simple, feature low in energy consumption.

The VGA of the fully differential common source structure based on source negative feedback is with roomyly owing to having, and the advantage such as the linearity is better, low in energy consumption, is widely applied.The type VGA can realize gain-variable by changing source feedback resistance and load resistance value resistance.But when changing VGA gain by change output loading, its output common mode change in voltage is larger, stablizes output common mode so need to stablize output common mode potential circuit, adopts traditionally common mode feedback circuit to stablize output common mode.

Refer to Fig. 1, this Fig. 1 shows variable gain amplifier (VGA) circuit of stablizing output common mode with common mode feedback circuit.This VGA adopts the fully differential commonsource amplifier structure with source negative feedback, its voltage gain A _v' can be expressed as:

${A_V}^{\′}=N\frac{R_D\left|\right|R_C}{R_S/2}\≈N\frac{R_D}{R_S/2}$ (R generally speaking _c>>R _d) (1)

Wherein N is transistor M3 and the size ratio of M7, R _s, R _dand R _cbe respectively source feedback resistance, load resistance and for detection of common mode electrical level, be added in the resistance of output, its gain can be by changing R _s, R _dresistance is realized.

Adopt and change output load resistance R _dregulate VGA gain can make the common mode electrical level of difference output change along with the variation of load, thereby make cannot normally work with the late-class circuit of VGA cascade.Can stablize output common mode by common mode feedback loop (CMFB), but this can increase the complexity of circuit design greatly, increase the power consumption of whole VGA, and need to add extra resistance to detect output common mode voltage, consume a large amount of chip areas.

Utility model content

In order to solve the problems of the technologies described above, the utility model proposes a kind of new straightforward procedure and stablize output common mode voltage, by when changing load resistance, the electric current that load is flow through in change is so that output common mode voltage remains unchanged, so just, saved traditional common mode feedback circuit, simplify circuit design, reduced power consumption and the chip area of VGA.

The main realization approach of the low-power consumption variable gain amplifier without common mode feedback circuit of the present utility model is:

Gain with the fully differential commonsource amplifier of source negative feedback can be expressed as:

$A_v=\frac{R_D}{\frac{1}{g_m}+R_S/2}\≈\frac{R_D}{R_S/2}---\left(2\right)$

G in formula _mfor the mutual conductance of difference input to pipe, R _dfor load resistance, R _sfor source feedback resistance.By formula (2), can find out that VGA gain is by resistance R _dand R _sratio determine, in the utility model by changing respectively R with switch arrays _d, R _svalue, obtain multiple different gain, and by changing load R _din time, changes and to flow through load R _delectric current, guarantee that output common mode voltage keeps constant, realized a kind of new simple method of stablizing output common mode voltage, saved traditional common mode feedback circuit.

The technical scheme that the utility model adopts is: a kind of low-power consumption variable gain amplifier without common mode feedback circuit, comprises difference common source amplifying unit, variable load electric resistance array R _d1～R _dn-1, the first digital control switch arrays A ₁～A _n-1, the second digital control switch arrays

variable current source array I ₁～I _n-1, variable source class feedback resistance array R _s1～R _sn-1, switch arrays K ₁～K _n-1, fixed current source I ₀and I _sS, fixed resistance R _d0and R _s0,

Described difference common source amplifying unit, comprises the first differential amplification pipe M1 and the second differential amplification pipe M2 in parallel, for receiving and amplified difference signal,

Described variable load electric resistance array R _d1～R _dn-1with fixed resistance R _d0after series connection, be connected to supply voltage V _dDand between the drain electrode of difference common source amplifying unit, variable load electric resistance array R _d1～R _dn-1in effective access resistance value by the first digital control switch arrays A ₁～A _n-1institute controls,

Described variable current source array I ₁～I _n-1, be connected to supply voltage V _dDand between the drain electrode of difference common source amplifying unit, this variable current source array I ₁～I _n-1current source by the second digital control switch arrays institute controls, the second digital control switch arrays

with the first digital control switch arrays A ₁～A _n-1on off state is contrary, even switch A ₁conducting, switch

disconnect; If switch A ₁disconnect, switch

conducting,

Described variable source class feedback resistance array R _s1～R _sn-1with fixed resistance R _s0after parallel connection, be connected between the source electrode of the first differential amplification pipe M1 and the source electrode of the second differential amplification pipe M2 variable source class feedback resistance array R _s1～R _sn-1in effective access resistance value by switch arrays K ₁～K _n-1institute controls,

Described fixed current source I ₀be connected to supply voltage V _dDand between the drain electrode of difference common source amplifying unit,

Described fixed current source I _sSbe connected between the source electrode and earthed voltage of difference common source amplifying unit,

The described variable gain amplifier output common mode voltage formula that meets the following conditions:

$V_C=V_{\mathrm{DD}}-[I_{\mathrm{SS}}-I_0-B_1\·I_1-B_2\·I_2-\·\·\·-B_{n-1}\·I_{n-1})\×(R_{d0}+{\stackrel{\‾}{B}}_1\·R_{d1}+{\stackrel{\‾}{B}}_2\·R_{d2}+\·\·\·+{\stackrel{\‾}{B}}_{n-1}\·R_{\mathrm{dn}-1})],$

Wherein

be the first digital control switch arrays A ₁, A ₂a _n-1on off state, if the first digital control switch arrays A ₁, A ₂a _n-1conducting,

value be 0; If the first digital control switch arrays A ₁, A ₂a _n-1disconnect,

value be 1; B ₁, B ₂b _n-1be the second digital control switch arrays

on off state, if the second digital control switch arrays conducting, B ₁, B ₂b _n-1value be 1; If the second digital control switch arrays

disconnect, B ₁, B ₂b _n-1value be 0; And

and A ₁, A ₂a _n-1logic opposite signal, i.e. A each other ₁if conducting,

turn-off A ₁if turn-off,

conducting; V _crepresent the output common mode magnitude of voltage that design is desired.

Further, described variable load electric resistance array R _d1～R _dn-1by n-1 resistance, connected, by described the first digital control switch arrays A ₁～A _n-1control and make each corresponding resistance R _d1, R _d2, R _dn-1by short circuit or be access in load, thereby change the resistance value of load.

Further, described variable source class feedback resistance array R _s1～R _sn-1in parallel by n-1 resistance, wherein one end of each resistance is connected to the source electrode of described the first differential amplification pipe M1, and the other end of described each resistance is connected to the source electrode of described the second differential amplification pipe M2, switch arrays K ₁～K _n-1in K switch ₁with resistance R _s1series connection, K switch ₂with resistance R _s2series connection ..., K switch _n-1with resistance R _sn-1series connection, thereby by switch arrays K ₁～K _n-1in K switch ₁, K ₂, K _n-1disconnect and conducting, change the resistance value of access source electrode.

Further, get n=2, variable load electric resistance array R _d1～R _dn-1comprise resistance R _d1, load resistance comprises resistance R _d0and resistance R _d1, described resistance R _d0comprise symmetrical two parts, be respectively resistance A_R _d0with resistance B_R _d0, and resistance R _d0resistance value=resistance A_R _d0resistance value=resistance B_R _d0resistance value, described resistance A_R _d0for resistance R 5, described resistance B_R _d0for resistance R 6, described resistance R _d1comprise symmetrical two parts, be respectively resistance A_R _d1with resistance B_R _d1, and resistance R _d1resistance value=resistance A_R _d1resistance value=resistance B_R _d1resistance value, described resistance A_R _d1for resistance R 7, described resistance B_R _d1for resistance R 8, described resistance R 7 and resistance R 5 series connection, the other end of resistance R 7 and supply voltage V _dDconnect, the other end of resistance R 5 is connected with the drain electrode of the first differential amplification pipe M1, described resistance R 8 and resistance R 6 series connection, resistance R 8 other ends and supply voltage V _dDconnect, resistance R 6 other ends are connected with the drain electrode of the second differential amplification pipe M2,

Described the first digital control switch arrays A ₁～A _n-1comprise digital control switch A ₁, described digital control switch A ₁by switching tube M13 and switching tube M14, formed, the source electrode of described switching tube M13, switching tube M14 respectively with supply voltage V _dDconnect, the grid of described switching tube M13, switching tube M14 is external digital controlled signal A respectively _d1, the drain electrode of described switching tube M13 is connected to the common connection end of resistance R 5 and resistance R 7, and the drain electrode of described switching tube M14 is connected to the common connection end of resistance R 6 and resistance R 8,

Described the second digital control switch arrays comprise digital control switch

described digital control switch

by switching tube M12 and COMS transmission gate, formed the source electrode of described switching tube M12 and supply voltage V _dDconnect, described switching tube M12 drain electrode is connected with the grid of electric current source capsule M11 with electric current source capsule M10 respectively, be connected with cmos transmission gate one end simultaneously, described COMS transmission gate consists of switching tube M19 and switching tube M20 parallel connection, described COMS transmission gate one end is connected with the grid of transistor M9, the other end is connected with drain electrode, electric current source capsule M10 and the grid of electric current source capsule M11 of switching tube M12, and the grid of described switching tube M12, COMS transmission gate switch pipe M20 is external digital controlled signal A all _d1, the external digital controlled signal A of grid of described COMS transmission gate switch pipe M19 _{d1_N}, digital controlled signal A _d1with digital controlled signal A _{d1_N}logic opposite signal each other,

Described variable current source array I ₁～I _n-1comprise current source I ₁, described current source I ₁comprise symmetrical two parts, be respectively electric current A_I ₁with electric current B_I ₁, and electric current I ₁current value=electric current A_I ₁current value=electric current B_I ₁current value, described electric current A_I ₁by electric current source capsule M10 and transistor M7, M8 and M9 mirror image reference current I _rEFform described electric current B_I ₁by electric current source capsule M11 and transistor M7, M8 and M9 mirror image reference current I _rEFform, the grid of described electric current source capsule M10 and electric current source capsule M11 is all connected with described COMS transmission gate one end, the source electrode of described electric current source capsule M10 and electric current source capsule M11 all with supply voltage V _dDconnect, the drain electrode of described electric current source capsule M10 and electric current source capsule M11 is connected with the drain electrode of electric current source capsule M4 with electric current source capsule M3 respectively,

Described fixed current source I ₀comprise that symmetrical two parts are respectively electric current A_I ₀with electric current B_I ₀, and electric current I ₀current value=electric current A_I ₀current value=electric current B_I ₀current value, described electric current A_I ₀by electric current source capsule M3 and transistor M7, M8 and M9 mirror image reference current I _rEFform described electric current B_I ₀by electric current source capsule M4 and transistor M7, M8 and M9 mirror image reference current I _rEFform, the source electrode of described electric current source capsule M3 and electric current source capsule M4 all with supply voltage V _dDconnect, the grid of described electric current source capsule M3 and electric current source capsule M4 is connected with drain electrode with the grid of electric current source capsule M9 by described cmos transmission gate,

The described variable gain amplifier output common mode voltage formula that meets the following conditions:

$V_C=V_{\mathrm{DD}}-[(I_{\mathrm{SS}}-I_0-B_1\·I_1)\×(R_{d0}+{\stackrel{\‾}{B}}_1\·R_{d1})]$

As digital controlled signal A _d1=0, A _{d1_N}=1 o'clock, switching tube M13 and switching tube M14 conducting, i.e. digital control switch A ₁conducting, resistance R 7 and resistance R 8 be by short circuit, i.e. variable load electric resistance array R _d1～R _dn-1in load R _d1by short circuit, now total load resistance is R _d0, the resistance value of the resistance value=resistance R 6 of total load resistance value=resistance R 5; Meanwhile, switching tube M12 conducting, cmos transmission gate disconnects, and the grid potential of electric current source capsule M10, electric current source capsule M11 is drawn high supply voltage V _dD, so electric current source capsule M10, electric current source capsule M11 disconnection, i.e. digital control switch

disconnect variable current source battle array A_I ₁and B_I ₁disconnect, and due to fixed current source A_I ₀and B_I ₀place in circuit, is respectively I so flow through the electric current of load resistance R5, resistance R 6 _ss-A_I ₀and I _ss-B_I ₀, and I _ss-A_I ₀=I _ss-B_I ₀;

Now, digital control switch A ₁conducting,

digital control switch disconnect, i.e. B ₁=0, be updated to above-mentioned conditional $V_C=V_{\mathrm{DD}}-[(I_{\mathrm{SS}}-I_0-B_1\·I_1)\×(R_{d0}+{\stackrel{\‾}{B}}_1\·R_{d1})]$ In obtain:

V _C＝V _DD-[(I _SS-I ₀)×(R _d0)]

As digital controlled signal A _d1=1, A _{d1_N}=0 o'clock, switching tube M13 and switching tube M14 disconnected, i.e. digital control switch A ₁disconnect, now variable load electric resistance array R _d1～R _dn-1in effective access resistance R _d1, total load resistance is resistance R _d1with resistance R _d0series connection, total load resistance value=resistance R 5 resistance values+resistance R 7 resistance values=resistance R 6 resistance values+resistance R 8 resistance values; Meanwhile, switching tube M12 disconnects, cmos transmission gate conducting, and the grid of electric current source capsule M10, electric current source capsule M11 is connected with the grid of transistor M9, forms current mirror, i.e. digital control switch

conducting, variable current source array A_I ₁and B_I ₁access circuit, now flows through load resistance R _d1with resistance R _d0electric current be respectively as I _ss-A_I ₀-A_I ₁and I _ss-B_I ₀-B_I ₁, and have I _ss-A_I ₀-A_I ₁=I _ss-B_I ₀-B_I ₁;

Now, digital control switch A ₁disconnect,

digital control switch

conducting, i.e. B ₁=1, be updated to above-mentioned conditional $V_C=V_{\mathrm{DD}}-[(I_{\mathrm{SS}}-I_0-B_1\·I_1)\×(R_{d0}+{\stackrel{\‾}{B}}_1\·R_{d1})]$ In obtain:

V _C＝V _DD-[(I _SS-I ₀-I ₁)×(R _d0+R _d1)]

Thereby V _dD-[(I _sS-I ₀-I ₁) * (R _d0+ R _d1)]=V _dD-[(I _sS-I ₀) * (R _d0)]=V _c, by current source I reasonable in design ₁and resistance R _d1value, guarantee that variable gain amplifier output common mode voltage keeps constant.

Further, according to specific implementation technique supply voltage V _dD, design suitable fixed current source I _sS, I ₀with fixed resistance R _d0, obtain

Situation when n>2 can obtain general expression by that analogy:

$V_C=V_{\mathrm{DD}}-[I_{\mathrm{SS}}-I_0-B_1\·I_1-B_2\·I_2-\·\·\·-B_{n-1}\·I_{n-1})\×(R_{d0}+{\stackrel{\‾}{B}}_1\·R_{d1}+{\stackrel{\‾}{B}}_2\·R_{d2}+\·\·\·+{\stackrel{\‾}{B}}_{n-1}\·R_{\mathrm{dn}-1})],$

Operation principle of the present utility model is: as the first digital control switch arrays A ₁～A _n-1during whole conducting,

equal 0), the second digital control switch arrays

for its logic opposite signal, digital control switch arrays all disconnect (B ₁, B ₂b _n-1be 0), the effective resistance value that now accesses load is minimum value R _d0, the electric current I in variable current source array ₁～I _n-1access, does not flow through load resistance branch road R _d0electric current be maximum, its output common mode voltage:

V _C＝V _DD-[(I _SS-I ₀)×R _d0]

When passing through to select variable load electric resistance array R _d1～R _dn-1while changing gain, for example, make A ₁switch disconnects

be 1), A ₂～A _n-1still conducting (

be 0),

conducting (B ₁be 1),

still disconnect (B ₂b _n-1be 0), resistance R now _d1in access load, R _d2～R _dn-1by short circuit, load effective resistance value is (R _d0+ R _d1) short circuit, the electric current I in variable current source array ₁access, flows through resistance (R _d0+ R _d1) electric current be (I _sS-I ₀-I ₁), its output common mode voltage is:

V _C1＝V _DD-[(I _SS-I ₀-I ₁)×（R _d0+R _d1)]

Design suitable current source I ₁with access resistance R _d1make it meet V _c1=V _c, that is:

(I _SS-I ₀-I ₁)×（R _d0+R _d1)＝(I _SS-I ₀)×R _d0

Output common mode in this case equates with common mode electrical level before;

By that analogy, design suitable variable current source array I ₁～I _n-1, and variable load electric resistance array R _d1～R _dn-1resistance value, makes it to meet the following conditions:

$V_C=V_{\mathrm{DD}}-[I_{\mathrm{SS}}-I_0-B_1\·I_1-B_2\·I_2-\·\·\·-B_{n-1}\·I_{n-1})\×(R_{d0}+{\stackrel{\‾}{B}}_1\·R_{d1}+{\stackrel{\‾}{B}}_2\·R_{d2}+\·\·\·+{\stackrel{\‾}{B}}_{n-1}\·R_{\mathrm{dn}-1})]$

Can guarantee under different gains, it is stable that the output common mode voltage of VGA keeps.

The utility model is by adopting technique scheme, and compared with prior art, tool has the following advantages: by this method for designing, when output common mode is stablized in same realization, save common mode feedback circuit, thereby reduced complex circuit designs and power consumption, saved chip area.

Accompanying drawing explanation

Fig. 1 is the gain-changeable amplifier circuit structure chart with common mode feedback circuit of the prior art;

Fig. 2 is the gain-changeable amplifier circuit structure chart of the first embodiment of the present utility model;

Fig. 3 is the gain-changeable amplifier circuit structure chart of the second embodiment of the present utility model.

Embodiment

Now with embodiment, the utility model is further illustrated by reference to the accompanying drawings.

Embodiment 1:

As shown in Figure 2, a kind of low-power consumption variable gain amplifier without common mode feedback circuit of the utility model, described variable gain amplifier comprises difference common source amplifying unit, variable load electric resistance array R _d1～R _dn-1, the first digital control switch arrays A ₁～A _n-1, the second digital control switch arrays variable current source array I ₁～I _n-1, variable source class feedback resistance array R _s1～R _sn-1, switch arrays K ₁～K _n-1, fixed current source I ₀and I _sS, fixed resistance R _d0and R _s0,

Described difference common source amplifying unit, comprises the first differential amplification pipe M1 and the second differential amplification pipe M2 in parallel, for receiving and amplified difference signal,

Described variable load electric resistance array R _d1～R _dn-1with fixed resistance R _d0after series connection, be connected to supply voltage V _dDand between the drain electrode of difference common source amplifying unit, variable load electric resistance array R _d1～R _dn-1in effective access resistance value by the first digital control switch arrays A ₁～A _n-1institute controls,

Described variable current source array I ₁～I _n-1, be connected to supply voltage V _dDand between the drain electrode of difference common source amplifying unit, this variable current source array I ₁～I _n-1current source by the second digital control switch arrays

institute controls, the second digital control switch arrays

with the first digital control switch arrays A ₁～A _n-1on off state is contrary, even switch A ₁conducting, switch disconnect; If switch A ₁disconnect, switch

conducting,

Described variable source class feedback resistance array R _s1～R _sn-1with fixed resistance R _s0after parallel connection, be connected between the source electrode of the first differential amplification pipe M1 and the source electrode of the second differential amplification pipe M2 variable source class feedback resistance array R _s1～R _sn-1in effective access resistance value by switch arrays K ₁～K _n-1institute controls,

Described fixed current source I ₀be connected to supply voltage V _dDand between the drain electrode of difference common source amplifying unit,

Described fixed current source I _sSbe connected between the source electrode and earthed voltage of difference common source amplifying unit,

The described variable gain amplifier output common mode voltage formula that meets the following conditions:

$V_C=V_{\mathrm{DD}}-[I_{\mathrm{SS}}-I_0-B_1\·I_1-B_2\·I_2-\·\·\·-B_{n-1}\·I_{n-1})\×(R_{d0}+{\stackrel{\‾}{B}}_1\·R_{d1}+{\stackrel{\‾}{B}}_2\·R_{d2}+\·\·\·+{\stackrel{\‾}{B}}_{n-1}\·R_{\mathrm{dn}-1})],$

Wherein be the first digital control switch arrays A ₁, A ₂a _n-1on off state, if the first digital control switch arrays A ₁, A ₂a _n-1conducting,

value be 0; If the first digital control switch arrays A ₁, A ₂a _n-1disconnect,

value be 1; B ₁, B ₂b _n-1be the second digital control switch arrays

on off state, if the second digital control switch arrays

conducting, B ₁, B ₂b _n-1value be 1; If the second digital control switch arrays disconnect, B ₁, B ₂b _n-1value be 0; And

and A ₁, A ₂a _n-1logic opposite signal, i.e. A each other ₁if conducting,

turn-off A ₁if turn-off,

conducting; V _crepresent the output common mode magnitude of voltage that design is desired.

Described variable load electric resistance array R _d1～R _dn-1by n-1 resistance, connected, by described the first digital control switch arrays A ₁～A _n-1control and make each corresponding resistance R _d1, R _d2, R _dn-1by short circuit or be access in load, thereby change the resistance value of load.

Described variable source class feedback resistance array R _s1～R _sn-1in parallel by n-1 resistance, wherein one end of each resistance is connected to the source electrode of described the first differential amplification pipe M1, and the other end of described each resistance is connected to the source electrode of described the second differential amplification pipe M2, switch arrays K ₁～K _n-1in K switch ₁with resistance R _s1series connection, K switch ₂with resistance R _s2series connection ..., K switch _n-1with resistance R _sn-1series connection, thereby by switch arrays K ₁～K _n-1in K switch ₁, K ₂, K _n-1disconnect and conducting, change the resistance value of access source electrode.

Operation principle of the present utility model is: as digital control switch arrays A ₁～A _n-1during whole conducting be 0) digital control switch arrays

for its logic opposite signal, digital control switch arrays

all disconnect (B ₁, B ₂b _n-1be 0), the effective resistance value that now accesses load is minimum value R _d0, the electric current I in variable current source array ₁～I _n-1access, does not flow through load resistance branch road R _d0electric current be maximum, its output common mode voltage:

V _C＝V _DD-[(I _SS-I ₀)×R _d0]

When passing through to select variable load electric resistance array R _d1～R _dn-1while changing gain, for example, make A ₁switch disconnects be 1), A ₂～A _n-1still conducting ( be 0),

conducting (B ₁be 1),

still disconnect (B ₂b _n-1be 0), resistance R now _d1in access load, R _d2～R _dn-1by short circuit, load effective resistance value is (R _d0+ R _d1) short circuit, the electric current I in variable current source array ₁access, flows through resistance (R _d0+ R _d1) electric current be (I _sS-I ₀-I ₁), its output common mode voltage is:

V _C1＝V _DD-[(I _SS-I ₀-I ₁)×（R _d0+R _d1)]

Design suitable current source I ₁with access resistance R _d1make it meet V _c1=V _c, that is:

(I _SS-I ₀-I ₁)×（R _d0+R _d1)＝(I _SS-I ₀)×R _d0

Output common mode voltage in this case equates with output common mode voltage before;

By that analogy, design suitable variable current source array I ₁～I _n-1, and variable load electric resistance array R _d1～R _dn-1resistance value, makes it to meet the following conditions:

$V_C=V_{\mathrm{DD}}-[I_{\mathrm{SS}}-I_0-B_1\·I_1-B_2\·I_2-\·\·\·-B_{n-1}\·I_{n-1})\×(R_{d0}+{\stackrel{\‾}{B}}_1\·R_{d1}+{\stackrel{\‾}{B}}_2\·R_{d2}+\·\·\·+{\stackrel{\‾}{B}}_{n-1}\·R_{\mathrm{dn}-1})]$

Can guarantee under different gains, it is stable that the output common mode voltage of VGA keeps.

By meeting above-mentioned relation formula, thereby can obtain the control situation of other gains, finally realize while changing gain by change load resistance, keep its output common mode constant.

Embodiment 2:

Based on above-mentioned amplifier circuit principle and working method, a utility model preferably more concrete preferred embodiment further illustrates implementation of the present utility model.

Shown in figure 3, as a more concrete preferred embodiment, a kind of low-power consumption variable gain amplifier without common mode feedback circuit of the utility model, gets n=2, variable load electric resistance array R _d1～R _dn-1comprise resistance R _d1, load resistance comprises resistance R _d0and resistance R _d1, described resistance R _d0comprise symmetrical two parts, be respectively resistance A_R _d0with resistance B_R _d0, and resistance R _d0resistance value=resistance A_R _d0resistance value=resistance B_R _d0resistance value, described resistance A_R _d0for resistance R 5, described resistance B_R _d0for resistance R 6, described resistance R _d1comprise symmetrical two parts, be respectively resistance A_R _d1with resistance B_R _d1, and resistance R _d1resistance value=resistance A_R _d1resistance value=resistance B_R _d1resistance value, described resistance A_R _d1for resistance R 7, described resistance B_R _d1for resistance R 8, described resistance R 7 and resistance R 5 series connection, the other end of resistance R 7 and supply voltage V _dDconnect, the other end of resistance R 5 is connected with the drain electrode of the first differential amplification pipe M1, described resistance R 8 and resistance R 6 series connection, resistance R 8 other ends and supply voltage V _dDconnect, resistance R 6 other ends are connected with the drain electrode of the second differential amplification pipe M2,

Described the first digital control switch arrays A ₁～A _n-1comprise digital control switch A ₁, described digital control switch A ₁by switching tube M13 and switching tube M14, formed, the source electrode of described switching tube M13, switching tube M14 respectively with supply voltage V _dDconnect, the grid of described switching tube M13, switching tube M14 is external digital controlled signal A respectively _d1, the drain electrode of described switching tube M13 is connected to the common connection end of resistance R 5 and resistance R 7, and the drain electrode of described switching tube M14 is connected to the common connection end of resistance R 6 and resistance R 8,

Described the second digital control switch arrays comprise digital control switch

described digital control switch

by switching tube M12 and COMS transmission gate, formed the source electrode of described switching tube M12 and supply voltage V _dDconnect, described switching tube M12 drain electrode is connected with the grid of electric current source capsule M11 with electric current source capsule M10 respectively, be connected with cmos transmission gate one end simultaneously, described COMS transmission gate consists of switching tube M19 and switching tube M20 parallel connection, described COMS transmission gate one end is connected with the grid of transistor M9, the other end is connected with drain electrode, electric current source capsule M10 and the grid of electric current source capsule M11 of switching tube M12, and the grid of described switching tube M12, COMS transmission gate switch pipe M20 is external digital controlled signal A all _d1, the external digital controlled signal A of grid of described COMS transmission gate switch pipe M19 _{d1_N}, digital controlled signal A _d1with digital controlled signal A _{d1_N}logic opposite signal each other,

Described variable current source array I ₁～I _n-1comprise current source I ₁, described current source I ₁comprise symmetrical two parts, be respectively electric current A_I ₁with electric current B_I ₁, and electric current I ₁current value=electric current A_I ₁current value=electric current B_I ₁current value, described electric current A_I ₁by electric current source capsule M10 and transistor M7, M8 and M9 mirror image reference current I _rEFform described electric current B_I ₁by electric current source capsule M11 and transistor M7, M8 and M9 mirror image reference current I _rEFform, the grid of described electric current source capsule M10 and electric current source capsule M11 is all connected with described COMS transmission gate one end, the source electrode of described electric current source capsule M10 and electric current source capsule M11 all with supply voltage V _dDconnect, the drain electrode of described electric current source capsule M10 and electric current source capsule M11 is connected with the drain electrode of electric current source capsule M4 with electric current source capsule M3 respectively,

Described fixed current source I ₀comprise that symmetrical two parts are respectively electric current A_I ₀with electric current B_I ₀, and electric current I ₀current value=electric current A_I ₀current value=electric current B_I ₀current value, described electric current A_I ₀by electric current source capsule M3 and transistor M7, M8 and M9 mirror image reference current I _rEFform described electric current B_I ₀by electric current source capsule M4 and transistor M7, M8 and M9 mirror image reference current I _rEFform, the source electrode of described electric current source capsule M3 and electric current source capsule M4 all with supply voltage V _dDconnect, the grid of described electric current source capsule M3 and electric current source capsule M4 is connected with drain electrode with the grid of electric current source capsule M9 by described cmos transmission gate,

The described variable gain amplifier output common mode voltage formula that meets the following conditions:

$V_C=V_{\mathrm{DD}}-[(I_{\mathrm{SS}}-I_0-B_1\·I_1)\×(R_{d0}+{\stackrel{\‾}{B}}_1\·R_{d1})]$

As digital controlled signal A _d1=0, A _{d1_N}=1 o'clock, switching tube M13 and switching tube M14 conducting, i.e. digital control switch A ₁conducting, resistance R 7 and resistance R 8 be by short circuit, i.e. variable load electric resistance array R _d1～R _dn-1in load R _d1by short circuit, now total load resistance is R _d0, the resistance value of the resistance value=resistance R 6 of total load resistance value=resistance R 5; Meanwhile, switching tube M12 conducting, cmos transmission gate disconnects, and the grid potential of electric current source capsule M10, electric current source capsule M11 is drawn high supply voltage V _dD, so electric current source capsule M10, electric current source capsule M11 disconnection, i.e. digital control switch

disconnect variable current source battle array A_I ₁and B_I ₁disconnect, and due to fixed current source A_I ₀and B_I ₀place in circuit, is respectively I so flow through the electric current of load resistance R5, resistance R 6 _ss-A_I ₀and I _ss-B_I ₀, and I _ss-A_I ₀=I _ss-B_I ₀;

Now, digital control switch A1 conducting,

digital control switch

disconnect, i.e. B ₁=0, be updated to above-mentioned conditional $V_C=V_{\mathrm{DD}}-[(I_{\mathrm{SS}}-I_0-B_1\·I_1)\×(R_{d0}+{\stackrel{\‾}{B}}_1\·R_{d1})]$ In obtain:

V _C＝V _DD-[(I _SS-I ₀)×(R _d0)]

As digital controlled signal A _d1=1, A _{d1_N}=0 o'clock, switching tube M13 and switching tube M14 disconnected, i.e. digital control switch A ₁disconnect, now variable load electric resistance array R _d1～R _dn-1in effective access resistance R _d1, total load resistance is resistance R _d1with resistance R _d0series connection, total load resistance value=resistance R 5 resistance values+resistance R 7 resistance values=resistance R 6 resistance values+resistance R 8 resistance values; Meanwhile, switching tube M12 disconnects, cmos transmission gate conducting, and the grid of electric current source capsule M10, electric current source capsule M11 is connected with the grid of transistor M9, forms current mirror, i.e. digital control switch conducting, variable current source array A_I ₁and B_I ₁access circuit, now flows through load resistance R _d1with resistance R _d0electric current be respectively as I _ss-A_I ₀-A_I ₁and I _ss-B_I ₀-B_I ₁, and have I _ss-A_I ₀-A_I ₁=I _ss-B_I ₀-B_I ₁;

Now, digital control switch A ₁disconnect,

digital control switch

conducting, i.e. B ₁=1, be updated to above-mentioned conditional $V_C=V_{\mathrm{DD}}-[(I_{\mathrm{SS}}-I_0-B_1\·I_1)\×(R_{d0}+{\stackrel{\‾}{B}}_1\·R_{d1})]$ In obtain:

V _C＝V _DD-[(I _SS-I ₀-I ₁)×(R _d0+R _d1)]

Thereby V _dD-[(I _sS-I ₀-I ₁) * (R _d0+ R _d1)]=V _dD-[(I _sS-I ₀) * (R _d0)]=V _c, by current source I reasonable in design ₁and resistance R _d1value, guarantee that variable gain amplifier output common mode voltage keeps constant.

In the present embodiment, according to specific implementation technique, and supply voltage V _dD, design suitable fixed current source I _sS, I ₀with fixed resistance R _d0obtain V _c=V _dD-[(I _sS-I ₀) * (R _d0)], when circuit design, according to the compromise consideration of the requirement of bandwidth, power consumption and the linearity, the key design parameter of circuit is supply voltage V _dD=3V, R ₅=R ₇=50K Ω, I _sS=50 μ A, I ₀=20 μ A, I ₁=15 μ A, and the L value of electric current source capsule M3 (M4), M10 (M11) and M5 (M6) is got larger value (L=8 μ m) $V_C=3-(50-20)*50=3-1.5=1.5=\frac{1}{2}{V}_{\mathrm{DD}}.$ Therefore under above-mentioned parameter, the equivalent output impedance of current source M3, M10 pipe is far longer than R5+R7, can ignore their impacts on output loading RD, the impact of the equivalent output impedance that in like manner also can ignore M5 pipe on source feedback resistance R S.Simulation results shows, while switching between amplifier different gains, its output common mode change in voltage scope is less than 10mV, so this circuit can be stablized output common mode voltage preferably, save extra common mode feedback circuit, reduced complexity and the power consumption of circuit.

By the design to circuit parameter, can realize equating of both output common modes.Compare with existing gain-changeable amplifier circuit, the utility model circuit has saved common mode feedback circuit when keeping stablizing output common mode voltage, has reduced complexity and the overall power of circuit design.

Although specifically show and introduced the utility model in conjunction with preferred embodiment; but those skilled in the art should be understood that; within not departing from the spirit and scope of the present utility model that appended claims limits; can make a variety of changes the utility model in the form and details, be protection range of the present utility model.

Claims (4)

1. a low-power consumption variable gain amplifier, is characterized in that: comprise difference common source amplifying unit, variable load electric resistance array R _d1～R _dn-1, the first digital control switch arrays A ₁～A _n-1, the second digital control switch arrays

variable current source array I ₁～I _n-1, variable source class feedback resistance array R _s1～R _sn-1, switch arrays K ₁～K _n-1, fixed current source I ₀and I _sS, fixed resistance R _d0and R _s0,

Described difference common source amplifying unit, comprises the first differential amplification pipe M1 and the second differential amplification pipe M2 in parallel, for receiving and amplified difference signal,

Described variable load electric resistance array R _d1～R _dn-1with fixed resistance R _d0after series connection, be connected to supply voltage V _dDand between the drain electrode of difference common source amplifying unit, variable load electric resistance array R _d1～R _dn-1in effective access resistance value by the first digital control switch arrays A ₁～A _n-1institute controls,

Described variable current source array I ₁～I _n-1, be connected to supply voltage V _dDand between the drain electrode of difference common source amplifying unit, this variable current source array I ₁～I _n-1current source by the second digital control switch arrays

institute controls, the second digital control switch arrays

with the first digital control switch arrays A ₁～A _n-1on off state is contrary, even switch A ₁conducting, switch

disconnect; If switch A ₁disconnect, switch

conducting,

Described variable source class feedback resistance array R _s1～R _sn-1with fixed resistance R _s0after parallel connection, be connected between the source electrode of the first differential amplification pipe M1 and the source electrode of the second differential amplification pipe M2 variable source class feedback resistance array R _s1～R _sn-1in effective access resistance value by switch arrays K ₁～K _n-1institute controls,

Described fixed current source I ₀be connected to supply voltage V _dDand between the drain electrode of difference common source amplifying unit,

Described fixed current source I _sSbe connected between the source electrode and earthed voltage of difference common source amplifying unit.

2. a kind of low-power consumption variable gain amplifier according to claim 1, is characterized in that: described variable load electric resistance array R _d1～R _dn-1by n-1 resistance, connected, by described the first digital control switch arrays A ₁～A _n-1control and make each corresponding resistance R _d1, R _d2, R _dn-1by short circuit or be access in load, thereby change the resistance value of load.

3. a kind of low-power consumption variable gain amplifier according to claim 2, is characterized in that: described variable source class feedback resistance array R _s1～R _sn-1in parallel by n-1 resistance, wherein one end of each resistance is connected to the source electrode of described the first differential amplification pipe M1, and the other end of described each resistance is connected to the source electrode of described the second differential amplification pipe M2, switch arrays K ₁～K _n-1in K switch ₁with resistance R _s1series connection, K switch ₂with resistance R _s2series connection ..., K switch _n-1with resistance R _sn-1series connection, thereby by switch arrays K ₁～K _n-1in K switch ₁, K ₂, K _n-1disconnect and conducting, change the resistance value of access source electrode.

4. a kind of low-power consumption variable gain amplifier according to claim 3, is characterized in that: get n=2, variable load electric resistance array R _d1～R _dn-1comprise resistance R _d1, load resistance comprises resistance R _d0and resistance R _d1, described resistance R _d0comprise symmetrical two parts, be respectively resistance A_R _d0with resistance B_R _d0, and resistance R _d0resistance value=resistance A_R _d0resistance value=resistance B_R _d0resistance value, described resistance A_R _d0for resistance R 5, described resistance B_R _d0for resistance R 6, described resistance R _d1comprise symmetrical two parts, be respectively resistance A_R _d1with resistance B_R _d1, and resistance R _d1resistance value=resistance A_R _d1resistance value=resistance B_R _d1resistance value, described resistance A_R _d1for resistance R 7, described resistance B_R _d1for resistance R 8, described resistance R 7 and resistance R 5 series connection, the other end of resistance R 7 and supply voltage V _dDconnect, the other end of resistance R 5 is connected with the drain electrode of the first differential amplification pipe M1, described resistance R 8 and resistance R 6 series connection, resistance R 8 other ends and supply voltage V _dDconnect, resistance R 6 other ends are connected with the drain electrode of the second differential amplification pipe M2,

Described the first digital control switch arrays A ₁～A _n-1comprise digital control switch A ₁, described digital control switch A ₁by switching tube M13 and switching tube M14, formed, the source electrode of described switching tube M13, switching tube M14 respectively with supply voltage V _dDconnect, the grid of described switching tube M13, switching tube M14 is external digital controlled signal A respectively _d1, the drain electrode of described switching tube M13 is connected to the common connection end of resistance R 5 and resistance R 7, and the drain electrode of described switching tube M14 is connected to the common connection end of resistance R 6 and resistance R 8,

Described the second digital control switch arrays

comprise digital control switch

described digital control switch by switching tube M12 and COMS transmission gate, formed the source electrode of described switching tube M12 and supply voltage V _dDconnect, described switching tube M12 drain electrode is connected with the grid of electric current source capsule M11 with electric current source capsule M10 respectively, be connected with cmos transmission gate one end simultaneously, described COMS transmission gate consists of switching tube M19 and switching tube M20 parallel connection, described COMS transmission gate one end is connected with the grid of transistor M9, the other end is connected with drain electrode, electric current source capsule M10 and the grid of electric current source capsule M11 of switching tube M12, and the grid of described switching tube M12, COMS transmission gate switch pipe M20 is external digital controlled signal A all _d1, the external digital controlled signal A of grid of described COMS transmission gate switch pipe M19 _{d1_N}, digital controlled signal A _d1with digital controlled signal A _{d1_N}logic opposite signal each other,

Described variable current source array I ₁～I _n-1comprise current source I ₁, described current source I ₁comprise symmetrical two parts, be respectively electric current A_I ₁with electric current B_I ₁, and electric current I ₁current value=electric current A_I ₁current value=electric current B_I ₁current value, described electric current A_I ₁by electric current source capsule M10 and transistor M7, M8 and M9 mirror image reference current I _rEFform described electric current B_I ₁by electric current source capsule M11 and transistor M7, M8 and M9 mirror image reference current I _rEFform, the grid of described electric current source capsule M10 and electric current source capsule M11 is all connected with described COMS transmission gate one end, the source electrode of described electric current source capsule M10 and electric current source capsule M11 all with supply voltage V _dDconnect, the drain electrode of described electric current source capsule M10 and electric current source capsule M11 is connected with the drain electrode of electric current source capsule M4 with electric current source capsule M3 respectively,

Described fixed current source I ₀comprise that symmetrical two parts are respectively electric current A_I ₀with electric current B_I ₀, and electric current I ₀current value=electric current A_I ₀current value=electric current B_I ₀current value, described electric current A_I ₀by electric current source capsule M3 and transistor M7, M8 and M9 mirror image reference current I _rEFform described electric current B_I ₀by electric current source capsule M4 and transistor M7, M8 and M9 mirror image reference current I _rEFform, the source electrode of described electric current source capsule M3 and electric current source capsule M4 all with supply voltage V _dDconnect, the grid of described electric current source capsule M3 and electric current source capsule M4 is connected with drain electrode with the grid of electric current source capsule M9 by described cmos transmission gate.

Images