CN103107791B - Gain linear variable gain amplifier with constant bandwidth - Google Patents
Gain linear variable gain amplifier with constant bandwidth Download PDFInfo
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- CN103107791B CN103107791B CN201210590866.3A CN201210590866A CN103107791B CN 103107791 B CN103107791 B CN 103107791B CN 201210590866 A CN201210590866 A CN 201210590866A CN 103107791 B CN103107791 B CN 103107791B
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Abstract
The invention discloses a gain linear variable gain amplifier with a constant bandwidth. The gain linear variable gain amplifier with the constant bandwidth comprises a common source class amplifier and a gain regulating network. The common source class amplifier comprises a first N type metallic oxide transistor, a fifth N type metallic oxide transistor, a first P type metallic oxide transistor, a second P type metallic oxide transistor and a first current source. The gain regulating network comprises N type metallic oxide transistors ranging from a second N type metallic oxide transistor to an eighth N type metallic oxide transistor, current sources ranging from a second current source to a tenth current source and switches ranging from a first switch to a fifteenth switch. The gain linear variable gain amplifier with the constant bandwidth has the advantage of being stable in bandwidth and meanwhile is capable of enabling the gain to achieve accurate linear effect through different control words.
Description
Technical field
The present invention relates to a kind of amplifier, specifically, relate to the gain linear variable gain amplifier that a kind of bandwidth is constant.
Background technology
In rf signal reception link, the effect of variable gain amplifier ensures the constant of output signal in the scope that input signal changes.Consider from whole receiver, amplifier should have the higher linearity.In addition, variable gain amplifier, as one of the major part of ifd module, should have good bandwidth to ensure stable transfer and the non-band signal of more effective suppression of signal.
Variable gain amplifier can be divided into analog signal to control variable gain amplifier and Digital Signals variable gain amplifier according to the difference of control signal.Analogue enlargement variable gain amplifier needs independent structural index voltage generation circuit, and CMOS is comparatively difficult under realizing.The dB that digital control variable gain amplifier realizes gain by control figure coded system is linear.Control variable gain amplifier compared to analog signal, Digital Signals variable gain amplifier does not need independent structural index voltage generation circuit, and in discrete point optimized gain value, can improve gain accuracy, is conducive to low-power consumption simultaneously yet.Therefore, digital variable gain amplifier more and more becomes the main way in radio frequency reception link.
Digital variable gain amplifier is mainly divided into open loop structure and closed-loop structure.Both is all the dB linear relationship being realized gain and digital signal by Digital Signals switch.Closed-loop structure realizes gain-variable by changing feedback network thus changing feedback factor, and its gain accuracy is high, but there is the shortcomings such as bandwidth is less, power consumption is larger; Open loop structure realizes gain-variable mainly through change equivalent transconductance or output impedance, and generally its gain control range is comparatively large, and broader bandwidth, power consumption is lower, but gain accuracy is poor.Common open loop structure has a lot, and based on the variable gain amplifier of programmable load, although can realize gain dB linear change, the bandwidth of amplifier can reduce along with the increase of gain.Based on the variable gain amplifier of diode load differential pair, changed the gain of amplifier by the mutual conductance changing input pipe and load pipe, be faced with the problem of bandwidth change equally.
Simultaneously, the general variable gain amplifier based on programmable trans-conductance is by simply changing the size of input pipe or changing the mutual conductance that bias current changes input pipe, when single varying sized or electric current, the overdrive voltage of input pipe changes, transistor drain-source voltage as bias current sources is changed, thus makes with the current source error change of current mirror manner generation larger.
Summary of the invention
Goal of the invention: for above-mentioned prior art Problems existing and deficiency, the object of this invention is to provide the gain linear variable gain amplifier that a kind of bandwidth is constant, the amplifier of this structure has the constant feature of bandwidth, simultaneously by conducting and the disconnection of control word control switch, gain can be made to reach accurate linear relationship.
Technical scheme: for achieving the above object, the technical solution used in the present invention is the gain linear variable gain amplifier that a kind of bandwidth is constant, and this variable gain amplifier comprises common-source stage amplifier and gain-adjusted network; Wherein:
Common-source stage amplifier comprises the first N-type MOS transistor, the 5th N-type MOS transistor, a P type MOS transistor, the 2nd P type MOS transistor and the first current source;
Gain-adjusted network comprises the second N-type MOS transistor, 3rd N-type MOS transistor, 4th N-type MOS transistor, 6th N-type MOS transistor, 7th N-type MOS transistor, 8th N-type MOS transistor, second current source, 3rd current source, 4th current source, 5th current source, 6th current source, 7th current source, 8th current source, 9th current source, tenth current source, first switch, second switch, 3rd switch, 4th switch, 5th switch, 6th switch, 7th switch, 8th switch, 9th switch, tenth switch, 11 switch, twelvemo is closed, 13 switch, 14 switch and the 15 switch,
Input signal anode is connected with the grid of the first N-type MOS transistor, the second N-type MOS transistor, the 3rd N-type MOS transistor and the 4th N-type MOS transistor; The drain electrode of the first N-type MOS transistor is connected with the drain electrode of a P type MOS transistor, and the drain electrode of a P type MOS transistor is connected with grid, and the source electrode of a P type MOS transistor connects supply voltage; The source electrode of the source electrode of the source electrode of the source electrode of the first N-type MOS transistor and the source electrode of the second N-type MOS transistor, the 3rd N-type MOS transistor, the source electrode of the 4th N-type MOS transistor, the 5th N-type MOS transistor, the source electrode of the 6th N-type MOS transistor, the source electrode of the 7th N-type MOS transistor and the 8th N-type MOS transistor is connected, and is connected with one end of the first current source, the first switch, second switch and the 3rd switch simultaneously; The other end of the first switch is connected with one end of the second current source, and the other end of second switch is connected with one end of the 3rd current source, and the other end of the 3rd switch is connected with one end of the 4th current source; The other end ground connection of the first current source, the second current source, the 3rd current source and the 4th current source; One end of 4th switch is connected with the drain electrode of the second N-type MOS transistor, and one end of the 5th switch is connected with the drain electrode of the 3rd N-type MOS transistor, and one end of the 6th switch is connected with the drain electrode of the 4th N-type MOS transistor; 4th switch, the 5th switch are connected with the drain electrode of the first N-type MOS transistor with the other end of the 6th switch, are connected, as the anode of amplifier output signal with one end that the tenth switch, the 11 switch and twelvemo are closed simultaneously; The other end of the tenth switch is connected with one end of the 7th current source, and the other end of the 11 switch is connected with one end of the 6th current source, and the other end that twelvemo is closed is connected with one end of the 5th current source; Another termination supply voltage of 5th current source, the 6th current source and the 7th current source; Input signal negative terminal is connected with the grid of the 5th N-type MOS transistor, the 6th N-type MOS transistor, the 7th N-type MOS transistor and the 8th N-type MOS transistor; The drain electrode of the 5th N-type MOS transistor is connected with the drain electrode of the 2nd P type MOS transistor, and the drain electrode of the 2nd P type MOS transistor is connected with grid, and the source electrode of the 2nd P type MOS transistor connects supply voltage; One end of 7th switch is connected with the drain electrode of the 6th N-type MOS transistor, and one end of the 8th switch is connected with the drain electrode of the 7th N-type MOS transistor, and one end of the 9th switch is connected with the drain electrode of the 8th N-type MOS transistor; 7th switch, the 8th switch are connected with the drain electrode of the 5th N-type MOS transistor with the other end of the 9th switch, are connected, as the negative terminal of amplifier output signal with one end of the 13 switch, the 14 switch and the 15 switch simultaneously; The other end of the 13 switch is connected with one end of the 8th current source, and the other end of the 14 switch is connected with one end of the 9th current source, and the other end of the 15 switch is connected with one end of the tenth current source; Another termination supply voltage of 8th current source, the 9th current source and the tenth current source.
Beneficial effect: compared with prior art, the present invention has following beneficial effect:
1. bandwidth is constant.Variable gain amplifier of the present invention is in the afterbody of receiver system analog signal link, and the input signal of amplifier is operated in low frequency state.Variable gain amplifier of the present invention, the impact that bandwidth is subject to change in gain is very little, substantially remains unchanged, like this can signal beyond better filtering bandwidth.The variable gain amplifier that bandwidth of the present invention is constant makes a P type MOS transistor and the 2nd P type MOS transistor be connected using diode fashion and as the load of two differential circuits, control current source in parallel make the electric current flowing through a P type MOS transistor and the 2nd P type MOS transistor not ensure that its impedance is constant by switch control word.The impedance of the one P type MOS transistor and the 2nd P type MOS transistor is less, then the output impedance of amplifier determines primarily of the impedance of these two transistors, these two transistors output grid source electric capacity are larger simultaneously, and the gate leakage capacitance of other transistors is very little on output node, output capacitance size is main also to be determined by these two transistors, thus ensure that bandwidth change is very little, substantially keep constant.
2. gain linearity relation is accurate.In whole receiver system, variable gain amplifier is in back segment, and therefore, the linearity height of amplifier directly has influence on the performance of whole receiver.Variable gain amplifier of the present invention achieves digital control word and the accurate linear relationship of gain.While the breadth length ratio of variable gain amplifier of the present invention by switch control word the first N-type MOS transistor and the 5th N-type MOS transistor in control common-source amplifier, change corresponding bias current size, make the mutual conductance of amplifier input pipe and control word linear.Ensure that the overdrive voltage of input pipe is constant, the current source transistor drain-source voltage that current mirror is produced is constant simultaneously, thus makes the error of current source less.Because output impedance remains unchanged substantially, by arranging different control word sizes, make the size of gain and control word linear, the step-length of simultaneously gain is fixed, and improves gain accuracy and the linearity.
Accompanying drawing explanation
Fig. 1 is circuit diagram of the present invention;
Fig. 2 is amplitude-frequency characteristic oscillogram of the present invention;
Fig. 3 is the gain contrast figure of the present invention and traditional structure.
Embodiment
Below in conjunction with the drawings and specific embodiments, illustrate the present invention further, these embodiments should be understood only be not used in for illustration of the present invention and limit the scope of the invention, after having read the present invention, the amendment of those skilled in the art to the various equivalent form of value of the present invention has all fallen within the application's claims limited range.
As shown in Figure 1, the gain linear variable gain amplifier that a kind of bandwidth of the present invention is constant, comprises common-source stage amplifier and gain-adjusted network, wherein, common-source stage amplifier comprises the first N-type MOS transistor N1, the 5th N-type MOS transistor N5, a P type MOS transistor P1, the 2nd P type MOS transistor P2 and the first current source I1, gain-adjusted network comprises the second N-type MOS transistor N2, 3rd N-type MOS transistor N3, 4th N-type MOS transistor N4, 6th N-type MOS transistor N6, 7th N-type MOS transistor N7, 8th N-type MOS transistor N8, second current source I2, 3rd current source I3, 4th current source I4, 5th current source I5, 6th current source I6, 7th current source I7, 8th current source I8, 9th current source I9, tenth current source I10, first switch S 1, second switch S2, 3rd switch S 3, 4th switch S 4, 5th switch S 5, 6th switch S 6, 7th switch S 7, 8th switch S 8, 9th switch S 9, tenth switch S 10, 11 switch S 11, twelvemo closes S12, 13 switch S 13, 14 switch S the 14 and the 15 switch S 15.
The grid of input signal anode VIN+ and the first N-type MOS transistor N1, the second N-type MOS transistor N2, the 3rd N-type MOS transistor N3 and the 4th N-type MOS transistor N4 is connected; The drain electrode of the first N-type MOS transistor N1 is connected with the drain electrode of a P type MOS transistor P1, and the drain electrode of a P type MOS transistor P1 is connected with grid, and the source electrode of a P type MOS transistor P1 connects supply voltage; The source electrode of the source electrode of the source electrode of the source electrode of the first N-type MOS transistor N1 and the source electrode of the second N-type MOS transistor N2, the 3rd N-type MOS transistor N3, the source electrode of the 4th N-type MOS transistor N4, the 5th N-type MOS transistor N5, the source electrode of the 6th N-type MOS transistor N6, the source electrode of the 7th N-type MOS transistor N7 and the 8th N-type MOS transistor N8 is connected, and is connected with one end of the first current source I1, the first switch S 1, second switch S2 and the 3rd switch S 3 simultaneously; The other end of the first switch S 1 is connected with one end of the second current source I2, and the other end of second switch S2 is connected with one end of the 3rd current source I3, and the other end of the 3rd switch S 3 is connected with one end of the 4th current source I4; The other end ground connection of the first current source I1, the second current source I2, the 3rd current source I3 and the 4th current source I4; One end of 4th switch S 4 is connected with the drain electrode of the second N-type MOS transistor N2, one end of 5th switch S 5 is connected with the drain electrode of the 3rd N-type MOS transistor N3, and one end of the 6th switch S 6 is connected with the drain electrode of the 4th N-type MOS transistor N4; 4th switch S 4, the 5th switch S 5 are connected with the drain electrode of the first N-type MOS transistor N1 with the other end of the 6th switch S 6, the one end of simultaneously closing S12 with the tenth switch S the 10, the 11 switch S 11 and twelvemo is connected, as the anode VOUT+ of amplifier output signal; The other end of the tenth switch S 10 is connected with one end of the 7th current source I7, and the other end of the 11 switch S 11 is connected with one end of the 6th current source I6, and the other end that twelvemo closes S12 is connected with one end of the 5th current source I5; Another termination supply voltage of 5th current source I5, the 6th current source I6 and the 7th current source I7; The grid of input signal negative terminal VIN-and the 5th N-type MOS transistor N5, the 6th N-type MOS transistor N6, the 7th N-type MOS transistor N7 and the 8th N-type MOS transistor N8 is connected; The drain electrode of the 5th N-type MOS transistor N5 is connected with the drain electrode of the 2nd P type MOS transistor P2, and the drain electrode of the 2nd P type MOS transistor P2 is connected with grid, and the source electrode of the 2nd P type MOS transistor P2 connects supply voltage; One end of 7th switch S 7 is connected with the drain electrode of the 6th N-type MOS transistor N6, one end of 8th switch S 8 is connected with the drain electrode of the 7th N-type MOS transistor N7, and one end of the 9th switch S 9 is connected with the drain electrode of the 8th N-type MOS transistor N8; 7th switch S 7, the 8th switch S 8 are connected with the drain electrode of the 5th N-type MOS transistor N5 with the other end of the 9th switch S 9, be connected, as the negative terminal VOUT-of amplifier output signal with one end of the 13 switch S the 13, the 14 switch S the 14 and the 15 switch S 15 simultaneously; The other end of the 13 switch S 13 is connected with one end of the 8th current source I8, and the other end of the 14 switch S 14 is connected with one end of the 9th current source I9, and the other end of the 15 switch S 15 is connected with one end of the tenth current source I10; Another termination supply voltage of 8th current source I8, the 9th current source I9 and the tenth current source I10.
The gain linear variable gain amplifier that above-mentioned bandwidth is constant, the electric current making to flow through a P type MOS transistor P1 and the 2nd P type MOS transistor P2 by the current source of switch control rule parallel connection is constant ensures that its impedance is constant.The impedance of the one P type MOS transistor P1 and the 2nd P type MOS transistor P2 is less, the output impedance of amplifier determines primarily of these two Transistor Impedance, these two transistors output grid source electric capacity are larger simultaneously, and the gate leakage capacitance of other transistors is very little on output node, output capacitance size is main also to be determined by these two transistors, thus ensure that bandwidth change is very little, substantially keep constant.While the breadth length ratio of gain control network of the present invention by switch control word the first N-type MOS transistor and the 5th N-type MOS transistor in control common-source amplifier, change corresponding bias current size, make the mutual conductance of amplifier input pipe and control word linear.Because output impedance remains unchanged substantially, by arranging different control word sizes, make the size of gain and control word linear, the step-length of simultaneously gain is fixed.
First switch S 1, the 4th switch S 4, the 7th switch S 7, the tenth switch S the 10 and the 13 switch S 13 control by a control word A1, second switch S2, the 5th switch S 5, the 8th switch S the 8, the 11 switch S the 11 and the 14 switch S 14 are controlled by a control word A2,3rd switch S 3, the 6th switch S 6, the 9th switch S 9, twelvemo close S12 and the 15 switch S 15 is controlled by a control word A3, and control word signal A3A2A1 is provided by the digital module in whole automatic gain control loop.First current source I1, the second current source I2, the 6th current source I6 are equal with the 9th current source I9 electric current, 7th current source I7 is equal with the 8th current source I8 size of current and equal the half of the first current source I1 electric current, 3rd current source I3, the 5th current source I5 are equal with the tenth current source I10 size of current and equal the twice of the first current source I1 electric current, and the 4th current source I4 size of current equals four times of the first current source I1 electric current.The breadth length ratio of the first N-type MOS transistor N1 and the 5th N-type MOS transistor N5 is equal, the breadth length ratio of the second N-type MOS transistor N2 and the 6th N-type MOS transistor N6 is equal and equal the breadth length ratio of the first N-type MOS transistor N1, the breadth length ratio of the 3rd N-type MOS transistor N3 and the 7th N-type MOS transistor N7 is equal and equal the twice of the first N-type MOS transistor N1 breadth length ratio, the breadth length ratio of the 4th N-type MOS transistor N4 and the 8th N-type MOS transistor N8 is equal and equal four times of the first N-type MOS transistor N1 breadth length ratio.Low frequency difference signal is added in anode VIN+ and negative terminal VIN-respectively, when the first to the 15 switch S 1-S15 all disconnects, voltage small-signal converts Small Current Signal to respectively by the first N-type MOS transistor N1 and the 5th N-type MOS transistor N5, first current source I1 provides current offset for common-source amplifier, one P type MOS transistor P1 is connected with diode fashion, as the load of difference branch road respectively with the 2nd P type MOS transistor P2.The drain electrode of the first N-type MOS transistor N1 and the 5th N-type MOS transistor N5 is respectively as the positive output end VOUT+ of amplifier and negative output terminal VOUT-.When control word A3A2A1 is 01, namely the first switch S 1, the 4th switch S 4, the 7th switch S 7, the tenth switch S the 10 and the 13 switch S 13 close, the electric current of the second current source I2 is shunted by the 7th current source I7 and the 8th current source I8, the electric current flowing through a P type MOS transistor P1 and the 2nd P type MOS transistor P2 remains unchanged, these two Transistor Impedance are equivalent to the inverse of mutual conductance, therefore impedance is constant and less.Meanwhile, the electric current of the 7th current source I7 flows through the second N-type MOS transistor N2 entirely, and the electric current of the 8th current source I8 flows through the 6th N-type MOS transistor N6 entirely.The impedance of entering viewed from output determines primarily of the equiva lent impedance of a P type MOS transistor P1 and the 2nd P type MOS transistor P2, and namely output impedance remains unchanged substantially.Output node place, the parasitic capacitance of the one P type MOS transistor P1 and the 2nd P type MOS transistor P2 mainly grid source electric capacity and larger, and introduce other transistors work is gate leakage capacitance, the transistor gate drain capacitance being operated in saturation region is very little, almost do not have, therefore output node place equivalent capacity is determined by a P type MOS transistor P1 and the 2nd P type MOS transistor P2 and constant, therefore bandwidth does not change, and keeps constant.Second current source I2 electric current only flows through the second N-type MOS transistor N2 and the 6th N-type MOS transistor N6, for it provides current offset, first switch S 1, the 4th switch S 4 and the 7th switch S 7 close simultaneously, make the breadth length ratio of the second N-type MOS transistor N2 change identical multiple with bias current respectively relative to the first N-type MOS transistor N1, then the mutual conductance of the second N-type MOS transistor N2 is the identical multiple of the first N-type MOS transistor N1 mutual conductance.Simultaneously, the breadth length ratio of the 6th N-type MOS transistor N6 changes identical multiple with bias current respectively relative to the 5th N-type MOS transistor N5, then the mutual conductance of the 6th N-type MOS transistor N6 is the identical multiple of the 5th N-type MOS transistor N5 mutual conductance.Guarantee first N-type MOS transistor N1 identical with the mutual conductance of the 5th N-type MOS transistor N5 and constant time, the size of multiple is depended in the mutual conductance of whole common-source amplifier equivalent inpnt, because output impedance size is constant, the size of multiple is depended in amplifier gain.
When control word A3A2A1 is 011, namely outside the first switch S 1, the 4th switch S 4, the 7th switch S 7, the tenth switch S the 10 and the 13 switch S 13 close, second switch S2, the 5th switch S 5, the 8th switch S the 8, the 11 switch S the 11 and the 14 switch S 14 also close simultaneously, the grid source capacitive effect of the transistor gate drain capacitance now introduced to an original P type MOS transistor P1 and the 2nd P type MOS transistor P2 is very little, and output capacitance remains unchanged; The electric current of the 3rd current source I3 is shunted by the 6th current source I6 and the 9th current source I9, ensure a P type MOS transistor P1 and the 2nd P type MOS transistor P2 electric current constant, the equiva lent impedance of its correspondence is also constant.Because other transistor drain-source resistances introduced are very large, output loading determines primarily of a P type MOS transistor P1 and the 2nd P type MOS transistor P2, therefore output impedance remains unchanged, and bandwidth also remains unchanged.Under this control word, the electric current of the 6th current source I6 flows through the 3rd N-type MOS transistor N3 entirely, and the electric current of the 9th current source I9 flows through the 7th N-type MOS transistor N7 entirely.3rd current source I3 electric current only flows through the 3rd N-type MOS transistor N3 and the 7th N-type MOS transistor N7, for it provides current offset, second switch S2, the 5th switch S 5 and the 8th switch S 8 close simultaneously, make the breadth length ratio of the 3rd N-type MOS transistor N3 change identical multiple with bias current respectively relative to the first N-type MOS transistor N1, then the mutual conductance of the 3rd N-type MOS transistor N3 is the identical multiple of the first N-type MOS transistor N1 mutual conductance.Simultaneously, the breadth length ratio of the 7th N-type MOS transistor N7 changes identical multiple with bias current respectively relative to the 5th N-type MOS transistor N5, then the mutual conductance of the 7th N-type MOS transistor N7 is the identical multiple of the 5th N-type MOS transistor N5 mutual conductance.Guarantee first N-type MOS transistor N1 identical with the mutual conductance of the 5th N-type MOS transistor N5 and constant time, total multiple and size are depended in the mutual conductance of whole common-source amplifier equivalent inpnt.
When control word A3A2A1 is 111, namely all switches close simultaneously, and now in the highest flight, output capacitance remains unchanged the grid source electric capacity of a P type MOS transistor P1 and the 2nd P type MOS transistor P2 substantially; The electric current of the 4th current source I4 is shunted by the 5th current source I5 and the tenth current source I10, ensure a P type MOS transistor P1 and the 2nd P type MOS transistor P2 electric current constant, the equiva lent impedance of its correspondence is also constant.Because other transistor drain-source resistances introduced are very large, output loading determines primarily of a P type MOS transistor P1 and the 2nd P type MOS transistor P2, therefore output impedance remains unchanged, and bandwidth also remains unchanged.Under this control word, the electric current of the 5th current source I5 flows through the 4th N-type MOS transistor N4 entirely, and the electric current of the tenth current source I10 flows through the 8th N-type MOS transistor N8 entirely.4th current source I4 electric current only flows through the 4th N-type MOS transistor N4 and the 8th N-type MOS transistor N8, for it provides current offset, 3rd switch S 3, the 6th switch S 6 and the 9th switch S 9 close simultaneously, make the breadth length ratio of the 4th N-type MOS transistor N4 change identical multiple with bias current respectively relative to the first N-type MOS transistor N1, then the mutual conductance of the 4th N-type MOS transistor N4 is the identical multiple of the first N-type MOS transistor N1 mutual conductance.Simultaneously, the breadth length ratio of the 8th N-type MOS transistor N8 changes identical multiple with bias current respectively relative to the 5th N-type MOS transistor N5, then the mutual conductance of the 8th N-type MOS transistor N8 is the identical multiple of the 5th N-type MOS transistor N5 mutual conductance.Guarantee first N-type MOS transistor N1 identical with the mutual conductance of the 5th N-type MOS transistor N5 and constant time, total multiple and size are depended in whole common-source amplifier input mutual conductance.The change of control word, directly makes whole amplifier input pipe equivalent transconductance change at double.By arranging fixing electric current multiple and input pipe size multiple, amplifier gain can be made to become accurate linear relationship with control word, and gain step size is fixed.
Illustrate that the present invention has the advantage of the constant and gain linearity of bandwidth below by simulation comparison.
Virtuoso simulation software is adopted to carry out the amplitude-frequency characteristic emulation of variable gain amplifier.Use this technology to contrast traditional technology reaching gain-variable by changing mutual conductance simultaneously.
As shown in Figure 2, abscissa represents the frequency of input signal to amplitude-frequency characteristic result, unit Hz, and ordinate represents gain, unit dB.As can be seen from Figure 2, bandwidth of the present invention is substantially constant near 170MHz.This technology and traditional reach the technology comparing result of gain-variable as shown in Figure 3 by changing mutual conductance, the variable gain amplifier that the present invention proposes has accurate gain linearity relation, and gain step size is 6dB.
To sum up, in the present invention, using the transistor of diode connected mode as load, make the break-make of switch change very little to the equiva lent impedance of output node and capacitive reactance, thus ensure that bandwidth is constant.The present invention adopts and changes input pipe size and bias current simultaneously, make the overdrive voltage of input pipe constant, ensure that the current source drain-source voltage that current mirror produces is constant, the dB linear relationship basis therefore realizing gain at common Digital Signals switch further increases gain accuracy.
Claims (1)
1. the gain linear variable gain amplifier that bandwidth is constant, is characterized in that: this variable gain amplifier comprises common-source stage amplifier and gain-adjusted network; Wherein:
Common-source stage amplifier comprises the first N-type MOS transistor (N1), the 5th N-type MOS transistor (N5), a P type MOS transistor (P1), the 2nd P type MOS transistor (P2) and the first current source (I1);
Gain-adjusted network comprises the second N-type MOS transistor (N2), 3rd N-type MOS transistor (N3), 4th N-type MOS transistor (N4), 6th N-type MOS transistor (N6), 7th N-type MOS transistor (N7), 8th N-type MOS transistor (N8), second current source (I2), 3rd current source (I3), 4th current source (I4), 5th current source (I5), 6th current source (I6), 7th current source (I7), 8th current source (I8), 9th current source (I9), tenth current source (I10), first switch (S1), second switch (S2), 3rd switch (S3), 4th switch (S4), 5th switch (S5), 6th switch (S6), 7th switch (S7), 8th switch (S8), 9th switch (S9), tenth switch (S10), 11 switch (S11), twelvemo closes (S12), 13 switch (S13), 14 switch (S14) and the 15 switch (S15),
Input signal anode (VIN+) is connected with the grid of the first N-type MOS transistor (N1), the second N-type MOS transistor (N2), the 3rd N-type MOS transistor (N3) and the 4th N-type MOS transistor (N4), the drain electrode of the one P type MOS transistor (P1) is connected with grid, and the source electrode of a P type MOS transistor (P1) connects supply voltage, the source electrode of the first N-type MOS transistor (N1) and the source electrode of the second N-type MOS transistor (N2), the source electrode of the 3rd N-type MOS transistor (N3), the source electrode of the 4th N-type MOS transistor (N4), the source electrode of the 5th N-type MOS transistor (N5), the source electrode of the 6th N-type MOS transistor (N6), the source electrode of the 7th N-type MOS transistor (N7) is connected with the source electrode of the 8th N-type MOS transistor (N8) and forms one article of main line, be divided into four branch roads afterwards, respectively with the first current source (I1), first switch (S1), second switch (S2) is connected with one end of the 3rd switch (S3), the other end of the first switch (S1) is connected with one end of the second current source (I2), the other end of second switch (S2) is connected with one end of the 3rd current source (I3), and the other end of the 3rd switch (S3) is connected with one end of the 4th current source (I4), the other end ground connection of the first current source (I1), the second current source (I2), the 3rd current source (I3) and the 4th current source (I4), one end of 4th switch (S4) is connected with the drain electrode of the second N-type MOS transistor (N2), one end of 5th switch (S5) is connected with the drain electrode of the 3rd N-type MOS transistor (N3), and one end of the 6th switch (S6) is connected with the drain electrode of the 4th N-type MOS transistor (N4), the other end of the 4th switch (S4), the 5th switch (S5) and the 6th switch (S6) is connected with the drain electrode of the first N-type MOS transistor (N1) and forms one article of main line, as the anode (VOUT+) of amplifier output signal, and this main line is divided into four branch roads, the one end of closing (S12) respectively with the drain electrode of a P type MOS transistor (P1), the tenth switch (S10), the 11 switch (S11) and twelvemo is connected, the other end of the tenth switch (S10) is connected with one end of the 7th current source (I7), the other end of the 11 switch (S11) is connected with one end of the 6th current source (I6), and the other end that twelvemo closes (S12) is connected with one end of the 5th current source (I5), another termination supply voltage of 5th current source (I5), the 6th current source (I6) and the 7th current source (I7), input signal negative terminal (VIN-) is connected with the grid of the 5th N-type MOS transistor (N5), the 6th N-type MOS transistor (N6), the 7th N-type MOS transistor (N7) and the 8th N-type MOS transistor (N8), the drain electrode of the 2nd P type MOS transistor (P2) is connected with grid, and the source electrode of the 2nd P type MOS transistor (P2) connects supply voltage, one end of 7th switch (S7) is connected with the drain electrode of the 6th N-type MOS transistor (N6), one end of 8th switch (S8) is connected with the drain electrode of the 7th N-type MOS transistor (N7), and one end of the 9th switch (S9) is connected with the drain electrode of the 8th N-type MOS transistor (N8), the other end of the 7th switch (S7), the 8th switch (S8) and the 9th switch (S9) is connected with the drain electrode of the 5th N-type MOS transistor (N5) and forms one article of main line, as the negative terminal (VOUT-) of amplifier output signal, and this main line is divided into four branch roads, be connected with one end of the drain electrode of the 2nd P type MOS transistor (P2), the 13 switch (S13), the 14 switch (S14) and the 15 switch (S15) respectively, the other end of the 13 switch (S13) is connected with one end of the 8th current source (I8), the other end of the 14 switch (S14) is connected with one end of the 9th current source (I9), and the other end of the 15 switch (S15) is connected with one end of the tenth current source (I10), another termination supply voltage of 8th current source (I8), the 9th current source (I9) and the tenth current source (I10).
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| CN106961255A (en) * | 2017-03-16 | 2017-07-18 | 天津大学 | The operational amplifier of programmable output Slew Rate |
| CN110971205B (en) * | 2018-09-30 | 2022-08-09 | 华为技术有限公司 | High-linearity variable gain amplifier and electronic device |
| TWI672903B (en) * | 2018-10-03 | 2019-09-21 | 立積電子股份有限公司 | Amplifier circuit |
| EP4258548A4 (en) * | 2020-12-30 | 2024-02-21 | Huawei Tech Co Ltd | Operational amplifier, drive circuit, interface chip, and electronic device |
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|---|---|---|---|---|
| US6331803B1 (en) * | 2000-05-08 | 2001-12-18 | Marvell International Ltd | Constant bandwidth, variable gain amplifier, and method |
| CN101951236A (en) * | 2010-09-20 | 2011-01-19 | 东南大学 | Digital variable gain amplifier |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6331803B1 (en) * | 2000-05-08 | 2001-12-18 | Marvell International Ltd | Constant bandwidth, variable gain amplifier, and method |
| CN101951236A (en) * | 2010-09-20 | 2011-01-19 | 东南大学 | Digital variable gain amplifier |
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| A CMOS Low-Distortion Variable Gain Amplifier;Li Yin et al;《IEEE》;20061231;P375-P378 * |
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