CN103051298A - Programmable gain amplification circuit and programmable gain amplifier - Google Patents
Programmable gain amplification circuit and programmable gain amplifier Download PDFInfo
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Abstract
The invention provides a programmable gain amplification circuit and a programmable gain amplifier. The programmable gain amplification circuit is of a symmetrical fully-differential circuit structure and comprises two differential branch circuits of the same structure, each differential branch circuit respectively comprises a differential input stage connected with a common source structure of a signal input end and a differential output stage connected with a common source structure of a signal output end, and a switching capacitor array is connected between the differential input stage and the differential output stage and connected with a feedback resistor to form a closed loop feedback circuit. The differential input stage of one differential branch circuit is connected with the differential input stage of the other differential branch circuit through a switching resistor array to form a source degeneracy structure. The programmable gain amplifier comprises a plurality of programmable gain amplification circuits connected through an alternating current coupling mode and an output buffer stage applied to a receiving end. The programmable gain amplifier can provide a large gain regulation range and can meet requirements of linearity and bandwidth.
Description
Technical field
The present invention relates to the integrated circuit (IC) design technical field, relate in particular a kind of Programmable Gain Amplifier Circuit and programmable gain amplifier.
Background technology
Along with the development of the communication technology, radio communication has entered the high speed data transfer epoch, and wider frequency band is with the Effective Raise data transmission efficiency, so Ultra-wideband Communication Technology becomes the research emphasis in the wireless communication system.
Receiver in the wireless communication system is the destination end that works in communication link, in order to receive signal and to be processed or change for local equipment, is the radio-frequency front-end demodulated received signal by receiver in communication system.Radio-frequency front-end generally includes the basic elements of character such as programmable gain amplifier, filter or baseband processing circuitry, and wherein, programmable gain amplifier is used for coming by the gain of regulating self intensity of conditioning signal, to export constant signal.
In super broad band radio communication system, need extremely wide bandwidth to transmit information, programmable gain amplifier is as a very important module in the radio-frequency front-end, its performance has vital impact to the performance of whole radio-frequency front-end, particularly at receiving terminal, need high bandwidth, high linearity and the larger amplifier of gain-adjusted scope, to realize the modulation to signal, obtain the signal of constant amplitude, for analog back-end.But existing programmable gain amplifier circuit structure is generally the open loop circuit structure, although can satisfy to a certain extent the requirement of bandwidth and the linearity, but because the restriction of open loop structure, the attainable gain of amplifier is very little, therefore its gain adjustable extent is also less, can not satisfy ultra-wideband communication system to the requirement of gain.
Therefore need at present the urgent technical problem that solves of those skilled in the art to be exactly: a kind of amplifier architecture of proposition how can innovate, amplifier gain adjustable range with the solution receiving terminal of communication system is less, and can not satisfy simultaneously the problem of high bandwidth and high linearity.
Summary of the invention
In view of this, the invention provides a kind of amplifying circuit and be applied to the amplifier of receiving terminal of communication system, little in order to solve in the communication system amplifier gain adjustable range, and can not satisfy simultaneously the problem of high bandwidth, high-gain and high linearity.
For achieving the above object, the invention provides following technical scheme:
A kind of Programmable Gain Amplifier Circuit, described Programmable Gain Amplifier Circuit are the fully differential circuit structure of symmetrical configuration, comprise two difference branch roads that structure is identical, wherein:
Each difference branch road comprises respectively the differential input stage of the common source structure that connects signal input part and the difference output stage of the common source structure that is connected signal output part, be connected with switched capacitor array between described differential input stage and the described difference output stage, and be connected with feedback resistance formation closed loop feedback structure;
Link to each other by the switch resistance array between the differential input stage of the differential input stage of one difference branch road and another difference branch road, form source degeneracy structure.
Preferably, described switched capacitor array is comprised of n capacitance switch connection in series-parallel, and described capacitance switch string is composed in series by electric capacity and switch; Described switch resistance array is comprised of n resistance switch connection in series-parallel, and described resistance switch string is composed in series by two resistance and switch, and wherein, n is positive integer.
Preferably, described differential input stage comprises difference input transistors, bias current transistor and the first current source load transistor, described difference input crystal tube grid connects signal input part, its source electrode links to each other with the bias current transistor drain electrode, and its drain electrode links to each other with the first current source load transistor drain; Described bias current transistor source electrode connects supply voltage, and its grid connects bias voltage; Described the first current source load transistor source ground connection, its grid connects bias voltage;
Described difference output stage comprises common source transistor and the second current source load transistor, described common source transistor drain links to each other with the second current source load transistor drain, and the connection signal output part, its grid connects the drain electrode of the first current source load, its source ground; Described the second current source load transistor gate connects bias voltage, and its source electrode connects supply voltage;
Described switched capacitor array is connected between the drain electrode of difference input transistors and the common source transistor drain;
Described feedback resistance is connected between difference input transistors source electrode and the second current source load transistor drain;
Described switch resistance array is connected between the source electrode of two difference input transistors in two difference branch roads.
Preferably, described difference input transistors and bias current transistor are the PMOS transistor, and described the first current source load transistor is nmos pass transistor, and described common source transistor is nmos pass transistor, and described the second current source load transistor is the PMOS transistor.
A kind of programmable gain amplifier is applied to receiving terminal of communication system, and described programmable gain amplifier comprises a plurality of above-mentioned Programmable Gain Amplifier Circuit and the output buffer stage that is applied to receiving terminal, wherein:
Connect in the AC coupled mode between the described Programmable Gain Amplifier Circuit and between Programmable Gain Amplifier Circuit and the output buffer stage, the signal output part of each Programmable Gain Amplifier Circuit connects the signal input part of next Programmable Gain Amplifier Circuit, and the signal output part of last Programmable Gain Amplifier Circuit connects the signal input part of output buffer stage.
Preferably, the fully differential form that the described output buffer stage that is applied to receiving terminal is symmetrical configuration recommend inverter structure, wherein:
Each difference branch road comprises the first transistor and transistor seconds, described the first transistor drain electrode links to each other with described transistor seconds drain electrode and is connected a signal output part, its grid links to each other with the transistor seconds grid and is connected a signal input part, and its source electrode connects supply voltage; Described transistor seconds source ground.
Preferably, the signal output part of described amplifying circuit connects the signal input part of next amplifying circuit by a pair of difference capacitance, and the signal output part of last amplifying circuit connects the signal input part of output buffer stage by a pair of difference capacitance.
Preferably, described the first transistor is the PMOS transistor, and described transistor seconds is nmos pass transistor.
Preferably, described amplifier specifically comprises five Programmable Gain Amplifier Circuit.
Preferably, four Programmable Gain Amplifier Circuit gain variation range in the described programmable gain amplifier are identical, and the gain-adjusted step-length of described four Programmable Gain Amplifier Circuit is greater than the gain-adjusted step-length of another amplifying circuit.
Via above-mentioned technical scheme as can be known, compared with prior art, the invention provides a kind of Programmable Gain Amplifier Circuit and programmable gain amplifier, described Programmable Gain Amplifier Circuit is the fully differential circuit structure, the circuit structure of employing source degeneracy, source degeneracy structure can improve the linearity of amplifying circuit.And described Programmable Gain Amplifier Circuit forms the closed loop feedback structure, the ratio of feedback resistance and source degeneracy resistance is depended in gain, bandwidth depends on the product of feedback resistance and building-out capacitor, wherein said source degeneracy resistance and building-out capacitor all adopt the switch arrays form, by controlling different switches, select suitable source degeneracy resistance and building-out capacitor can satisfy gain and can be in harmonious proportion the requirement of high bandwidth.Programmable gain amplifier of the present invention adopts a plurality of described Programmable Gain Amplifier Circuit to connect with the cascade of AC coupled mode, can satisfy the requirement of larger gain-adjusted scope, and each amplifying circuit only need provide less gain to get final product, thereby avoided gain when larger and the problem of the step-down amplifier linearity has satisfied high bandwidth in the ultra-wideband communication system, high linearity and the large requirement of gain-adjusted scope.Simultaneously, amplifier of the present invention adopts the output stage that is applied to receiving terminal, so that this amplifier architecture can drive the receiving terminal load.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, the below will do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art, apparently, accompanying drawing in the following describes only is embodiments of the invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to the accompanying drawing that provides other accompanying drawing.
Fig. 1 is the electrical block diagram of an embodiment of a kind of Programmable Gain Amplifier Circuit of the present invention;
Fig. 2 is the equivalent circuit structure schematic diagram of a kind of Programmable Gain Amplifier Circuit of the present invention;
Fig. 3 is the electrical block diagram of a kind of programmable gain amplifier of the present invention;
Fig. 4 is the electrical block diagram that is applied to the output buffer stage of receiving terminal in the programmable gain amplifier of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
The embodiment of the invention discloses a kind of Programmable Gain Amplifier Circuit and programmable gain amplifier, described Programmable Gain Amplifier Circuit is the fully differential circuit structure, adopts source degeneracy common source amplification circuit structure, has improved the linearity.Described amplifying circuit forms the closed loop feedback structure, the ratio of feedback resistance and source degeneracy resistance is depended in gain, bandwidth depends on the product of feedback resistance and building-out capacitor, wherein source degeneracy resistance and building-out capacitor adopt the switch arrays form, by controlling different switches, select suitable source degeneracy resistance and building-out capacitor can satisfy gain and the adjustable requirement of bandwidth.Programmable gain amplifier of the present invention adopts a plurality of described Programmable Gain Amplifier Circuit to connect to form in the AC coupled mode, can satisfy the larger requirement of gain-adjusted scope.Because each Programmable Gain Amplifier Circuit only need provide less gain get final product, thereby avoided gaining when larger and affected the problem of linearity of amplifier degree, satisfied high bandwidth in the ultra-wideband communication system, high linearity and the large requirement of gain-adjusted scope.Simultaneously, programmable gain amplifier of the present invention adopts the output stage that is applied to receiving terminal, so that this programmable gain amplifier can drive the receiving terminal load.
Fig. 1 shows the electrical block diagram of an embodiment of a kind of amplifying circuit of the present invention.
Described Programmable Gain Amplifier Circuit is the fully differential circuit structure of symmetrical configuration, comprise two difference branch roads that structure is identical, each difference branch road comprises respectively the differential input stage of the common source structure that connects signal input part and the difference output stage of the common source structure that is connected signal output part, connecting valve capacitor array between differential input stage and the difference output stage, and be connected with feedback resistance formation closed-loop feedback circuit; Link to each other by the switch resistance array between the differential input stage of the differential input stage of one difference branch road and another difference branch road, form source degeneracy structure.
In conjunction with Fig. 1, for the convenience on describing, if described two difference branch roads are respectively the first difference branch road and the second difference branch road, described signal input part comprises a signal input part Vinp and another signal input part Vinn, respectively as the signal input part of difference branch road; Described signal output part comprises a signal output part Voutp and another signal output part Voutn, respectively as the signal input part of difference branch road.
Described the first difference branch road comprises the first differential input stage 101 of the common source structure that connects signal input part Vinp and the first difference output stage 102 of the common source structure that is connected signal output part Voutp, and described the second difference branch road comprises the second differential input stage 103 of the common source structure that connects signal input part Vinn and the second difference output stage 104 of the common source structure that is connected signal output part Voutn.
Be connected with the first switched capacitor array 105 between described the first differential input stage 101 and the second difference output stage 102, and be connected with the first feedback resistance 106, form closed-loop feedback circuit; Be connected with second switch capacitor array 107 between described the second differential input stage 103 and the second difference output stage 104, and be connected with the second feedback resistance 108, form closed-loop feedback circuit.
Link to each other by switch resistance array 109 between described the first differential input stage 101 and the second differential input stage 103, form source degeneracy structure.
The electric capacity that comprises in the described switched capacitor array is the building-out capacitor of circuit, and the resistance that described switch resistance array comprises is source degeneracy resistance.
In the present embodiment, described Programmable Gain Amplifier Circuit adopts source degeneracy circuit structure, improved the linearity, simultaneously described amplifying circuit forms the closed loop feedback structure, yield value depends on the ratio of feedback resistance and source degeneracy resistance, bandwidth depends on the product of feedback resistance and building-out capacitor, and described source degeneracy resistance and building-out capacitor employing switch arrays form.Can select suitable source degeneracy resistance and building-out capacitor can satisfy high bandwidth and the adjustable requirement of gain by control switch.
Wherein, concrete, in conjunction with Fig. 1, described the first differential input stage 101 comprises difference input transistors M11, bias current transistor M21 and the first current source load transistor M31, the grid of described difference input transistors M11 connects signal input part Vinp, its source electrode links to each other with the drain electrode of bias current transistor M21, and its drain electrode links to each other with the first current source load transistor M31 drain electrode; The source electrode of described bias current transistor M21 connects supply voltage, and its grid connects bias voltage Vbp; The source ground of described the first current source load transistor M31, its grid connects bias voltage Vbn.
Described the second differential input stage 103 is identical with described the first differential input stage 101 structures, comprise difference input transistors M12, bias current transistor M22 and the first current source load transistor M32, the grid of described difference input transistors M12 connects signal input part Vinn, its source electrode links to each other with the drain electrode of bias current transistor M22, and its drain electrode links to each other with the first current source load transistor M32 drain electrode; The source electrode of described bias current transistor M22 connects supply voltage, and its grid connects bias voltage Vbp; The source ground of described the first current source load transistor M32, its grid connects bias voltage Vbn.
Described the first difference output stage 102 comprises common source transistor M41 and the second current source load transistor M51, the drain electrode of described common source transistor M41 links to each other with the drain electrode of the second current source load transistor M51, and connection signal output part Voutp, its grid connects the drain electrode of the first current source load transistor M31, its source ground; The grid of described the second current source load transistor M51 connects bias voltage Vbp, and its source electrode connects supply voltage.
Described the second difference output stage 104 is identical with the first difference output stage 102 structures, comprise common source transistor M42 and the second current source load transistor M52, the drain electrode of described common source transistor M42 links to each other with the drain electrode of the second current source load transistor M52, and connection signal output part Voutn, its grid connects the drain electrode of the first current source load transistor M32, its source ground; The grid of described the second current source load transistor M52 connects bias voltage Vbp, and its source electrode connects supply voltage.
Described the first switched capacitor array 105 is connected between the drain electrode of the drain electrode of difference input transistors M11 and common source transistor M41, be that described the first switched capacitor array 105 1 ends link to each other with the drain electrode of difference input transistors M11, the other end together drain electrode of source transistor M41 links to each other; Described second switch capacitor array 107 is connected between the drain electrode of the drain electrode of difference input transistors M12 and common source transistor M42, also be that described second switch capacitor array 107 1 ends link to each other with the drain electrode of difference input transistors M12, the other end together drain electrode of source transistor M42 links to each other.
Described the first feedback resistance 106 is connected between the drain electrode of the source electrode of difference input transistors M11 and the second current source load transistor M51, also be that described the first feedback resistance 106 1 ends link to each other with the source electrode of difference input transistors M11, the other end links to each other with the drain electrode of the second current source load transistor M51; Described the second feedback resistance 108 is connected between the drain electrode of the source electrode of difference input transistors M12 and the second current source load transistor M52, also be that described the second feedback resistance 108 1 ends link to each other with the source electrode of difference input transistors M12, the other end links to each other with the drain electrode of the second current source load transistor M52.
Described switch resistance array 109 is connected between the source electrode of the source electrode of difference input transistors M11 and difference input transistors M12, also be that described switch resistance array 109 1 ends link to each other with the source electrode of difference input transistors M11, the other end links to each other with the source electrode of difference input transistors M12.
Wherein, described switch resistance array 109 is comprised of n resistance switch connection in series-parallel, and described resistance switch string is composed in series by two resistance and switch; Described the first switched capacitor array 105 and described second switch capacitor array 107 form by n capacitance switch connection in series-parallel, described capacitance switch string is composed in series by electric capacity and switch, wherein, n is positive integer, and described two resistance are namely respectively as the source degeneracy resistance of difference branch road.
As shown in Figure 1, in the first switched capacitor array 105, described capacitance switch string comprises capacitor C
N1And switch S
N1, wherein n=1,2,3...... such as first switching capacity string comprise capacitor C
11And switch S
11, second switch electric capacity string comprises capacitor C
21And switch S
21... n switching capacity string comprises capacitor C
N1And switch S
N1In second switch capacitor array 107, described capacitance switch string comprises capacitor C
N2And switch S
N2, wherein n=1,2,3...... such as first capacitance switch string comprise capacitor C
12And switch S
12, second switch electric capacity string comprises capacitor C
22And switch S
22... n switching capacity string comprises capacitor C
N2And switch S
N2
In described switch resistance array 109, described resistance switch string comprises resistance R
Sn1, resistance R
Sn2And switch S
n, comprise resistance R such as first resistance switch string
S11, R
S12And switch S
1, the second resistor switch series comprises resistance R
S21, R
S22And switch S
2... n resistance switch string comprises resistance R
Sn1, R
Sn2And switch S
n
The first switched capacitor array 205 and second switch capacitor array 207 are respectively the building-out capacitor of the difference branch road in the difference channel structure, the R in the switch resistance array
Sn1And R
Sn2Be respectively the source degeneracy resistance of difference branch road.
Because building-out capacitor and source degeneracy resistance are the switch arrays form, therefore select different switches, can obtain different building-out capacitors and source degeneracy resistance.Specifically can referring to Fig. 2, show the equivalent circuit structure figure of a kind of Programmable Gain Amplifier Circuit of the present invention.
In real work, difference input transistors M11 and difference input transistors M12 are difference input transistors pair, be used for the input voltage signal of its grid is converted to current signal, bias current transistor M21 and bias current transistor M22, be used for the current source as the difference input, so that flow through the right current constant of difference input transistors.Input signal by the difference input transistors to passing to source degeneracy resistance, so that the linearity of the conversion mutual conductance of input signal improves, the conversion mutual conductance is that the difference input is to the mutual conductance of pipe, employing source degeneracy structure, described conversion mutual conductance shows as the inverse of source degeneracy resistance, be a linear term, therefore guaranteed the linearity of amplifying circuit.
In conjunction with Fig. 1 and Fig. 2, in the Programmable Gain Amplifier Circuit of present embodiment, yield value depends on the ratio of feedback resistance and source degeneracy resistance, and computing formula is:
A
v＝1+R
f/R
s
Wherein, R
SFor selected source degeneracy resistance in the difference branch road, be the R in the switch resistance array
Sn1Perhaps R
Sn2R
fBeing the feedback resistance in the difference branch road, is the first feedback resistance 106 or the second feedback resistance 108, can be learnt by this formula, and the ratio of two feedback resistances is depended in the amplifying circuit gain.
Bandwidth is approximately:
ω
-3dB≈1/R
f*C
Capacitor C is the selected building-out capacitor of difference branch road, is the C in the capacitive switch array
N1Perhaps C
N2, the bandwidth of described amplifying circuit is not only relevant with building-out capacitor, and is also relevant with feedback resistance.
By above-mentioned two formulas as can be known, keep feedback resistance R
fConstant, select different source degeneracy resistance R by control switch
SWith building-out capacitor C, can obtain different gains and bandwidth.
Wherein, described n value, and the capacitance in each switch arrays or resistance value are according in the different actual conditions requirement of bandwidth and gain variation range specifically being set.
In the integrated circuit (IC) design field, described difference input transistors and bias current transistor can be PMOS (P type Metal-Oxide-Semiconductor, Metal-oxide-semicondutor) transistor, described the first current source load transistor can be nmos pass transistor, described common source transistor can be NMOS (N-type metal-oxide-semiconductor) transistor, and described the second current source load transistor can be the PMOS transistor.
In the embodiment of the invention, building-out capacitor and source degeneracy resistance are the switch arrays form in the Programmable Gain Amplifier Circuit, switch by the control switch electric resistance array, can select the resistance of different resistances as source degeneracy resistance, because the yield value of amplifying circuit is determined by source degeneracy resistance and inter-stage feedback resistance ratio, therefore, keeps feedback resistance constant, can obtain different gains according to the different source degeneracy resistance of selecting, realize that gain is adjustable.Switch by the control switch capacitor array, can select the electric capacity of different values, because the pga circuit bandwidth depends on inter-stage feedback resistance and feedback capacity, feedback resistance is constant, therefore can obtain different bandwidth according to different capacitances, and described Programmable Gain Amplifier Circuit adopts source degeneracy circuit structure, has improved the linearity.
Referring to Fig. 3, show the electrical block diagram of a kind of programmable gain amplifier of the present invention, described programmable gain amplifier is applied to receiving terminal of communication system.
Described programmable gain amplifier comprises a plurality of above-mentioned Programmable Gain Amplifier Circuit and an output buffer stage that is applied to receiving terminal.Wherein, the number of described a plurality of Programmable Gain Amplifier Circuit is specifically set according to the performance of each amplifying circuit, and described performance comprises available gain variation range, the requirements such as bandwidth excursion, the linearity and power consumption.
Can comprise in the present embodiment that five Programmable Gain Amplifier Circuit are described, therefore in conjunction with Fig. 3, described programmable gain amplifier specifically comprises first order Programmable Gain Amplifier Circuit 301, second level Programmable Gain Amplifier Circuit 302, third level Programmable Gain Amplifier Circuit 303, fourth stage Programmable Gain Amplifier Circuit 304, level V Programmable Gain Amplifier Circuit 305 and is applied to the output buffer stage 306 of receiving terminal.
Need to prove that the present invention does not specifically limit the number of described Programmable Gain Amplifier Circuit.In actual applications, described programmable gain amplifier can be selected five Programmable Gain Amplifier Circuit cascades, guarantees to realize the indices of programmable gain amplifier.
Between the described Programmable Gain Amplifier Circuit and Programmable Gain Amplifier Circuit and be applied to connect in the AC coupled mode between the output buffer stage of receiving terminal, the signal output part of each Programmable Gain Amplifier Circuit connects the signal input part of next Programmable Gain Amplifier Circuit, and the signal output part of last Programmable Gain Amplifier Circuit connects the signal input part of described output buffer stage.
Concrete, the signal output part of Programmable Gain Amplifier Circuit is by the signal input part of the next Programmable Gain Amplifier Circuit of a pair of difference capacitance 307 connections, and the signal output part of last Programmable Gain Amplifier Circuit connects the signal input part of output buffer stages by a pair of difference capacitance 307.This employing capacitance carries out the mode of AC coupled can the cancellation of DC offset phenomenon.
Wherein, the structure of described each amplifying circuit is identical, and concrete structure can be described referring to above-mentioned Programmable Gain Amplifier Circuit specific embodiment, do not repeat them here.
In communication system, particularly in the ultra-wideband communication system, programmable gain amplifier is as the important module of radio-frequency front-end, its performance is most important for radio-frequency front-end, particularly at receiving terminal, needs a gain dynamic range large, the programmable gain amplifier of high linearity and high bandwidth comes according to the signal amplitude that receives, adjust, obtain the signal of a constant amplitude, to export to analog back-end.
In the present embodiment, comprise a plurality of Programmable Gain Amplifier Circuit, and connect by the AC coupled mode, because each Programmable Gain Amplifier Circuit all can provide the higher linearity, larger bandwidth and a gain-adjusted scope, a plurality of Programmable Gain Amplifier Circuit cascades, can guarantee the linearity and the bandwidth requirement of programmable gain amplifier, and increased the adjustable range of gain, therefore can satisfy programmable gain amplifier high linearity, large bandwidth and the large requirement of gain-adjusted scope.
Wherein, consider the situation of receiving terminal load, the receiving terminal load is comprised of a low resistance and a large Capacitance parallel connection usually.Therefore, adopt an output buffer stage that is applied to receiving terminal to drive the load of receiving terminal.
Concrete, referring to Fig. 4, show the electrical block diagram that the present invention is applied to the output buffer stage 306 of receiving terminal programmable gain amplifier, the fully differential form that described output buffer stage is symmetrical configuration recommend inverter structure, comprise the two-pass DINSAR branch road that structure is identical, each difference branch road comprises the first transistor and transistor seconds, wherein the first transistor drain electrode links to each other with the transistor seconds drain electrode and is connected a signal output part, its grid links to each other with the transistor seconds grid and is connected a signal input part, and its source electrode connects supply voltage; The transistor seconds source ground.
For the convenience on describing, described two-pass DINSAR branch road is made as respectively the first difference branch road and the second difference branch road, described the first difference branch road comprises the first transistor Mp1 and transistor seconds Mn1, the drain electrode of the first transistor Mp1 links to each other with the drain electrode of transistor seconds Mn1 and is connected another signal output part Voutn1, its grid links to each other with the transistor seconds grid and is connected a signal input part Vinp1, and its source electrode connects supply voltage; The source ground of transistor seconds Mn1.
In like manner, described the second difference branch road comprises the first transistor Mp2 and transistor seconds Mn2, the drain electrode of the first transistor Mp2 links to each other with the drain electrode of transistor seconds Mn2 and is connected another signal output part Voutp1, its grid links to each other with the transistor seconds grid and is connected another signal input part Vinn1, and its source electrode connects supply voltage; The source ground of transistor seconds Mn1.
Wherein, described the first transistor can be the PMOS transistor, and described transistor seconds can be nmos pass transistor.
Because each Programmable Gain Amplifier Circuit comprises two signal output parts and two signal input parts, therefore two signal input parts of first order Programmable Gain Amplifier Circuit connect respectively the input side of differential signal, two signal output part connects two signal input parts of second level amplifying circuit by a pair of capacitance, according to this, the signal output part of every one-level Programmable Gain Amplifier Circuit all connects the signal input part of the amplifying circuit of next stage by a pair of capacitance, the afterbody Programmable Gain Amplifier Circuit, two signal output parts that also are the level V Programmable Gain Amplifier Circuit connect two signal input parts exporting buffer stage by a pair of isolation capacitance, two signal output parts of described output buffer stage connect respectively the load circuit of receiving terminal, and the load circuit of described receiving terminal is generally baseband processing circuitry.
In actual applications, by controlling switched capacitor array in every one-level amplifying circuit and the different switches in the degeneracy switch resistance array of source, can obtain the different gains of amplifier, realize the large dynamic change scope of gain, guarantee simultaneously high bandwidth and high linearity requirement.
Comprise that take described programmable gain amplifier five Programmable Gain Amplifier Circuit are as example, for satisfying receiving terminal of communication system to the requirement of gain-adjusted scope, four Programmable Gain Amplifier Circuit gain variation range that arrange in the described programmable gain amplifier are identical, and the gain-adjusted step-length of described four Programmable Gain Amplifier Circuit is greater than the gain-adjusted step-length of another amplifying circuit.For example, for so that the attainable gain variation range of amplifying circuit is 0～50dB (decibel), change step is 2dB, and therefore every one-level amplifying circuit is guaranteeing in the high situation of the linearity, adopt the form of Pyatyi cascade, every one-level provides a less gain dynamic change scope.By controlling different switch combinations, select electric capacity and the resistance of varying number and numerical value, so that the amplifying circuit of front level Four is realized the coarse tuning of gain, the attainable gain variation range of every one-level in the front level Four is 0～12dB, tuning step-length is 6dB, the level V amplifying circuit is realized the fine tuning scope of gain, and gain dynamic change scope is 0～6dB, and tuning step-length is 2dB.The while control switch, the high bandwidth of assurance amplifier can reach the hundreds of megahertz, has satisfied the requirement of ultra-wideband communication system high bandwidth.
Each embodiment adopts the mode of going forward one by one to describe in this specification, and what each embodiment stressed is and the difference of other embodiment that identical similar part is mutually referring to getting final product between each embodiment.
To the above-mentioned explanation of the disclosed embodiments, make this area professional and technical personnel can realize or use the present invention.Multiple modification to these embodiment will be apparent concerning those skilled in the art, and General Principle as defined herein can in the situation that does not break away from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention will can not be restricted to these embodiment shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (10)
1. a Programmable Gain Amplifier Circuit is characterized in that, described Programmable Gain Amplifier Circuit is the fully differential circuit structure of symmetrical configuration, comprises two difference branch roads that structure is identical, wherein:
Each difference branch road comprises respectively the differential input stage of the common source structure that connects signal input part and the difference output stage of the common source structure that is connected signal output part, be connected with switched capacitor array between described differential input stage and the described difference output stage, and be connected with feedback resistance formation closed loop feedback structure;
Link to each other by the switch resistance array between the differential input stage of the differential input stage of one difference branch road and another difference branch road, form source degeneracy structure.
2. Programmable Gain Amplifier Circuit according to claim 1 is characterized in that, described switched capacitor array is comprised of n capacitance switch connection in series-parallel, and described capacitance switch string is composed in series by electric capacity and switch; Described switch resistance array is comprised of n resistance switch connection in series-parallel, and described resistance switch string is composed in series by two resistance and switch, and wherein, n is positive integer.
3. Programmable Gain Amplifier Circuit according to claim 1 and 2, it is characterized in that, described differential input stage comprises difference input transistors, bias current transistor and the first current source load transistor, described difference input crystal tube grid connects signal input part, its source electrode links to each other with the bias current transistor drain electrode, and its drain electrode links to each other with the first current source load transistor drain; Described bias current transistor source electrode connects supply voltage, and its grid connects bias voltage; Described the first current source load transistor source ground connection, its grid connects bias voltage;
Described difference output stage comprises common source transistor and the second current source load transistor, described common source transistor drain links to each other with the second current source load transistor drain, and the connection signal output part, its grid connects the drain electrode of the first current source load, its source ground; Described the second current source load transistor gate connects bias voltage, and its source electrode connects supply voltage;
Described switched capacitor array is connected between the drain electrode of difference input transistors and the common source transistor drain;
Described feedback resistance is connected between difference input transistors source electrode and the second current source load transistor drain;
Described switch resistance array is connected between the source electrode of two difference input transistors in two difference branch roads.
4. Programmable Gain Amplifier Circuit according to claim 3, it is characterized in that, described difference input transistors and bias current transistor are the PMOS transistor, described the first current source load transistor is nmos pass transistor, described common source transistor is nmos pass transistor, and described the second current source load transistor is the PMOS transistor.
5. programmable gain amplifier, it is characterized in that, be applied to receiving terminal of communication system, described programmable gain amplifier comprises a plurality of such as each described Programmable Gain Amplifier Circuit of claim 1～4 and the output buffer stage that is applied to receiving terminal, wherein:
Connect in the AC coupled mode between the described Programmable Gain Amplifier Circuit and between Programmable Gain Amplifier Circuit and the output buffer stage, the signal output part of each Programmable Gain Amplifier Circuit connects the signal input part of next Programmable Gain Amplifier Circuit, and the signal output part of last Programmable Gain Amplifier Circuit connects the signal input part of output buffer stage.
6. programmable gain amplifier according to claim 5 is characterized in that, the fully differential form that the described output buffer stage that is applied to receiving terminal is symmetrical configuration recommend inverter structure, wherein:
Each difference branch road comprises the first transistor and transistor seconds, described the first transistor drain electrode links to each other with described transistor seconds drain electrode and is connected a signal output part, its grid links to each other with the transistor seconds grid and is connected a signal input part, and its source electrode connects supply voltage; Described transistor seconds source ground.
7. programmable gain amplifier according to claim 6, it is characterized in that, the signal output part of described amplifying circuit connects the signal input part of next amplifying circuit by a pair of difference capacitance, and the signal output part of last amplifying circuit connects the signal input part of output buffer stage by a pair of difference capacitance.
8. programmable gain amplifier according to claim 6 is characterized in that, described the first transistor is the PMOS transistor, and described transistor seconds is nmos pass transistor.
9. programmable gain amplifier according to claim 5 is characterized in that, described amplifier specifically comprises five Programmable Gain Amplifier Circuit.
10. programmable gain amplifier according to claim 9, it is characterized in that, four Programmable Gain Amplifier Circuit gain variation range in the described programmable gain amplifier are identical, and the gain-adjusted step-length of described four Programmable Gain Amplifier Circuit is greater than the gain-adjusted step-length of another amplifying circuit.
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