CN203377841U - Satellite-based crystal oscillator taming apparatus for time service - Google Patents
Satellite-based crystal oscillator taming apparatus for time service Download PDFInfo
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- CN203377841U CN203377841U CN201320406853.6U CN201320406853U CN203377841U CN 203377841 U CN203377841 U CN 203377841U CN 201320406853 U CN201320406853 U CN 201320406853U CN 203377841 U CN203377841 U CN 203377841U
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Abstract
The utility model provides a satellite-based crystal oscillator taming apparatus for time service. The apparatus comprises a navigation positioning receiver, an FPGA chip circuit, a voltage controlled oscillator, a digital-to-analog converter and a power supply module. The FPGA chip circuit includes a validity determination module, a digital phase discriminator, a filter, an aging compensation module, a proportional-integral controller, a frequency divider, a frequency multiplication device and a delayer. Through satellite time frequency standards, more accurate and stable local crystal oscillator output frequency can be obtained and the precision can reach up to a nanosecond level, so that the apparatus can be better applied to production and life.
Description
Technical field
The utility model relates to a kind of crystal oscillator and tames equipment, and specifically a kind of crystal oscillator based on satellite time transfer is tamed equipment.
Background technology
In various Time synchronization technique, satellite time transfer owing to thering is broad covered area, the frequency reference precision is high (can reach 10
-12~ 10
-15), lower characteristics of relative cost and being widely used.People generally extract the synchronised clock frequency of satellite system by navigation positioning receiver, yet satellite distance ground kilometers up to ten thousand, navigation positioning receiver can inject interference signal and random noise in the process of demodulation, therefore, although adopt satellite time transfer to there is the long-term stability of tracking satellite signal, increased the phase jitter of short-term.On the contrary, have advantages of that such as voltage type crystal oscillator (VCXO) and thermostatic control formula crystal oscillator (OCXO) etc. short-term stability is good, but these crystal oscillators exist aging inherent shortcoming, and performance steady in a long-term is poor.
The utility model content
The purpose of this utility model just is to provide a kind of crystal oscillator based on satellite time transfer and tames equipment, to solve local crystal oscillator, because of the aging clock accuracy that causes, descends and the poor problem of performance steady in a long-term.
The utility model is achieved in that a kind of crystal oscillator based on satellite time transfer tames equipment, comprising:
Navigation positioning receiver, join with the validity judge module, for the standard second pulse signal that receives satellite system and it is transferred to the validity judge module;
The validity judge module, with described navigation positioning receiver, digital phase discriminator and compensation of ageing module, join respectively, whether effective for judging the standard second pulse signal that navigation positioning receiver transmits, effectively the standard second pulse signal is transferred to digital phase discriminator, and invalid standard second pulse signal sends to the compensation of ageing module;
Digital phase discriminator, with described validity judge module, filter, frequency divider and delayer, join respectively, for the crystal oscillator pps pulse per second signal that receives the standard second pulse signal and transmitted by delayer, and two pps pulse per second signals that receive are carried out to the phase difference comparison to obtain the clock difference signal, afterwards the clock difference signal is exported to filter, control frequency divider output crystal oscillator pps pulse per second signal simultaneously when the clock difference signal stabilization;
Filter, join with described digital phase discriminator and compensation of ageing module respectively, for the noise of filtering clock difference signal, and the clock difference signal after filtering noise exported to the compensation of ageing module;
The compensation of ageing module, with described validity judge module, described filter and pi controller, join respectively, ageing error for compensated voltage controlled oscillator, and the clock difference signal after compensation of ageing is exported to pi controller, and, when receiving invalid standard second pulse signal, extract punctual signal and export to pi controller;
Pi controller, join with described compensation of ageing module and digital to analog converter respectively, for the clock difference signal to after filtering noise and compensation of ageing, carries out smothing filtering, converts the clock difference signal to digital regulated amount afterwards and export to digital to analog converter;
Digital to analog converter, join with described pi controller and voltage controlled oscillator respectively, for the clock difference digital signal to converting digital regulated amount to, carries out exporting to voltage controlled oscillator after digital-to-analogue conversion;
Voltage controlled oscillator, join with described digital to analog converter, frequency divider and frequency multiplier respectively, under the control in the clock difference analog signal to the pulse signal of frequency divider and frequency multiplier output rated frequency;
Frequency divider, with described digital phase discriminator, described voltage controlled oscillator and delayer, join respectively, for will be the crystal oscillator pps pulse per second signal by the pulse signal frequency division of the rated frequency of voltage controlled oscillator output, and under the control of digital phase discriminator to delayer output crystal oscillator pps pulse per second signal;
Delayer, join with described frequency divider and described digital phase discriminator respectively, for the crystal oscillator pps pulse per second signal is carried out exporting to digital phase discriminator after delay process, and exports the clock signal of crystal oscillator pps pulse per second signal after time delay is adjusted simultaneously;
Frequency multiplier, join with described voltage controlled oscillator, for the pulse signal of the rated frequency to voltage controlled oscillator output, increased frequently, for relevant device, uses; And
Power module, join with each part mentioned above, provides each several part required operating voltage.
Described navigation positioning receiver is GPS receiver or Beidou satellite receiver.
The pulse signal that the pulse signal of the rated frequency of being exported by voltage controlled oscillator is 10MHz.
The utility model makes the frequency of local voltage controlled oscillator consistent with spaceborne caesium or rubidium atomic frequency standard on satellite system, the 1pps signal that the taming voltage controlled oscillator of pps pulse per second signal obtains like this, has via satellite just had the accuracy of satellite pps pulse per second signal and the stability of local voltage controlled oscillator concurrently.The aging error caused because of voltage controlled oscillator by the compensation of ageing module for compensating simultaneously, thereby can solve the problem of the clock accuracy decline caused because local voltage controlled oscillator is aging, realize short-term and all there is for a long time high stability, high-precision frequency reference and time synchronizing standard source.The utility model precision high (can reach the ns level), cost are low, good stability, life-span are long, can be applied to better productive life.
The accompanying drawing explanation
Fig. 1 is circuit structure block diagram of the present utility model.
Embodiment
As shown in Figure 1, the utility model comprises navigation positioning receiver 1, FPGA(field programmable gate array, Field-Programmable Gate Array) chip circuit 2, voltage controlled oscillator 3, digital to analog converter 4 and power module 5.Fpga chip circuit 2 comprises again validity judge module 21, digital phase discriminator 22, filter 23, compensation of ageing module 24, pi controller 27, frequency divider 26, frequency multiplier 28 and delayer 25.
Navigation positioning receiver 1 is GPS receiver or Beidou satellite receiver, and both are redundance unit each other, when the two all can be worked, can compare the rear optimum selecting of judgement to signal that is:, when one can not be worked, can independently be switched to the opposing party.
Navigation positioning receiver 1 adopts the active antenna pattern, and the replacement between GPS receiver and Beidou satellite receiver only need get final product connecting the corresponding interface.All leave serial ports (UART) communication interface and 1pps signaling interface in the modular circuit of GPS receiver and Beidou satellite receiver, UART is for the navigation data information of receiver module, operating state that on the one hand can test module, on the other hand can be in system the function of integrated with guidance location, facilitate system extension.
The LEA-5T model GPS receiver that navigation positioning receiver 1 in the present embodiment adopts U-blox company to release.Navigation positioning receiver 1 receives the standard second pulse 1pps signal of satellite system and it is transferred to validity judge module 21.
The clock difference signal that 24 pairs of compensation of ageing modules receive carries out the ageing error compensation, to eliminate the error of bringing because of the intrinsic aging blemiss of voltage controlled oscillator 3 own, and the clock difference signal after compensation is transferred to proportional integral (PI) controller 27.Compensation of ageing module 24, also for when receiving invalid standard second pulse 1pps signal, is extracted punctual signal (being stored in compensation of ageing module 24 inside) and is exported to pi controller 27.
Clock difference signal after 27 pairs of filtering noise signals of pi controller and compensation of ageing carries out smothing filtering, converts the clock difference signal to digital regulated amount afterwards and exports to digital to analog converter 4.
Digital to analog converter 4 is selected 18 conversion chip DAC9881 of TI company, adopts the SPI serial interface mode of standard, can reach 50MHz data input clock frequency.4 pairs of digital to analog converters convert the clock difference digital signal of digital regulated amount to carry out exporting to voltage controlled oscillator 3 after digital-to-analogue conversion.
In the present embodiment, voltage controlled oscillator 3 is selected the constant temperature VCXO (VCOCXO) of brilliant standing grain scientific & technical corporation, its short-term frequency stability<5 * 10
-12/ s, ageing rate is ± 0.03ppm/.Voltage controlled oscillator 3 under the control of clock difference analog signal to the pulse signal of the rated frequency of frequency divider 26 and frequency multiplier 28 output 10MHz.
Delayer 25 carries out crystal oscillator pulse per second (PPS) 1pps signal to export to digital phase discriminator 22 after delay process; Export the clock signal of crystal oscillator pulse per second (PPS) 1pps signal after time delay is adjusted simultaneously, comprise with B second (adopting the clock signal of IRIG-B coding) and two kinds of form type outputs of time service second (or punctual second).
Fpga chip adopts the EP3C120484 model of the U.S. CycloneIII of ALTERA company series, can embed the NiosII soft-core processor.During the FPGA configuration circuit, QuartusII software downloads to configuration file in FPGA by the JTAG mouth, at first the AS pattern downloads to configuration file in EPCS by the AS mouth by QuartusII, can from EPCS device read configuration file when then FPGA powers at every turn and reconfigure FPGA.This equipment adopts universal circuit, and the SDRAM memory uses two MT48LC4M16A2.
The present embodiment median filter 23, frequency divider 26, frequency multiplier 28, delayer 25, PI controller 27, NiosII all build on the SOPC hardware platform.Wherein before the PI link, first the clock difference signal is carried out to Kalman filtering, estimate the actual value of clock difference, then recycle the tracking lock that PI controller 27 is realized system, result shows, filter effect is relatively good.After whole SOPC system building completes, just can utilize the application program of NiosII IDE developing instrument exploitation based on the NiosII processor.
The utility model adopts fpga chip circuit 2, Mathematical model control device 4 and voltage controlled oscillator 3 to build a closed negative feedback phase-locked loop, has realized the purpose of the local crystal oscillator frequency of taming adjusting.
Claims (3)
1. the crystal oscillator based on satellite time transfer is tamed equipment, it is characterized in that, comprising:
Navigation positioning receiver, join with the validity judge module, for the standard second pulse signal that receives satellite system and it is transferred to the validity judge module;
The validity judge module, with described navigation positioning receiver, digital phase discriminator and compensation of ageing module, join respectively, whether effective for judging the standard second pulse signal that navigation positioning receiver transmits, effectively the standard second pulse signal is transferred to digital phase discriminator, and invalid standard second pulse signal sends to the compensation of ageing module;
Digital phase discriminator, with described validity judge module, filter, frequency divider and delayer, join respectively, for the crystal oscillator pps pulse per second signal that receives the standard second pulse signal and transmitted by delayer, and two pps pulse per second signals that receive are carried out to the phase difference comparison to obtain the clock difference signal, afterwards the clock difference signal is exported to filter, control frequency divider output crystal oscillator pps pulse per second signal simultaneously when the clock difference signal stabilization;
Filter, join with described digital phase discriminator and compensation of ageing module respectively, for the noise of filtering clock difference signal, and the clock difference signal after filtering noise exported to the compensation of ageing module;
The compensation of ageing module, with described validity judge module, described filter and pi controller, join respectively, ageing error for compensated voltage controlled oscillator, and the clock difference signal after compensation of ageing is exported to pi controller, and, when receiving invalid standard second pulse signal, extract punctual signal and export to pi controller;
Pi controller, join with described compensation of ageing module and digital to analog converter respectively, for the clock difference signal to after filtering noise and compensation of ageing, carries out smothing filtering, converts the clock difference signal to digital regulated amount afterwards and export to digital to analog converter;
Digital to analog converter, join with described pi controller and voltage controlled oscillator respectively, for the clock difference digital signal to converting digital regulated amount to, carries out exporting to voltage controlled oscillator after digital-to-analogue conversion;
Voltage controlled oscillator, join with described digital to analog converter, frequency divider and frequency multiplier respectively, under the control in the clock difference analog signal to the pulse signal of frequency divider and frequency multiplier output rated frequency;
Frequency divider, with described digital phase discriminator, described voltage controlled oscillator and delayer, join respectively, for will be the crystal oscillator pps pulse per second signal by the pulse signal frequency division of the rated frequency of voltage controlled oscillator output, and under the control of digital phase discriminator to delayer output crystal oscillator pps pulse per second signal;
Delayer, join with described frequency divider and described digital phase discriminator respectively, for the crystal oscillator pps pulse per second signal is carried out exporting to digital phase discriminator after delay process, and exports the clock signal of crystal oscillator pps pulse per second signal after time delay is adjusted simultaneously;
Frequency multiplier, join with described voltage controlled oscillator, for the pulse signal of the rated frequency to voltage controlled oscillator output, increased frequently, for relevant device, uses; And
Power module, join with each part mentioned above, provides each several part required operating voltage.
2. the crystal oscillator based on satellite time transfer according to claim 1 is tamed equipment, it is characterized in that, described navigation positioning receiver is GPS receiver or Beidou satellite receiver.
3. the crystal oscillator based on satellite time transfer according to claim 1 and 2 is tamed equipment, it is characterized in that the pulse signal that the pulse signal of the rated frequency of being exported by voltage controlled oscillator is 10MHz.
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Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
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CN104460311A (en) * | 2014-12-30 | 2015-03-25 | 四川九洲电器集团有限责任公司 | Time calibration method and device |
CN105527833A (en) * | 2016-01-28 | 2016-04-27 | 安徽四创电子股份有限公司 | Beidou GPS dual-mode electric power time synchronizer |
CN106209338A (en) * | 2016-06-28 | 2016-12-07 | 武汉大学 | The frequency stabilization of a kind of DVB pps pulse per second signal and phase correction device and method |
CN107526288A (en) * | 2017-09-05 | 2017-12-29 | 江汉大学 | A kind of time difference correcting device and method based on GPS |
CN109085616A (en) * | 2018-08-30 | 2018-12-25 | 桂林电子科技大学 | A kind of satellite timing method, device and storage medium |
CN112433230A (en) * | 2020-11-05 | 2021-03-02 | 西北工业大学 | High-precision synchronous generation type unmanned aerial vehicle navigation decoy system and synchronous time service method |
CN113078900A (en) * | 2021-03-30 | 2021-07-06 | 中国核动力研究设计院 | System and method for improving clock source performance of DCS (distributed control System) platform of nuclear power plant |
CN113114224A (en) * | 2021-05-10 | 2021-07-13 | 深圳市麒博精工科技有限公司 | Taming frequency-locked loop system based on clock timer |
CN114384791A (en) * | 2021-12-09 | 2022-04-22 | 上海通立信息科技有限公司 | Satellite clock disciplining method, system, medium, and apparatus |
CN115268533A (en) * | 2022-08-02 | 2022-11-01 | 泰斗微电子科技有限公司 | Miniature multi-functional time frequency module |
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2013
- 2013-07-09 CN CN201320406853.6U patent/CN203377841U/en not_active Expired - Lifetime
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
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CN104460311A (en) * | 2014-12-30 | 2015-03-25 | 四川九洲电器集团有限责任公司 | Time calibration method and device |
CN105527833A (en) * | 2016-01-28 | 2016-04-27 | 安徽四创电子股份有限公司 | Beidou GPS dual-mode electric power time synchronizer |
CN106209338A (en) * | 2016-06-28 | 2016-12-07 | 武汉大学 | The frequency stabilization of a kind of DVB pps pulse per second signal and phase correction device and method |
CN106209338B (en) * | 2016-06-28 | 2019-05-24 | 武汉大学 | A kind of frequency stabilization of satellite receiver second pulse signal and phase correction device and method |
CN107526288A (en) * | 2017-09-05 | 2017-12-29 | 江汉大学 | A kind of time difference correcting device and method based on GPS |
CN109085616A (en) * | 2018-08-30 | 2018-12-25 | 桂林电子科技大学 | A kind of satellite timing method, device and storage medium |
CN112433230A (en) * | 2020-11-05 | 2021-03-02 | 西北工业大学 | High-precision synchronous generation type unmanned aerial vehicle navigation decoy system and synchronous time service method |
CN113078900A (en) * | 2021-03-30 | 2021-07-06 | 中国核动力研究设计院 | System and method for improving clock source performance of DCS (distributed control System) platform of nuclear power plant |
CN113078900B (en) * | 2021-03-30 | 2022-07-15 | 中国核动力研究设计院 | System and method for improving performance of clock source of DCS platform of nuclear power plant |
CN113114224A (en) * | 2021-05-10 | 2021-07-13 | 深圳市麒博精工科技有限公司 | Taming frequency-locked loop system based on clock timer |
CN113114224B (en) * | 2021-05-10 | 2022-10-18 | 深圳市麒博精工科技有限公司 | Taming frequency-locked loop system based on clock timer |
CN114384791A (en) * | 2021-12-09 | 2022-04-22 | 上海通立信息科技有限公司 | Satellite clock disciplining method, system, medium, and apparatus |
CN115268533A (en) * | 2022-08-02 | 2022-11-01 | 泰斗微电子科技有限公司 | Miniature multi-functional time frequency module |
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