CN101931481A - IEEE 1588 clock output device and method - Google Patents

Abstract

The invention discloses an IEEE 1588 clock output device and an IEEE 1588 clock output method. The method comprises the following steps that: a 1588 chip outputs a 1PPS signal to a processor by taking a clock signal fed back by an OCXO as a time stamp processing clock and combining the content of a received PTP packet; the processor generates a digital voltage control end adjusting signal according to the 1PPS signal and the clock signal fed back by the OCXO and outputs the digital voltage control end adjusting signal to a digital-to-analog converter; the digital-to-analog converter converts the digital voltage control end adjusting signal into an analog voltage control end adjusting signal and controls the OCXO by using the analog voltage control end adjusting signal; and the OCXO outputs a clock signal with the same phase as the 1PPS signal under the control of the analog voltage control end adjusting signal and feeds the clock signal back to the 1588 chip and the processor. The technical scheme of the invention can save equipment cost and reduce the jitter of a 1PPS clock.

Description

A kind of IEEE 1588 clock output devices and method

Technical field

The present invention relates to the mobile communication technology field, particularly relate to a kind of IEEE 1588 clock output devices and method.

Background technology

At present, TD SDMA inserts (TD-SCDMA, Time Division-Synchronous Code Division Multiple Access) communication technology and has obtained development at a high speed.

In TD-SCDMA, need to realize strict system synchronization, promptly realize the frame synchronization of base station and terminal and access network equipment radio network controller (RNC) and base station synchronously, can finish smoothly to guarantee the sub-district switching.

Synchronisation requirement is to obtain the pulse per second (PPS) (1PPS of time dissemination system by each network element, 1 Pulse Per Second) phase place, do not have the 5ms subframe moment that differs by local high stability crystal oscillator generation with 1PPS, calculate subframe numbers (SFN) simultaneously and finally realize Frequency Synchronization and time synchronized.For time synchronized, the main mode that realizes has: GP S time service, Big Dipper time service and employing time synchronization protocol are (as IEEE 1588 agreements, Network Time Protocol etc.) adjust master clock and, in the absolute moment of calibrating this equipment, realize time synchronized from the time deviation of clock.

At present, the base station equipment among the TD-SCDMA realizes the synchronous of frequency and clock by the IEEE 1588 accurate clock protocols of network measure and control system in network, solved the GPS substitution problem.The basic function of IEEE 1588 accurate clock protocols is to use the most accurate clock and other clocks in the distributed network to keep synchronously, it has defined a kind of accurate clock protocols (PTP, Precision Time Protocol), be used for master clock and synchronous from the submicrosecond level between the clock.

Fig. 1 is the composition schematic diagram of the IEEE 1588 clock output modules in the TS-SCDMA of the prior art base station.As shown in Figure 1, the IEEE 1588 clock output modules in the existing TS-SCDMA base station comprise: temperature compensating crystal oscillator (TCXO) 101,1588 chips 102, processor 103, digital to analog converter (DA) 104 and constant-temperature crystal oscillator (OCXO) 105.Wherein, TCXO 101 stabs processing clock to 1588 chips, 102 output times; 1588 chips 102 receive the clock and the PTP bag of TCXO 101 outputs, and with the clock of TCXO 101 outputs as the timestamp processing clock, in conjunction with the content of PTP bag, to processor 103 output 1PPS signals and day time (TOD, Time Of Day) signals; The TOD signal is the absolute signal constantly of expression; Processor 103 receives the clock signal from the 1PPS signal of 1588 chips 102 and TOD signal and OCXO 105 feedbacks, clock signal to 1PPS signal and OCXO 105 feedbacks is carried out phase demodulation and Filtering Processing, to the digital voltage-controlled end adjustment information of digital to analog converter 104 outputs; The TOD signal that processor 103 receives is kept supplying layer inquiry; Digital to analog converter 104 is adjusted conversion of signals with the voltage-controlled end of numeral and is become the voltage-controlled end adjustment of simulation signal to export to OCXO 105; OCXO 105 adjusts under the control of signal at the voltage-controlled end of simulation, and output is used for the base station with the clock signal of 1PPS signal homophase, and this clock signal feeds back to the input of processor simultaneously.

In IEEE 1588 clock output schemes as shown in Figure 1, used independent TCXO to provide the timestamp processing clock for 1588 chips, the cost of increase and equipment, and TCXO is three grades of clocks, clock accuracy is not high enough, causes the shake of the 1PPS clock that 1588 chip solution separate out excessive.

Summary of the invention

The invention provides a kind of IEEE 1588 clock output devices, this device can be saved equipment cost, reduce the shake of 1PPS clock.

The present invention also provides a kind of IEEE 1588 clock output intents, and this method can be saved equipment cost, be reduced the shake of 1PPS clock.

For achieving the above object, technical scheme of the present invention is achieved in that

The invention discloses a kind of IEEE 1588 clock output devices, this device comprises: 1588 chips, processor, digital to analog converter and constant-temperature crystal oscillator OCXO, wherein:

1588 chips are used to receive the clock signal of accurate clock protocols PTP bag and OCXO feedback, and the clock signal of OCXO feedback as the timestamp processing clock, and in conjunction with the content of PTP bag, is exported pulse per second (PPS) 1PPS signal to processor;

Processor is used to receive the 1PPS signal of 1588 chips output and the clock signal of OCXO feedback, generates digital voltage-controlled end according to the clock signal of 1PPS signal and OCXO feedback and adjusts signal;

Digital to analog converter is used for that the voltage-controlled end of numeral is adjusted conversion of signals and becomes the voltage-controlled end of simulation to adjust signal, adjusts signal with the voltage-controlled end of simulation OCXO is controlled, and makes the clock signal of OCXO output and described 1PP S signal homophase;

OCXO is used for clock signal under the control of the voltage-controlled end adjustment of simulation signal, and this clock signal is fed back to 1588 chips and processor.

The invention also discloses a kind of IEEE 1588 clock output intents, this method comprises:

1588 chips with the clock signal of OCXO feedback as the timestamp processing clock, and in conjunction with the content of the PTP bag that is received, to processor output 1PP S signal;

Processor generates digital voltage-controlled end adjustment signal according to the clock signal of 1PPS signal and OCXO feedback, and the voltage-controlled end of numeral is adjusted signal export to digital to analog converter;

Digital to analog converter is adjusted conversion of signals with the voltage-controlled end of numeral and is become the voltage-controlled end of simulation to adjust signal, adjusts signal with the voltage-controlled end of simulation OCXO is controlled;

OCXO exports the clock signal with described 1PPS signal homophase under the control of the voltage-controlled end adjustment of simulation signal, and this clock signal is fed back to 1588 chips and processor.

By as seen above-mentioned, this 1588 chips of the present invention with the clock signal of OCXO feedback as the timestamp processing clock, and in conjunction with the content of the PTP bag that is received, to processor output 1PPS signal and TOD signal; Processor is according to the 1PPS signal, the clock signal of TOD signal and OCXO feedback generates the voltage-controlled end adjustment of data signal and exports to digital to analog converter, digital to analog converter is adjusted conversion of signals with the voltage-controlled end of numeral and is become the voltage-controlled end of simulation to adjust signal, and adjust signal with the voltage-controlled end of simulation OCXO is controlled, OCXO exports the clock signal with described 1PPS signal homophase under the control of the voltage-controlled end adjustment of simulation signal, and this clock signal is fed back to the technical scheme of 1588 chips and processor, than prior art, because 1588 chips use the clock signal of OCXO feedback as the timestamp processing clock, and no longer need an independent TCXO, therefore saved equipment cost, and the clock of OCXO is than the clock of TCXO, therefore its precision is higher, can effectively reduce the shake of the 1PPS signal that 1588 chip solution separate out.

Description of drawings

Fig. 1 is the composition schematic diagram of the IEEE 1588 clock output modules in the TS-SCDMA of the prior art base station;

Fig. 2 is the composition structure chart of a kind of IEEE 1588 clock output devices of the embodiment of the invention;

Fig. 3 is the flow chart of a kind of IEEE 1588 clock output intents of the embodiment of the invention;

Fig. 4 is the internal structure and the outside connection diagram of the processor 203 in the embodiment of the invention.

Embodiment

Core concept of the present invention is: 1588 chips use the clock signal of OCXO feedback as the timestamp processing clock, and no longer need an independent TCXO, therefore saved equipment cost, and the clock of OCXO is than the clock of TCXO, therefore its precision is higher, can effectively reduce the shake of the 1PPS signal that 1588 chip solution separate out.

In order to make the purpose, technical solutions and advantages of the present invention clearer, describe the present invention below in conjunction with the drawings and specific embodiments.

Fig. 2 is the composition structure chart of a kind of IEEE 1588 clock output devices of the embodiment of the invention.As shown in Figure 2, this device comprises: 1588 chips 202, processor 203, digital to analog converter (AD) 204 and OCXO 205, wherein:

1588 chips 202, be used to receive the clock signal of accurate clock protocols PTP bag and OCXO 205 feedbacks, with the clock signal of OCXO 205 feedback as the timestamp processing clock, and in conjunction with the content of PTP bag, to processor 203 output pulse per second (PPS) 1PPS signals and a day time T OD signal; In the present invention, 1588 chips 202 are identical with 1588 chips 102 of the prior art;

Processor 203, be used to receive the 1PPS signal of 1588 chips, 202 outputs and the clock signal of TOD signal and OCXO 205 feedbacks, clock signal according to 1PPS signal and OCXO 205 feedbacks generates digital voltage-controlled end adjustment signal, and the TOD signal that is received is kept supplying layer inquiry; In one embodiment of the invention, processor 203 is identical with processor of the prior art 103, and processor 203 also can be different with processor of the prior art 103 in other embodiments of the invention, can introduce in detail in follow-up embodiment.

Digital to analog converter 204 is used for that the voltage-controlled end of numeral is adjusted conversion of signals and becomes the voltage-controlled end of simulation to adjust signal, adjusts signal with the voltage-controlled end of simulation OCXO 205 is controlled, and makes the clock signal of OCXO 205 outputs and described 1PPS signal homophase; In the present invention, digital to analog converter 204 is identical with digital to analog converter of the prior art 104;

OCXO 205, are used for clock signal under the control of the voltage-controlled end adjustment of simulation signal, and this clock signal is fed back to 1588 chips 202 and processor 203.In the present invention, OCXO 205 is identical with OCXO of the prior art 105;

In one embodiment of the invention, device shown in Figure 2 further comprises: base station clock generation module (not drawing among Fig. 2), be used to receive the clock signal of OCXO 205 outputs, and be benchmark, produce the clock signal that use the base station with the clock signal of OCXO 205 outputs.For example, produce the base station system master clock, produce TD-SCDMA system-frame timing signal, T_FRAME, T_SLOT etc. signal and coding synchronously, form the system synchronization sequence.

Use the clock source of a slice TCXO in the prior art separately, obtain high steady clock and carry out the extraction of PTP agreement as 1588 chips, but because the precision of TCXO is low, thereby make that the 1PPS clock jitter that parses is excessive.And the above-mentioned solution that proposes among the present invention, with the high steady clock source OCXO of base station clock source as 1588 chips, the 1PPS that uses 1588 chip solution to separate out simultaneously removes to calibrate OCXO by certain filtering and phase discrimination processing, not only save cost, reduced the density of integrated circuit board, and reduced the shake of the 1588 1PPS signals that parse.

Based on the foregoing description, next provide the flow chart of a kind of IEEE 1588 clock output intents among the present invention.

Fig. 3 is the flow chart of a kind of IEEE 1588 clock output intents of the embodiment of the invention.As shown in Figure 3, this method comprises:

Step 301,1588 chips with the clock signal of OCXO feedback as the timestamp processing clock, and in conjunction with the content of the PTP bag that is received, to processor output 1PPS signal;

Step 302, processor generates digital voltage-controlled end adjustment signal according to the clock signal of 1PPS signal and OCXO feedback, and the voltage-controlled end of numeral is adjusted signal export to digital to analog converter;

Step 303, digital to analog converter are adjusted conversion of signals with the voltage-controlled end of numeral and are become the voltage-controlled end of simulation to adjust signal, adjust signal with the voltage-controlled end of simulation OCXO is controlled;

Step 304, OCXO exports the clock signal with described 1PPS signal homophase under the control of the voltage-controlled end adjustment of simulation signal, and this clock signal is fed back to 1588 chips and processor.

Method shown in Figure 3 can further include following steps: the clock signal with OCXO output is a benchmark, produces the clock signal that use the base station.

(1mHz equals 10 to the bandwidth of the phase-locked loop of 1558 chip internals that use in the present embodiment as 100mHz ^-3Hz).Phase-locked loop is uncorrelated or correlation is very weak if the bandwidth of back level phase-locked loop, then can be thought two much smaller than the bandwidth of prime phase-locked loop, can independently consider each loop.Therefore, in embodiments of the present invention, the bandwidth of the phase-locked loop of processor inside is set to be less than or equal to 10mHz.

Fig. 4 is the internal structure and the outside connection diagram of the processor 203 in the embodiment of the invention.As shown in Figure 4, processor 203 comprises: frequency adjustment unit 401, phase discriminator 402, open-loop gain unit 403 and finite impulse response FIR filter 404, wherein:

Frequency adjustment unit 401 is used to receive the clock signal of OCXO 205 feedbacks, exports to phase discriminator after the frequency of the clock signal of OCXO 205 feedbacks is adjusted; Wherein the frequency with the clock signal of OCXO 205 feedback is adjusted into: with the frequency of the clock signal of OCXO 205 feedbacks divided by α * 10 ⁶Be the frequency of adjusted signal, wherein α is the nominal frequency of OCXO 205, and unit is MHz;

Phase discriminator 402 is used for the signal of receive frequency adjustment unit 401 output and the 1PPS signal of 1588 chips, 202 outputs, carries out output signal u after the phase discrimination processing _d(n) give the open-loop gain unit; Wherein, u _d(n)=K _d* θ _e,

θ _eBe the signal of frequency adjustment unit 401 outputs and the 1PPS phase difference between signals of 1588 chips, 202 outputs;

Open-loop gain unit 403 is used to receive the u that phase discriminator is exported _d(n) signal carries out exporting after the gain process

Signal is given FIR filter 404, and wherein gain factor is k;

FIR filter 404 is used for divided ring gain unit output

Signal carries out exporting u after the Filtering Processing _f(n) signal is given digital to analog converter.

Referring to Fig. 4, the nominal frequency of OCXO 205 is α MHz, and its frequency pulling scope is ± β ppmHz 1ppmHz=10 ^-6Hz, the voltage range of its voltage-controlled end is Volt (V).The signal of OCXO 205 outputs is:

The figure place of digital to analog converter 204 is the γ position, and its output voltage is

Volt, so the voltage-controlled end adjustment signal V of simulation (t) of digital to analog converter output is:

Thereby,

$u_o\left(t\right)=\mathrm{\α}\×{10}^6+\frac{\mathrm{\β}\×{10}^6\×\mathrm{\α}\×{10}^6}{2^{\mathrm{\γ}-1}}\×(u_f\left(n\right)-2^{\mathrm{\γ}-1})$

$O_o\left(n\right)=\frac{\mathrm{\β}\×{10}^{-6}\×\mathrm{\α}\×{10}^6}{2^{\mathrm{\γ}-1}}{\∫}_0^n{u}_f\left(\mathrm{\τ}\right)\mathrm{d\τ}$

O _o(n) be the phase place of OCXO output signal.

Phase discriminator is a standard with 1PP S, to the output clock u of OCXO _o(t) count, the output signal that obtains is: u _d(n)=K _d* θ _e

Wherein,

θ _eBe the signal of frequency adjustment unit output and the function of the 1PPS phase difference between signals that 1588 chips are exported.

In one embodiment of the invention, the FIR filter adopts Hamming (Hamming) window FIR filter, the sample frequency Fs=1Hz of its window, cut-off frequency Fc=0.01Hz.In order to obtain more high attenuation, better inhibition noise, just must increase filter order, and allow the sample of transition band as free sample, adopt linear programming to solve the optimized design problem in the present embodiment, draw the filter that adheres to specification by matlab emulation, this filter is 50 rank, its minimum stopband attenuation is-52dB to be given:

The system function of FIR filter is:

$H\left(z\right)=\underset{n=0}{\overset{49}{\mathrm{\Σ}}}h\left(n\right)z^{-n}$

In the formula, H (z) is z ^-1The N-1 order polynomial, it has 49 zero points on the Z plane, and z=0 is the heavy limits in N-1 rank, is positioned at the unit circle of r=1.Because the response of the unit impulse of FIR filter is time-limited, system is stable forever.Good stability and linear phase are the outstanding features of FIR filter.

The open-loop transfer function of whole phase-locked loop shown in Figure 4 is:

$H\left(z\right)=\frac{\mathrm{\α}\×{10}^6}{2\mathrm{\π}}\×\frac{\mathrm{\β}\×\mathrm{\α}}{2^{\mathrm{\γ}-1}}\×k\×\frac{z}{z-1}\×\underset{n=0}{\overset{49}{\mathrm{\Σ}}}h\left(n\right)z^{-n}$

Wherein, k is the gain coefficient of whole phase-locked loop.

The closed loop transfer function, of phase-locked loop is:

$H_B\left(z\right)=\frac{H\left(z\right)}{1+H\left(z\right)G\left(z\right)}=\frac{\frac{\mathrm{k\β}{\mathrm{\α}}^2\×{10}^6}{2^{\mathrm{\γ}}\mathrm{\π}}\×\underset{n=0}{\overset{49}{\mathrm{\Σ}}}h\left(n\right)z^{-n}}{1-z^{-1}+\frac{\mathrm{k\β\α}}{2^{\mathrm{\γ}}\mathrm{\π}}\×\underset{n=0}{\overset{49}{\mathrm{\Σ}}}h\left(n\right)z^{-n}}$

By matlab emulation, obtain working as

Value between [40,100], promptly k gets

Arrive

During numerical value in the scope, can guarantee that the linear discrete closed-loop control system is stable, and gain meets the demands.For example, in one embodiment of the invention

She Ji processor can prevent that clock loop from producing self-excitation by the way.

Need to prove, also comprise other modular units in the processor 203, be used to receive the TOD signal of 1588 chips, 202 outputs, offer the upper strata when inquiring about on the upper strata, this part content is same as the prior art, no longer repeats here.

In sum, this 1588 chips of the present invention with the clock signal of OCXO feedback as the timestamp processing clock, and in conjunction with the content of the PTP bag that is received, to processor output 1PPS signal; Processor generates digital voltage-controlled end according to the clock signal of 1PPS signal and OCXO feedback and adjusts signal and export to digital to analog converter; Digital to analog converter is adjusted conversion of signals with the voltage-controlled end of numeral and is become the voltage-controlled end of simulation to adjust signal, and adjusts signal with the voltage-controlled end of simulation OCXO is controlled; OCXO exports the clock signal with described 1PPS signal homophase under the control of the voltage-controlled end adjustment of simulation signal, and this clock signal is fed back to the technical scheme of 1588 chips and processor, than prior art, because 1588 chips use the clock signal of OCXO feedback as the timestamp processing clock, and no longer need an independent TCXO, therefore saved equipment cost, and the clock of OCXO is than the clock of TCXO, therefore its precision is higher, can effectively reduce the shake of the 1PPS signal that 1588 chip solution separate out.

The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being made, is equal to replacement, improvement etc., all should be included within the scope of protection of the invention.

Claims (10)

1. IEEE 1588 clock output devices is characterized in that this device comprises: 1588 chips, processor, digital to analog converter and constant-temperature crystal oscillator OCXO, wherein:

1588 chips are used to receive the clock signal of accurate clock protocols PTP bag and OCXO feedback, and the clock signal of OCXO feedback as the timestamp processing clock, and in conjunction with the content of PTP bag, is exported pulse per second (PPS) 1PPS signal to processor;

Processor is used to receive the 1PPS signal of 1588 chips output and the clock signal of OCXO feedback, generates digital voltage-controlled end according to the clock signal of 1PPS signal and OCXO feedback and adjusts signal;

Digital to analog converter is used for that the voltage-controlled end of numeral is adjusted conversion of signals and becomes the voltage-controlled end of simulation to adjust signal, adjusts signal with the voltage-controlled end of simulation OCXO is controlled, and makes the clock signal of OCXO output and described 1PPS signal homophase;

OCXO is used for clock signal under the control of the voltage-controlled end adjustment of simulation signal, and this clock signal is fed back to 1588 chips and processor.

2. device according to claim 1 is characterized in that, this device further comprises:

The base station clock generation module is used to receive the clock signal of OCXO output, and is benchmark with the clock signal of OCXO output, produces the clock signal that use the base station.

3. device according to claim 1 is characterized in that,

The bandwidth of the phase-locked loop of described 1588 chip internals is 100mHz, and the bandwidth of the phase-locked loop of described processor inside is less than or equal to 10mHz.

4. according to claim 1 or 3 described devices, it is characterized in that described processor comprises: frequency adjustment unit, phase discriminator, open-loop gain unit and finite impulse response FIR filter, wherein:

The frequency adjustment unit is used to receive the clock signal of OCXO feedback, exports to phase discriminator after the frequency of the clock signal of OCXO feedback is adjusted; Wherein the frequency with the clock signal of OCXO feedback is adjusted into: with the frequency of the clock signal of OCXO feedback divided by α * 10 ⁶, wherein α is the nominal frequency of OCXO, unit is MHz;

Phase discriminator is used for the signal of receive frequency adjustment unit output and the 1PPS signal of 1588 chips output, carries out output signal u after the phase discrimination processing _d(n) give the open-loop gain unit; Wherein, u _d(n)=K _d* θ _e,

θ _eBe the signal of frequency adjustment unit output and the function of the 1PPS phase difference between signals that 1588 chips are exported;

The open-loop gain unit is used to receive the u that phase discriminator is exported _d(n) signal carries out exporting after the gain process Signal is given the FIR filter, and wherein gain factor is k;

The FIR filter is used for divided ring gain unit output

Signal carries out exporting u after the Filtering Processing _f(n) signal is given digital to analog converter.

5. device according to claim 4 is characterized in that,

The gain factor k of described open-loop gain unit gets

Arrive

Numerical value in the scope; Wherein, wherein α is the nominal frequency of OCXO, and unit is MHz, and the frequency pulling scope of OCXO is ± β, and unit is ppmHz, and γ is the figure place of described digital to analog converter;

And/or,

The window sample frequency of described FIR filter is 1Hz, and cut-off frequency is 0.01Hz, and exponent number is 50.

6. IEEE 1588 clock output intents is characterized in that this method comprises:

1588 chips with the clock signal of OCXO feedback as the timestamp processing clock, and in conjunction with the content of the PTP bag that is received, to processor output 1PPS signal;

Processor generates digital voltage-controlled end adjustment signal according to the clock signal of 1PPS signal and OCXO feedback, and the voltage-controlled end of numeral is adjusted signal export to digital to analog converter;

Digital to analog converter is adjusted conversion of signals with the voltage-controlled end of numeral and is become the voltage-controlled end of simulation to adjust signal, adjusts signal with the voltage-controlled end of simulation OCXO is controlled;

OCXO exports the clock signal with described 1PPS signal homophase under the control of the voltage-controlled end adjustment of simulation signal, and this clock signal is fed back to 1588 chips and processor.

7. method according to claim 6 is characterized in that, this method further comprises: the clock signal with OCXO output is a benchmark, produces the clock signal that use the base station.

8. method according to claim 6 is characterized in that, the bandwidth of the phase-locked loop of described 1588 chip internals is 100mHz, and the bandwidth of the phase-locked loop of described processor inside is less than or equal to 10mHz.

9. according to claim 6 or 8 described methods, it is characterized in that described processor generates digital voltage-controlled end according to the clock signal of 1PPS signal and OCXO feedback and adjusts signal, and the voltage-controlled end of numeral adjusted signal export to digital to analog converter and comprise:

After described processor was adjusted the frequency of the clock signal of OCXO feedback, the 1PPS signal of exporting with 1588 chips carried out phase discrimination processing, obtains signal u _d(n);

Wherein, the frequency with the clock signal of OCXO feedback is adjusted into: with the frequency of the clock signal of OCXO feedback divided by α * 10 ⁶, wherein α is the nominal frequency of OCXO, unit is MHz; u _d(n)=K _d* θ _e, θ _eBe the signal of frequency adjustment unit output and the function of the 1PPS phase difference between signals that 1588 chips are exported;

Described processor is to u _d(n) signal carries out gain process and obtains

Signal; Wherein gain factor is k;

Described processor is right The digital voltage-controlled end of output was adjusted signal u after signal carried out Filtering Processing _f(n) give digital to analog converter.

10. method according to claim 9 is characterized in that,

The gain factor k of described open-loop gain unit gets

Arrive

Numerical value in the scope; Wherein, wherein α is the nominal frequency of OCXO, and unit is MHz, and the frequency pulling scope of OCXO is ± β, and unit is ppmHz, and γ is the figure place of described digital to analog converter;

And/or,

Described FIR filter is that 1Hz, cut-off frequency are that 0.01Hz, exponent number are 50 FIR filter for the window sample frequency.

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