CN114384791A - Satellite clock disciplining method, system, medium, and apparatus - Google Patents
Satellite clock disciplining method, system, medium, and apparatus Download PDFInfo
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Abstract
The invention provides a satellite clock disciplining method, a satellite clock disciplining system, a satellite clock disciplining medium and satellite clock disciplining equipment, wherein the satellite clock disciplining system comprises the following steps: step 1: receiving a signal sent by a GPS satellite through a satellite time service receiver, and transmitting the signal to a Field Programmable Gate Array (FPGA); step 2: transmitting a clock signal generated by the constant-temperature voltage-controlled crystal oscillator to the field programmable logic gate array through the clock interface for frequency division to obtain a frequency division signal; and step 3: carrying out phase comparison on the frequency-divided signal and the received signal in a field programmable logic gate array to obtain a phase difference; and 4, step 4: converting the phase difference into a control word of a digital-to-analog converter (DAC), and transmitting the control word to the DAC; and 5: the crystal oscillator frequency is controlled by the voltage-controlled voltage generated by the digital-to-analog converter to form a phase-locked loop, so that the 1Hz frequency of the crystal oscillator is gradually stabilized in a preset range, and the pulse per second which meets the preset condition is obtained. The invention saves cost and improves the precision and stability of clock signals.
Description
Technical Field
The invention relates to the technical field of pulse-per-second signal processing and constant-temperature crystal oscillator calibration, in particular to a satellite clock disciplining method, a satellite clock disciplining system, a satellite clock disciplining medium and satellite clock disciplining equipment.
Background
The information age science and technology is rapidly advanced, and the requirement of people for time precision is continuously improved. High-precision time synchronization systems are increasingly applied to the fields of national defense science and technology, power systems, deep space exploration and the like, and the research of high-stability clock systems becomes more and more important. The clock system of the present day generally adopts the following three schemes:
first, high precision atomic clocks such as hydrogen atomic clock, cesium atomic clock, etc. Atomic clocks have the advantage of good long-term and short-term stability, but have the disadvantages of being very expensive and having high requirements on the use environment, and therefore are only used in national time service laboratories.
And secondly, a high-stability clock based on a GPS. The artificial satellite is provided with high-precision cesium atomic clocks which have high precision, and after the ground receiver receives a GPS signal, the receiver outputs a 1PPS signal after decoding conversion, and the signal has good long-term stability (no accumulated error in a statistical sense). The disadvantage of this scheme is that the 1PPS signal output by the receiver is not stable enough in a short period due to the long-distance transmission of GPS signal in the atmosphere, the system error of the receiver itself, electromagnetic interference and the like, and the precision is only about 10-7.
And thirdly, adopting a constant temperature crystal oscillator as a clock source. The frequency of the constant temperature crystal oscillator has the characteristic of high short-term stability, but the disadvantage is that the frequency and the phase shift along with the increase of time.
Patent document CN101582690A (application number: CN200910032708.4) discloses an oscillator taming system for a satellite clock device in an electric power system, which includes a digital phase discriminator for discriminating a reference 1PPS output by a satellite time service receiver from a 1PPS output by a high-stability crystal oscillator frequency division, the digital phase discriminator is connected with a proportional-integral regulator, a voltage output by the proportional-integral regulator is sent to a voltage-controlled control end of the high-stability crystal oscillator, the voltage-controlled control end finely adjusts an output frequency, and the high-stability crystal oscillator is connected with the frequency divider. However, the patent adopts the output voltage of the proportional-integral regulator, and the use cost is higher compared with the invention.
Disclosure of Invention
In view of the deficiencies in the prior art, it is an object of the present invention to provide a method, system, medium and apparatus for satellite clock disciplining.
The satellite clock disciplining method provided by the invention comprises the following steps:
step 1: receiving a signal sent by a GPS satellite through a satellite time service receiver, and transmitting the signal to a Field Programmable Gate Array (FPGA);
step 2: transmitting a clock signal generated by the constant-temperature voltage-controlled crystal oscillator to the field programmable logic gate array through the clock interface for frequency division to obtain a frequency division signal;
and step 3: carrying out phase comparison on the frequency-divided signal and the received signal in a field programmable logic gate array to obtain a phase difference;
and 4, step 4: converting the phase difference into a control word of a digital-to-analog converter (DAC), and transmitting the control word to the DAC;
and 5: the crystal oscillator frequency is controlled by the voltage-controlled voltage generated by the digital-to-analog converter to form a phase-locked loop, so that the 1Hz frequency of the crystal oscillator is gradually stabilized in a preset range, and the pulse per second which meets the preset condition is obtained.
Preferably, the field programmable gate array FPGA includes a digital phase detector, and the digital phase detector directly converts a phase difference or a time interval between two signals into a digital quantity to output through time interval measurement.
Preferably, the field programmable gate array FPGA includes a loop filter, the loop filter is a digital filter, receives the time interval measurement value of the digital phase discriminator, calculates a digital control quantity by the field programmable gate array, and then converts the digital control quantity by the digital-to-analog converter to output an analog voltage quantity within the voltage control range of the constant temperature voltage controlled crystal oscillator.
Preferably, a satellite time service receiver receives a 1pps signal transmitted by a GPS satellite;
the constant-temperature voltage-controlled crystal oscillator generates a 50M clock signal, and a 1Hz signal is obtained after frequency division is carried out on the field programmable gate array;
and carrying out phase comparison on the received 1pps signal and the frequency-divided 1Hz signal to obtain a phase difference.
The satellite clock disciplining system provided by the invention comprises:
module M1: receiving a signal sent by a GPS satellite through a satellite time service receiver, and transmitting the signal to a Field Programmable Gate Array (FPGA);
module M2: transmitting a clock signal generated by the constant-temperature voltage-controlled crystal oscillator to the field programmable logic gate array through the clock interface for frequency division to obtain a frequency division signal;
module M3: carrying out phase comparison on the frequency-divided signal and the received signal in a field programmable logic gate array to obtain a phase difference;
module M4: converting the phase difference into a control word of a digital-to-analog converter (DAC), and transmitting the control word to the DAC;
module M5: the crystal oscillator frequency is controlled by the voltage-controlled voltage generated by the digital-to-analog converter to form a phase-locked loop, so that the 1Hz frequency of the crystal oscillator is gradually stabilized in a preset range, and the pulse per second which meets the preset condition is obtained.
Preferably, the field programmable gate array FPGA includes a digital phase detector, and the digital phase detector directly converts a phase difference or a time interval between two signals into a digital quantity to output through time interval measurement.
Preferably, the field programmable gate array FPGA includes a loop filter, the loop filter is a digital filter, receives the time interval measurement value of the digital phase discriminator, calculates a digital control quantity by the field programmable gate array, and then converts the digital control quantity by the digital-to-analog converter to output an analog voltage quantity within the voltage control range of the constant temperature voltage controlled crystal oscillator.
Preferably, a satellite time service receiver receives a 1pps signal transmitted by a GPS satellite;
the constant-temperature voltage-controlled crystal oscillator generates a 50M clock signal, and a 1Hz signal is obtained after frequency division is carried out on the field programmable gate array;
and carrying out phase comparison on the received 1pps signal and the frequency-divided 1Hz signal to obtain a phase difference.
According to the present invention, a computer-readable storage medium is provided, in which a computer program is stored, which computer program, when being executed by a processor, carries out the steps of the method.
The satellite clock taming equipment provided by the invention comprises: a controller;
the controller comprises the computer readable storage medium having stored thereon a computer program that, when executed by a processor, performs the steps of the satellite clock discipline method; alternatively, the controller includes the satellite clock discipline system.
Compared with the prior art, the invention has the following beneficial effects:
the invention gives full play to the advantages of good long-term stability of the GPS clock and good short-term stability of the crystal oscillator, reduces the product cost and obtains the clock signal with high stability.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
FIG. 1 is a block diagram of a clock taming system;
FIG. 2 is a circuit diagram of a constant temperature voltage controlled crystal oscillator;
fig. 3 is a schematic diagram of the phase locked loop.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.
Example (b):
referring to fig. 1, 2 and 3, the present invention provides a satellite clock disciplining system, including:
the satellite time service receiver receives a 1pps signal sent by a GPS satellite and sends the signal to the FPGA, a 50M clock signal generated by the constant-temperature voltage-controlled crystal oscillator is sent to the FPGA for frequency division through a clock interface, the 1Hz signal after frequency division and the 1pps signal are compared and measured in the FPGA to obtain time difference, the time difference result is converted into DAC control words and sent to the DAC, the DAC generates voltage-controlled voltage to control the frequency of the crystal oscillator to form a phase-locked loop, the 1Hz frequency of the crystal oscillator is gradually stabilized in an acceptable range, and high-precision stable second pulse is obtained.
In the taming system, the reference input of a phase-locked loop is a 1PPS signal output by a satellite time service receiver, and the other signal which is compared with the phase of the phase-locked loop is a 1Hz signal obtained by frequency division of a constant-temperature voltage-controlled crystal oscillator; the phase discriminator in the phase-locked loop can directly convert the phase difference or the time interval between two signals into digital quantity output through time interval measurement; the loop filter is realized by adopting a digital filter, wherein the filter receives a time interval measurement value of the previous stage, calculates a digital control quantity by the FPGA, and outputs an analog voltage quantity in a voltage control range of the constant-temperature voltage-controlled crystal oscillator through DAC conversion.
The satellite clock disciplining method provided by the invention comprises the following steps: step 1: receiving a signal sent by a GPS satellite through a satellite time service receiver, and transmitting the signal to a Field Programmable Gate Array (FPGA); step 2: transmitting a clock signal generated by the constant-temperature voltage-controlled crystal oscillator to the field programmable logic gate array through the clock interface for frequency division to obtain a frequency division signal; and step 3: carrying out phase comparison on the frequency-divided signal and the received signal in a field programmable logic gate array to obtain a phase difference; and 4, step 4: converting the phase difference into a control word of a digital-to-analog converter (DAC), and transmitting the control word to the DAC; and 5: the crystal oscillator frequency is controlled by the voltage-controlled voltage generated by the digital-to-analog converter to form a phase-locked loop, so that the 1Hz frequency of the crystal oscillator is gradually stabilized in a preset range, and the pulse per second which meets the preset condition is obtained.
The FPGA comprises a digital phase discriminator, and the digital phase discriminator directly converts the phase difference or the time interval between two signals into digital quantity to be output through time interval measurement. The FPGA comprises a loop filter, wherein the loop filter is a digital filter, receives a time interval measurement value of the digital phase discriminator, calculates a digital control quantity by the FPGA, and then converts the digital control quantity by a digital-to-analog converter to output an analog voltage quantity within the voltage control range of the constant-temperature voltage-controlled crystal oscillator. Receiving a 1pps signal sent by a GPS satellite through a satellite time service receiver; the constant-temperature voltage-controlled crystal oscillator generates a 50M clock signal, and a 1Hz signal is obtained after frequency division is carried out on the field programmable gate array; and carrying out phase comparison on the received 1pps signal and the frequency-divided 1Hz signal to obtain a phase difference.
Those skilled in the art will appreciate that, in addition to implementing the systems, apparatus, and various modules thereof provided by the present invention in purely computer readable program code, the same procedures can be implemented entirely by logically programming method steps such that the systems, apparatus, and various modules thereof are provided in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers and the like. Therefore, the system, the device and the modules thereof provided by the present invention can be considered as a hardware component, and the modules included in the system, the device and the modules thereof for implementing various programs can also be considered as structures in the hardware component; modules for performing various functions may also be considered to be both software programs for performing the methods and structures within hardware components.
The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.
Claims (10)
1. A method for satellite clock disciplining, comprising:
step 1: receiving a signal sent by a GPS satellite through a satellite time service receiver, and transmitting the signal to a Field Programmable Gate Array (FPGA);
step 2: transmitting a clock signal generated by the constant-temperature voltage-controlled crystal oscillator to the field programmable logic gate array through the clock interface for frequency division to obtain a frequency division signal;
and step 3: carrying out phase comparison on the frequency-divided signal and the received signal in a field programmable logic gate array to obtain a phase difference;
and 4, step 4: converting the phase difference into a control word of a digital-to-analog converter (DAC), and transmitting the control word to the DAC;
and 5: the crystal oscillator frequency is controlled by the voltage-controlled voltage generated by the digital-to-analog converter to form a phase-locked loop, so that the 1Hz frequency of the crystal oscillator is gradually stabilized in a preset range, and the pulse per second which meets the preset condition is obtained.
2. The satellite clock taming method of claim 1, wherein said field programmable gate array FPGA includes a digital phase detector that directly converts a phase difference or time interval between two signals into a digital quantity output by time interval measurement.
3. The satellite clock taming method according to claim 2, wherein the field programmable gate array FPGA includes a loop filter, the loop filter is a digital filter, receives the time interval measurement value of the digital phase detector, calculates a digital control quantity by the field programmable gate array, and converts the digital control quantity by the digital-to-analog converter to output an analog voltage quantity within the voltage control range of the constant temperature voltage controlled crystal oscillator.
4. The method for taming a satellite clock as claimed in claim 1, wherein a 1pps signal transmitted from a GPS satellite is received by a satellite timing receiver;
the constant-temperature voltage-controlled crystal oscillator generates a 50M clock signal, and a 1Hz signal is obtained after frequency division is carried out on the field programmable gate array;
and carrying out phase comparison on the received 1pps signal and the frequency-divided 1Hz signal to obtain a phase difference.
5. A satellite clock disciplining system, comprising:
module M1: receiving a signal sent by a GPS satellite through a satellite time service receiver, and transmitting the signal to a Field Programmable Gate Array (FPGA);
module M2: transmitting a clock signal generated by the constant-temperature voltage-controlled crystal oscillator to the field programmable logic gate array through the clock interface for frequency division to obtain a frequency division signal;
module M3: carrying out phase comparison on the frequency-divided signal and the received signal in a field programmable logic gate array to obtain a phase difference;
module M4: converting the phase difference into a control word of a digital-to-analog converter (DAC), and transmitting the control word to the DAC;
module M5: the crystal oscillator frequency is controlled by the voltage-controlled voltage generated by the digital-to-analog converter to form a phase-locked loop, so that the 1Hz frequency of the crystal oscillator is gradually stabilized in a preset range, and the pulse per second which meets the preset condition is obtained.
6. The satellite clock taming system of claim 5, wherein said field programmable gate array FPGA comprises a digital phase detector that directly converts the phase difference or time interval between two signals into a digital quantity output by time interval measurement.
7. The satellite clock taming system according to claim 6, wherein the field programmable gate array FPGA includes a loop filter, the loop filter is a digital filter, receives the time interval measurement value of the digital phase detector, calculates a digital control quantity by the field programmable gate array, and converts the digital control quantity by the digital-to-analog converter to output an analog voltage quantity within the voltage control range of the constant temperature voltage controlled crystal oscillator.
8. The satellite clock disciplining system as claimed in claim 5, wherein the 1pps signal transmitted from the GPS satellite is received by the satellite timing receiver;
the constant-temperature voltage-controlled crystal oscillator generates a 50M clock signal, and a 1Hz signal is obtained after frequency division is carried out on the field programmable gate array;
and carrying out phase comparison on the received 1pps signal and the frequency-divided 1Hz signal to obtain a phase difference.
9. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 4.
10. A satellite clock disciplining apparatus, characterized by comprising: a controller;
the controller comprising the computer readable storage medium of claim 9 having a computer program stored thereon which, when executed by a processor, performs the steps of the satellite clock disciplining method of any one of claims 1 to 4; alternatively, the controller comprises the satellite clock discipline system as claimed in any one of claims 5 to 8.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116203823A (en) * | 2023-02-16 | 2023-06-02 | 深圳市中冀联合技术股份有限公司 | High-precision clock taming method |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11174170A (en) * | 1997-12-10 | 1999-07-02 | Japan Radio Co Ltd | Frequency standard device |
| US6078224A (en) * | 1997-08-18 | 2000-06-20 | Advantest Corp. | Frequency standard generator |
| JP2009222486A (en) * | 2008-03-14 | 2009-10-01 | Kinkei System Corp | Time device and portable electronic apparatus |
| CN101582690A (en) * | 2009-06-26 | 2009-11-18 | 江苏北斗科技有限公司 | Oscillator disciplining system for satellite clock device of power system |
| CN101799658A (en) * | 2010-02-24 | 2010-08-11 | 华中科技大学 | Backup clock calibrated by GPS |
| CN102315927A (en) * | 2011-06-30 | 2012-01-11 | 大唐移动通信设备有限公司 | Clock synchronization device and method |
| CN102436174A (en) * | 2011-10-26 | 2012-05-02 | 东莞市泰斗微电子科技有限公司 | Method and corresponding device for taming crystal oscillation frequency of time-keeping device |
| CN203377841U (en) * | 2013-07-09 | 2014-01-01 | 石家庄市经纬度科技有限公司 | Satellite-based crystal oscillator taming apparatus for time service |
| CN105892280A (en) * | 2016-04-08 | 2016-08-24 | 武汉中原电子集团有限公司 | Satellite time service device |
| CN113078900A (en) * | 2021-03-30 | 2021-07-06 | 中国核动力研究设计院 | System and method for improving clock source performance of DCS (distributed control System) platform of nuclear power plant |
-
2021
- 2021-12-09 CN CN202111501223.2A patent/CN114384791A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6078224A (en) * | 1997-08-18 | 2000-06-20 | Advantest Corp. | Frequency standard generator |
| JPH11174170A (en) * | 1997-12-10 | 1999-07-02 | Japan Radio Co Ltd | Frequency standard device |
| JP2009222486A (en) * | 2008-03-14 | 2009-10-01 | Kinkei System Corp | Time device and portable electronic apparatus |
| CN101582690A (en) * | 2009-06-26 | 2009-11-18 | 江苏北斗科技有限公司 | Oscillator disciplining system for satellite clock device of power system |
| CN101799658A (en) * | 2010-02-24 | 2010-08-11 | 华中科技大学 | Backup clock calibrated by GPS |
| CN102315927A (en) * | 2011-06-30 | 2012-01-11 | 大唐移动通信设备有限公司 | Clock synchronization device and method |
| CN102436174A (en) * | 2011-10-26 | 2012-05-02 | 东莞市泰斗微电子科技有限公司 | Method and corresponding device for taming crystal oscillation frequency of time-keeping device |
| CN203377841U (en) * | 2013-07-09 | 2014-01-01 | 石家庄市经纬度科技有限公司 | Satellite-based crystal oscillator taming apparatus for time service |
| CN105892280A (en) * | 2016-04-08 | 2016-08-24 | 武汉中原电子集团有限公司 | Satellite time service device |
| CN113078900A (en) * | 2021-03-30 | 2021-07-06 | 中国核动力研究设计院 | System and method for improving clock source performance of DCS (distributed control System) platform of nuclear power plant |
Non-Patent Citations (1)
| Title |
|---|
| 柯熙政: "《多模式多尺度数据融合理论及其应用》", 北京：科学出版社, pages: 51 - 56 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116203823A (en) * | 2023-02-16 | 2023-06-02 | 深圳市中冀联合技术股份有限公司 | High-precision clock taming method |
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