CN113114224A - Taming frequency-locked loop system based on clock timer - Google Patents

Taming frequency-locked loop system based on clock timer Download PDF

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Publication number
CN113114224A
CN113114224A CN202110506027.8A CN202110506027A CN113114224A CN 113114224 A CN113114224 A CN 113114224A CN 202110506027 A CN202110506027 A CN 202110506027A CN 113114224 A CN113114224 A CN 113114224A
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clock
timer
cpu
frequency
control system
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CN113114224B (en
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戴仁寿
林楠林
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Shenzhen Qibo Jinggong Technology Co ltd
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Shenzhen Qibo Jinggong Technology Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L1/00—Stabilisation of generator output against variations of physical values, e.g. power supply
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

The invention discloses a taming frequency locking loop system based on a clock timer, which comprises a clock selection switch, a CPU clock control system, a DAC converter, a voltage-controlled crystal oscillator to be taminated and a controllable programming clock generator, wherein the clock selection switch is connected with the CPU clock control system; the CPU clock control system comprises a clock selection controller, a timer driven by an external clock, a timer driven by an internal clock, a clock input device and a CPU processor; the clock selection switch inputs a clock signal to the CPU clock control system, and the CPU clock control system controls the voltage-controlled crystal oscillator to be tamed through the DAC; the voltage-controlled crystal oscillator to be tamed inputs a clock signal to a clock input device through a controllable programming clock generator; the CPU clock control system controls the controllable programming clock generator. The invention aims to provide a taming frequency locking loop system based on a clock timer, which has the advantages of low cost, strong flexibility, high reliability and simple structure.

Description

Taming frequency-locked loop system based on clock timer
Technical Field
The invention relates to the technical field of electronics, in particular to a taming frequency locking loop system based on a clock timer.
Background
Currently, many electronic systems require a clock signal of precise frequency. Such electronic systems include precision test equipment, communications equipment, navigation, aerospace and military equipment, and the like.
Such clock signals with precise frequencies are all from a Voltage Controlled Oscillator (VCO). These voltage Controlled Crystal oscillators may be in the form of an OCXO (Oven Controlled Crystal Oscillator) or a Temperature Compensated Crystal Oscillator (TCXO). These oscillators, regardless of how well their short term stability is, suffer from long term aging and frequency drift problems. This frequency shift is an irreversible physical property of the material. Under the conditions of wide frequency working range or poor working conditions (high temperature and low temperature), the frequency shift phenomenon is more serious, and the normal operation of an electronic system is influenced.
The precise frequency crystal oscillator which has high frequency and wide adjustable frequency working range is very valuable. It is difficult to use for commercial products.
However, it is known that clock signals of global positioning systems such as Beidou, GPS and the like are generated by atomic clocks, and are very accurate and stable. In addition, a fixed low frequency (10MHz signal) accurate and stable signal source is also relatively easily available. Both of these are very good reference frequency standards.
In fact, any electronic system requiring a precise frequency signal must contain a clock disciplining mechanism. This disciplined mechanism includes a phase tracking loop (phase tracking loop) that continuously detects the phase difference between the local VCO output signal and the external input reference signal.
The phase difference information modulates the width of a pulse signal, and the pulse signals with different widths enter a filter, and the output of the filter is a voltage signal for controlling the VCO. The purpose of this control loop is to make the phase difference of the two clock signals constant over time.
If a digital implementation is used, the time difference between the upper or lower edges of the two clocks is measured by a high speed counter, which itself may be implemented in an FPGA. The result of the counter is output to a microcontroller. The micro controller calculates a voltage correction value by observing the slope of the result of the counter along with the change of time, and outputs a new VCO control voltage through an analog-to-digital converter.
The above domestication mechanism is a Frequency-locked Loop (FLL). The externally input reference signal may be a 10MHz signal generated by an accurate signal source, or may be a pulse per second (1 PPS) generated by a global positioning system receiver such as a compass, a GPS, or the like.
Designing the above clock signal disciplining system is an important and obscure "cold" industry. The design knowledge and concept followed by the industry history are hard to be mastered by the "layman" at first sight. And increases the cost and complexity of the hardware system.
Chinese patent application No. 202020446274.4, application date: 31/03/2020, open: the patent names are as follows, namely, 10 and 23 days in 2020: the invention discloses a clock taming system of a computer and equipment with a hardware triggering function, which comprises a signal generating module, a clock training module and a clock training module, wherein the signal generating module comprises a connecting port and a signal port; the connection port and the signal port are both arranged on the signal generation module, and the signal generation module is used for generating an oscillation signal; a computer module connected to the signal generation module and receiving the communication packet transmitted by the signal generation module; the equipment module is connected with the signal generation module, can receive the oscillation signal sent by the signal generation module and is triggered by the oscillation signal; and the sensor module is connected with the computer module and is used for identifying the target object. The invention synchronizes the host computer of the sensor without a hardware triggering function with the equipment with the hardware triggering function through the signal generating module, thereby realizing the functions of distance measurement and the like of the sensor.
Although the above patent document discloses a clock taming system including a computer and a device with a hardware trigger function, the system has insufficient detection accuracy, poor reliability, poor sensitivity, and high cost.
Disclosure of Invention
In view of the above, the present invention provides a clock timer-based frequency locked loop disciplined system with low cost, high flexibility, high reliability and simple structure.
In order to realize the purpose of the invention, the following technical scheme can be adopted:
a disciplined frequency locking loop system based on a clock timer comprises a clock selection switch, a CPU clock control system, a DAC converter, a voltage-controlled crystal oscillator to be disciplined and a controllable programming clock generator; the CPU clock control system comprises a clock selection controller, a timer driven by an external clock, a timer driven by an internal clock, a clock input device and a CPU processor;
the clock selection switch is used for controlling the selection of a reference clock signal source; the CPU clock control system is used for controlling and outputting clock information; the DAC converter is used for converting digital signals into analog signals; the voltage-controlled crystal oscillator to be tamed is used for generating a crystal oscillator signal; the controllable programming clock generator is used for inputting a reference clock frequency;
the clock selection controller is used for controlling the potential of the clock selection switch; the external clock-driven timer and the internal clock-driven timer are used for measuring the frequency of the clock signal; the CPU processor is used for analyzing and processing the metering value of the timer; the clock input device is used for a clock interface circuit of a CPU clock control system;
the clock selection switch inputs a clock signal to the CPU clock control system, and the CPU clock control system controls the voltage-controlled crystal oscillator to be tamed through the DAC; the voltage-controlled crystal oscillator to be tamed inputs a clock signal to a clock input device through a controllable programming clock generator;
the clock selection controller and the timer driven by the external clock respectively receive clock signals input by the clock selection switch, the clock selection controller and the timer driven by the external clock input the clock signals to the CPU processor, and the CPU processor controls the voltage-controlled crystal oscillator to be tamed through the DAC; the voltage-controlled crystal oscillator to be tamed inputs a clock signal to a clock input unit through a controllable programming clock generator, the clock input unit provides a clock driving signal for an internal clock-driven timer, and the internal clock-driven timer inputs the clock signal to the CPU processor;
the CPU clock control system controls the controllable programming clock generator.
The invention also comprises a sine wave signal source and a sine wave to square wave circuit, wherein the sine wave signal source inputs a clock signal to the clock selection switch through the sine wave to square wave circuit.
The clock frequency module inputs a pulse-per-second clock signal to the clock selection switch.
The clock frequency module comprises a GPS clock module or a Beidou clock module.
The CPU processor is a TMS320C6657 chip.
The CPU processor includes memory for DMA ingestion.
The CPU control system also comprises a DAC interface, and the CPU processor controls the DAC converter through the DAC interface.
The controllable programming clock generator includes a clock output for outputting a clock frequency signal.
The invention has the beneficial effects that: 1) the invention has reasonable structure and lower cost; 2) the invention has strong flexibility, high stability and strong reliability; 3) the invention outputs the clock signal to the CPU processor through the clock input device, and controls the controllable programming clock generator through the CPU processor, thereby simplifying the circuit structure and improving the working efficiency; the invention has wide application field and is suitable for general popularization.
Drawings
FIG. 1 is a block diagram of a clock timer based taming frequency locked loop system according to an embodiment of the present invention;
FIG. 2 is a logic diagram of a clock timer based tame frequency locked loop system according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and embodiments thereof.
Example 1
Referring to fig. 1, the disciplined frequency-locked loop system based on the clock timer comprises a clock selection switch 3, a CPU clock control system 4, a DAC converter 5, a voltage-controlled crystal oscillator 6 to be disciplined, and a controllable programming clock generator 7; the CPU clock control system 4 includes a clock selection controller 41, an external clock-driven timer 42, an internal clock-driven timer 43, a clock input 44, a CPU processor 46;
the clock selection switch 3 is used for controlling the selection of a reference clock signal source; the CPU clock control system 4 is used for controlling and outputting clock information; the DAC converter 5 is used for converting digital signals into analog signals; the voltage-controlled crystal oscillator 6 to be tamed is used for generating a crystal oscillator signal; the controllable programming clock generator 7 is used for inputting a reference clock frequency;
the clock selection controller 41 is used for controlling the potential of the clock selection switch; the external clock-driven timer 42 and the internal clock-driven timer 43 for measuring the frequency of the clock signal; the CPU processor 46 is configured to analyze a metering value of the processing timer; the clock input device 44 is used for a clock interface circuit of a CPU clock control system;
the clock selection switch 3 inputs a clock signal to the CPU clock control system 4, and the CPU clock control system 4 controls the voltage-controlled crystal oscillator 6 to be tamed through a DAC (digital-to-analog converter) 5; the voltage-controlled crystal oscillator 6 to be tamed inputs a clock signal to a clock input device 44 through a controllable programming clock generator 7;
the clock selection controller 41 and the external clock-driven timer 42 respectively receive the clock signal input by the clock selection switch 3, the clock selection controller 41 and the external clock-driven timer 42 input the clock signal to the CPU processor 46, and the CPU processor 46 controls the voltage-controlled crystal oscillator 6 to be tamed through the DAC converter 5; the voltage controlled crystal oscillator 6 to be tamed inputs a clock signal to a clock input unit 44 through a controllable programming clock generator 7;
the clock input 44 provides a clock driving signal to the internal clock driven timer 42, and the internal clock driven timer 42 inputs a clock signal to the CPU processor 46;
the CPU clock control system 4 controls the controllable program clock generator 7.
In this embodiment, the clock selection switch 3 inputs an external reference clock signal to the CPU clock control system 4;
in this embodiment, the CPU clock control system 4 is configured to discipline the voltage controlled crystal oscillator 6, so that the frequency output generated by the voltage controlled crystal oscillator is locked to the external reference clock frequency.
In this embodiment, the controllable program clock generator 12 is used to change the frequency of the reference input clock to other frequencies; and the controllable program clock generator 12 can generate outputs of various frequency signals including clock signals required by the CPU clock control system 4 itself.
In this embodiment, the voltage controlled crystal oscillator 10 to be disciplined generates clock signals with different frequencies through the controllable programming clock generator 12, some of which are used as outputs and one of which is used as a clock input of the CPU processor 7;
in this embodiment, the voltage-controlled crystal oscillator 10 to be disciplined generates various frequency signals through the controllable programming clock generator 12, including the clock signal required by the CPU clock control system 4 itself;
in this embodiment, the clock selection controller 41 inputs an external reference clock signal to an external clock-driven timer 42, which measures the frequency of the external reference signal; meanwhile, the timer 42 driven by the internal CPU clock measures the clock frequency of the CPU clock control system 4; by comparing the values of the two timers, the CPU clock control system 4 analyzes a new control voltage required by the voltage controlled crystal oscillator 6 to be disciplined; the CPU clock control system 4 sends the analyzed control voltage to the voltage controlled crystal oscillator 6 to be acclimatized through a DAC (digital-to-analog converter) 5;
the voltage-controlled crystal oscillator 6 to be tamed generates various frequency signals through a controllable programming clock generator 12, and the frequency signals comprise clock signals required by the CPU clock control system 4;
in this embodiment, the present invention preferably further includes a sine wave signal source 1 and a sine wave to square wave circuit 2, where the sine wave signal source 1 inputs a clock signal to the clock selection switch 3 through the sine wave to square wave circuit 2.
The sine wave-to-square wave circuit 2 is a chip with the model number DIN 44-IBF.
The invention also comprises a clock frequency module 9, wherein the clock frequency module 9 inputs a pulse per second signal to the clock selection switch 3.
Preferably, the clock frequency module 9 includes the GPS clock module 91 or the beidou clock module 92.
In this embodiment, preferably, the CPU 46 is a chip with a model number of TMS320C 6657.
Further, the CPU processor 46 preferably includes a DMA ingest memory 45, and the DMA ingest memory 45 is used to store the clock information analyzed and processed by the CPU processor 46.
In this embodiment, it is further preferable that the clock input device 44 is a chip with a model number DS12C 887.
The external clock-driven timer 42 drives the internal clock-driven timer by externally input clock information, and then inputs the clock information to the CPU processor 46.
The internal clock driving timer 43 is supplied with a clock driving signal from a clock input 44, and the internal clock driving timer 44 inputs clock information to the CPU processor 46.
In this embodiment, the CPU control system 4 further includes a DAC interface 47, and the CPU processor 46 controls the DAC converter 5 through the DAC interface 47.
In this embodiment, the controllable programming clock generator 7 may preferably select a chip with model number MS 5351M.
In this embodiment, it is further preferable that the controllable programming clock generator 7 includes a clock output device 8, and the clock output device 8 is configured to output clock signals with various frequencies.
The clock outputter 8 may output the output clock signal to other electronic circuits or electronic devices.
In this embodiment, the sine wave provided by the sine wave signal source 1 is converted into a square wave by the sine wave-to-square wave circuit 2, and then the clock selection switch 3 selects the square wave to drive the external clock-driven timer 41.
Or the 1-pps second pulse signal generated by the GPS clock module 91 or the beidou clock module 92 drives the timer 42 driven by the external clock after being selected by the clock selection switch 3.
The clock input device 44 is from an external controllable program clock generator 7, and the reference clock signal of the controllable program clock generator 7 can be provided by a reference clock input device, which can provide the reference clock signal from the voltage controlled crystal oscillator 6 to be disciplined.
The voltage-controlled crystal oscillator 6 to be disciplined is a device which needs to be disciplined in the present invention.
In this embodiment, the driving signal of the internal clock driven timer 43 is provided by the clock input 44.
Referring to FIG. 2, FIG. 2 is a diagram illustrating the operational logic of the present invention;
the present system sets the upper modulus of the external clock driven timer 41 to the external reference signal frequency multiplied by an "integration" time. For example, when the frequency of the externally input reference signal is 10MHz, the integration time is 3 seconds, and then the upper limit mode value of the timer 5 driven by the external clock is 30000000-1.
As a result of this arrangement, every 3 seconds the external clock-driven timer 5 will generate a DMA trigger event and also an interrupt response request. The timer is driven by an externally input reference clock.
The present system sets the upper modulus of the internal clock driven timer 42 to a 32-bit or 64-bit maximum. The internal clock driven timer 42 is driven by the internal CPU clock control system 4, and the CPU clock control system 4 clocks the final slave voltage controlled oscillator 6 to be disciplined.
The present system sets the DMA response of the external clock driven timer 42 to: each DMA event trigger forces the DMA engine to automatically read the value of the clocked timer 41 at that moment and store the read value in a circular buffer.
The interrupt response of the external clock driven timer 42 is set to: for each interrupt request, the software will calculate the difference between the count value of the most recent internal clock-driven timer 43 in the circular buffer and the previous count value.
This difference reflects the difference between the chip clock frequency of the clock input 44 and the external reference frequency.
Assuming that the difference between the count values is dC. if the clock input 44 chip clock is perfectly synchronized with the external reference clock, then the dC value has an ideal value, which is assumed to be dC _ ideal.
Assuming that the theoretical frequency of the voltage controlled crystal 6 to be acclimated is Fc (for example, Fc is 25MHz, corresponding to a crystal oscillator of 25 MHz), and assuming that the frequency offset value of the crystal oscillator is df, the relative frequency offset of the voltage controlled crystal 10 to be acclimated is: fr ═ df/Fc.
This relative frequency offset fr is generally expressed in ppm (parts per million) or ppb (parts per billion).
A simple mathematical derivation can prove the following relationship:
fr＝df/Fc＝(dC_ideal–dC)/(dC_ideal)＝1–(dC/dC_ideal)
the DAC correction value of the voltage-controlled crystal oscillator 10 to be disciplined is:
DAC_correction＝alpha*Scale*fr
where 0< alpha <1 is a damping coefficient for keeping the control loop stable, and Scale is a coefficient related to the adjustment sensitivity of the crystal oscillator frequency to the voltage, that is: each time the DAC is shifted by one scale, the relative offset value is determined.
The interrupt response routine will send the following values to the DAC:
DAC_new_value＝DAC_old_value+DAC_correction
the above steps complete one correction of the control voltage of the voltage controlled crystal oscillator 10 to be disciplined.
The reason why the DMA engine is used to read the value of the internal clock-driven timer 43 instead of reading the value of the internal clock-driven timer 43 in the interrupt response routine is as follows: the work of the DMA engine is already in hardware on the design of the CPU processor and is not influenced by the uncertainty of the software operation on the interrupt response processing. This ensures that the count value read by the internal clock-driven timer 43 does not contain any "jitter" (jitter) caused by the running of the CPU software.
The invention aims to remove the mysterization in the industry and provide a simple, firm and flexible tame frequency-locked loop system based on a clock timer. The invention only needs a microprocessor of a clock driving timer, but does not need any extra hardware or special filter design and the like, thereby greatly simplifying the circuit structure, greatly reducing the cost and being suitable for general popularization.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.

Claims (8)

1. A taming frequency-locked loop system based on a clock timer is characterized in that: the device comprises a clock selection switch, a CPU clock control system, a DAC converter, a voltage-controlled crystal oscillator to be tamed and a controllable programming clock generator; the CPU clock control system comprises a clock selection controller, a timer driven by an external clock, a timer driven by an internal clock, a clock input device and a CPU processor;
the clock selection switch is used for controlling the selection of a reference clock signal source; the CPU clock control system is used for controlling and outputting clock information; the DAC converter is used for converting digital signals into analog signals; the voltage-controlled crystal oscillator to be tamed is used for generating a crystal oscillator signal; the controllable programming clock generator is used for inputting a reference clock frequency;
the clock selection controller is used for controlling the potential of the clock selection switch; the external clock-driven timer and the internal clock-driven timer are used for measuring the frequency of the clock signal; the CPU processor is used for analyzing and processing the metering value of the timer; the clock input device is used for a clock interface circuit of a CPU clock control system;
the clock selection switch inputs a clock signal to the CPU clock control system, and the CPU clock control system controls the voltage-controlled crystal oscillator to be tamed through the DAC; the voltage-controlled crystal oscillator to be tamed inputs a clock signal to a clock input device through a controllable programming clock generator;
the clock selection controller and the timer driven by the external clock respectively receive clock signals input by the clock selection switch, the clock selection controller and the timer driven by the external clock input the clock signals to the CPU processor, and the CPU processor controls the voltage-controlled crystal oscillator to be tamed through the DAC; the voltage-controlled crystal oscillator to be tamed inputs a clock signal to a clock input unit through a controllable programming clock generator, the clock input unit provides a clock driving signal for an internal clock-driven timer, and the internal clock-driven timer inputs the clock signal to the CPU processor;
the CPU clock control system controls the controllable programming clock generator.
2. The clock-timer-based taming frequency-locked loop system of claim 1, wherein: the clock selection switch is connected with the sine wave signal source and the sine wave-to-square wave circuit, and the clock selection switch is connected with the sine wave signal source and the sine wave-to-square wave circuit.
3. The clock-timer-based taming frequency-locked loop system of claim 1, wherein: the clock frequency module inputs a pulse-per-second clock signal to the clock selection switch.
4. The clock-timer-based taming frequency-locked loop system of claim 3, wherein: the clock frequency module comprises a GPS clock module or a Beidou clock module.
5. The clock-timer-based taming frequency-locked loop system of claim 1, wherein: the CPU processor is a TMS320C6657 chip.
6. The clock-timer-based taming frequency-locked loop system of claim 1 or 5, wherein: the CPU processor includes memory for DMA ingestion.
7. The clock-timer-based taming frequency-locked loop system of claim 6, wherein: the CPU control system also comprises a DAC interface, and the CPU processor controls the DAC converter through the DAC interface.
8. The clock-timer-based taming frequency-locked loop system of claim 1, wherein: the controllable programming clock generator includes a clock output for outputting a clock frequency signal.
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