CN203224746U

CN203224746U - Real-time parallel multichannel signal acquisition system

Info

Publication number: CN203224746U
Application number: CN2013202422422U
Authority: CN
Inventors: 李立凯; 杨宁; 杨帆; 郭晨鲜; 齐小文; 张璐璐; 王小琼
Original assignee: Zhongzhou University
Current assignee: Zhongzhou University
Priority date: 2013-05-08
Filing date: 2013-05-08
Publication date: 2013-10-02
Anticipated expiration: 2023-05-08

Abstract

The utility model relates to a real-time parallel multichannel signal acquisition system, and can effectively solve the problems of being high in cost, long in period and difficult in implementation in multichannel type signal acquisition of a signal acquisition system based on an industrial personal computer. The technical scheme for solving the problems is that the real-time parallel multichannel signal acquisition system comprises a sensor, an amplifier, a signal conditioner, an industrial personal computer and a display, the sensor is connected with the input end of the signal conditioner through the amplifier, the output end of the signal conditioner is connected with the input end of a multichannel extension module, the output end of the multichannel extension module is connected with the input end of a data acquisition card in the industrial personal computer, and the industrial personal computer is connected with the display. The real-time parallel multichannel signal acquisition system is novel and unique in structure, simple and reasonable, low in cost, and good in using effect, and has good social and economic benefits.

Description

A kind of real-time parallel multiplexed signal sampling system

Technical field

The utility model relates to data acquisition system (DAS), particularly a kind of real-time parallel multiplexed signal sampling system.

Background technology

Data acquisition system (DAS) (containing high-speed data acquisition card) based on industrial computer (PC) is widely used in places such as laboratory, production scene, manufacturing shop, and data acquisition system (DAS) is made up of four parts usually: sensor and pre-amplification circuit thereof, change-over circuit, interface circuit and computing machine host computer are handled.

Because microcomputer is universal day by day in recent years, and cheap; Electronics is integrated to have remarkable progress with weak signal processing aspect, and the high-speed data acquisition performance is very high, and price has also reduced much, also very convenient based on the high-speed data acquisition card use of PCI, PCI_E on computing machine and the mainboard and PXI interface.So consider that from applicability and the generalization angle of system at present, most of computer based data acquisition system (DAS)s are designed to computer-oriented main board bus expansion board form.

In four parts based on the data acquisition system (DAS) of industrial computer, sensor and preposition discharge road thereof and signal condition change-over circuit be relative fixed and basic forming all; Host computer handle to be gone up the early stage Visual of employing Basic(and is called for short VB) programming language more, use Microsoft Visual C++(to be called for short VC++) programming language handle use comparatively general.But use the VC++ language in programming, comparatively complicated, very not attractive in appearance on man-machine interface yet; Interface problem mainly according to industrial computer on mainboard expansion card type and signal-processing board interface type.Carrying out the multichannel model when gathering based on industrial computer machine signal acquiring system, high-speed data acquisition card is generally about the 8-64 paths, if acquisition channel more than 200 the tunnel, is being gathered in real time and will bothered very much, greatly increase project cost and design cycle, even can't realize.

Summary of the invention

At above-mentioned situation, for overcoming the defective of prior art, the purpose of the utility model just provides a kind of real-time parallel multiplexed signal sampling system, can effectively solve based on industrial computer machine signal acquiring system cost height, cycle when carrying out multichannel model signals collecting longly, realizes the problem of difficulty.

The technical scheme that the utility model solves is, comprise sensor, amplifier, signal conditioner, industrial computer and display, sensor links to each other with the input end of signal conditioner through amplifier, the output terminal of signal conditioner links to each other with the input end of multichannel expansion module, the input end of the data collecting card on the output terminal of multichannel expansion module and the industrial computer links to each other, and industrial computer links to each other with display.

The utility model novel structure uniqueness, advantages of simple, cost is low, and result of use is good, and good society and economic benefit are arranged.

Description of drawings

Fig. 1 is that structure of the present utility model connects frame figure.

(wherein n is progressive whole number to Fig. 2, i.e. n=1,2,3,4,5,6,7,8,9 for the utility model multichannel expansion module structure connects frame figure ...).

Embodiment

Below in conjunction with accompanying drawing embodiment of the present utility model is described in further detail.

Provided by Fig. 1,2, the utility model comprises sensor, amplifier, signal conditioner, industrial computer and display, sensor 1 links to each other through the input end of amplifier 2 with signal conditioner 3, the output terminal of signal conditioner 3 links to each other with the input end of multichannel expansion module 4, the input end of the data collecting card on the output terminal of multichannel expansion module (claiming the FPGA module again) 4 and the industrial computer 5 links to each other, and industrial computer 5 links to each other with display 6.

In order to guarantee result of use, described multichannel expansion module 4 is made of some (n) individual identical expanding element, each unit comprises times frequency module 7, clock synchronization module 9 and the igniter module 8 that links to each other successively, pulse width detection module 10, first latch 11, parallel serial conversion module 12, second latch 13, data cache device 14, times frequency module 7 connects igniter module 8, pulse width detection module 10 and data cache device 14 respectively, and clock synchronization module 9 connects first latch 11, second latch 13 and data cache device 14 respectively.

Described amplifier 2 is made of the amplifying circuit in housing and the housing; The width detection that described pulse width detection module 10 is realized each road pulse signal; Described clock synchronization module 9 produces sequential with clock signal and measured pulse signal, when the measured signal high level finishes, produce three clock signals, be synchronized with external reference clock respectively, and lag behind a reference clock cycle mutually between each synchronous clock, these three signals are respectively applied to institute and deposit and zero clearing; Parallel serial conversion module 12 is parallel signal pulse width detection architecture, forms a tandem queue by coding, is gathered by data collecting card during through the output of data cache device; Described data cache device 14 is a kind of data cache device of first-in first-out (claiming high speed FIFO again); Data collecting card on the described industrial computer 5 is high-speed data acquisition card.

Reference numeral 7n among Fig. 2,8n, 9n, 10n, 11n, 12n, 13n, 14n represents a times frequency module respectively, connect igniter module, clock synchronization module, the pulse width detection module, first latch, parallel serial conversion module, second latch and data cache device, respectively with times frequency module 7, connect igniter module 8, clock synchronization module 9, pulse width detection module 10, first latch 11, parallel serial conversion module 12, second latch 13 is corresponding with data cache device 14, wherein n is progressive whole number, be n=1,2,3,4,5,6,7,8,9 ..., the expression expanding element can have identical n.

Operating position of the present utility model is, after signal is through sensor 1 collection and signal conditioner 3 signal conditions, enter into multichannel expansion module 4, finishing channel parallel at the multichannel expansion module handles in real time and analyzes, each passage result coding outputs to high-speed data acquisition card by high speed FIFO, the coded data as a result of each passage of high-speed data acquisition card, under the Labview software that industrial computer 5 is installed, programme based on object module, realization is handled each channel data decoding, realizes the secondary treating to the passage image data.

Natural analog data signals such as all kinds of physical quantitys that needs are gathered, electric weight at first use corresponding sensor and amplifier to carry out acquisition process, and digital signal is amplified and changed into to weak signal; Signal conditioner is adjusted the level of signal amplitude, phase place, frequency etc. and is handled, make it can with the Signal Matching of the multichannel expansion module of back, realize connecting.

The multichannel expansion module is to gathering multichannel (be example explanation with 128 road signals) the parallel pin that inserts the multichannel expansion module of signal grouping, at first at 128 identical circuit modules of the inner generation of multichannel expansion module, each road signal is carried out the signal anti-interference process, and immunity module is made of 4 d type flip flops.Pulsewidth detects afterwards, and the result is latched.Each module clock has external clock to produce through phase-locked loop pll, and synchronizing signal module generation system control sequential mainly contains the reset signal of latch sequential and FIFO etc.Data after 128 road signals are handled through grouping, coding treatment circuit after by being connected on the high-speed data acquisition card of industrial control computer mainboard after the high speed FIFO output, the high-speed collection card image data is sent host computer, through decoding back secondary treating.128 road signal packet count are exactly to receive the port number that high-speed data acquisition card takies, and its purpose is to reduce one group of signal in the time through high speed FIFO output.This FPGA parallel multi-channel design takes into full account on the basis of real-time, has solved the problem that the hyperchannel number is gathered.

Data acquisition system (DAS) real-time: realize simultaneously multiple signals being realized running simultaneously processing to gathering the clock multiplier processing that signal is handled at the multichannel expansion module, all will greatly improve Signal Processing speed, specifically decide on project.When adjust handling back signal coding through high speed FIFO output, its principle is equal to and goes here and there conversion, some loss on processing speed.If but suitable through the signal way of high speed FIFO, this loss can be lowered to greatest extent, so, at this problem, multiple signals are carried out packet transaction be linked into high-speed data acquisition card.After the processing of multichannel expansion module, system not only can realize the multichannel processing, also improves a lot on signal real-time simultaneously.

The specific implementation process is as follows:

(1) physical quantity signal passes through sensor and amplifier collection and converts suitable level type and signal to;

(2) signal conditioner carries out the adjustment of suitable conditioning and level type to the signal after handling, in order to directly be connected (during use, follow-up multichannel expansion module also can be accepted the signal from other integrated circuit boards simultaneously) with subsequent module;

(3) multiple signals enter into the multichannel expansion module, at the multichannel expansion module at first to the signal anti-interference process, finish multi-channel parallel afterwards and handle in real time and analyze, and with each passage result packet coding, output to the high-speed data acquisition card of industrial computer inside by high speed FIFO;

(4) high-speed data acquisition card is gathered the coded data of each passage, under host computer Labview software, based on the object module programming, realizes each channel data decoding is handled, and realizes the secondary treating to the passage image data.

The utility model is based on industrial computer multichannel real-time acquisition system, taking into full account signal real-time and multichannel handles, on multichannel is handled: behind signal, and be advanced into the FPGA module, real-time analysis is handled, result according to certain coded system, is carried out and gone here and there conversion or adopt the high speed FIFO of FPGA inside modules, result is delivered to high-speed data acquisition card on the PC mainboard.Can gather I/O number and internal logic resource that the signal way depends on the multichannel expansion module, thoroughly solve the problem based on PC high-speed data acquisition card port number deficiency.On the real-time of signal, after low speed signal enters the multichannel expansion module, can adopt the PLL(phase-locked loop) after FPGA inside modules frequency multiplication, handle again, by and go here and there result or directly export to capture card by high speed FIFO, the property carried out is influenced very little.And signal has been realized parallel processing truly in the FPGA inside modules, and this is that processing such as single-chip microcomputer, DSP and ARM are beyond one's reach.Adopt the Labview software of programming based on object module in upper system handles, can improve the aesthetics of VC++ graphical interfaces and the complexity of reduction programming code, cost is low, and result of use is good, and good society and economic benefit are arranged.

It is to be noted, among the application, each parts is commercially available prod (known technology), the application's contribution is combining each parts science, constitute novel real-time parallel multiplexed signal sampling system, cost is low, and result of use is good, embodiment only in order to specify the application's technical scheme, is not intended to limit; Although with reference to preferred embodiment the utility model is had been described in detail, those of ordinary skill in the field are to be understood that: still can make amendment or the part technical characterictic is equal to replacement embodiment of the present utility model; And do not break away from the technical scheme of the essence of present techniques scheme, all should be encompassed in the middle of the technical scheme scope that the application asks for protection.

Claims

1. real-time parallel multiplexed signal sampling system, comprise sensor, amplifier, signal conditioner, industrial computer and display, it is characterized in that, sensor (1) links to each other through the input end of amplifier (2) with signal conditioner (3), the output terminal of signal conditioner (3) links to each other with the input end of multichannel expansion module (4), the input end of the data collecting card on the output terminal of multichannel expansion module (4) and the industrial computer (5) links to each other, and industrial computer (5) links to each other with display (6).

2. real-time parallel multiplexed signal sampling according to claim 1 system, it is characterized in that, described multichannel expansion module (4) is made of several identical expanding elements, each unit comprises a times frequency module (7), clock synchronization module (9) and the igniter module that links to each other successively (8), pulse width detection module (10), first latch (11), parallel serial conversion module (12), second latch (13), data cache device (14), times frequency module (7) connects igniter module (8) respectively, pulse width detection module (10) and data cache device (14), clock synchronization module (9) connects first latch (11) respectively, second latch (13) and data cache device (14).