CN106209090B - A kind of combining unit pulse per second (PPS) synchronism output system and method based on FPGA - Google Patents
A kind of combining unit pulse per second (PPS) synchronism output system and method based on FPGA Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
A kind of combining unit pulse per second (PPS) synchronism output system and method based on FPGA of the present invention, simple and convenient, parsing is simple.Step 1 the method includes, counting the inside pulse per second (PPS) of combining unit using external pulse per second (PPS)；According to combining unit data output frequencies, cycle count is carried out to its output data serial number；Two count in the clearing of pulse per second (PPS) rising edge time；Step 2, label receives the second count value and data sequence number count value of external pulse per second (PPS) rising edge time, calculates interior external clock time difference to be adjusted at the time difference, as synchronism output except period output data, and obtain time difference；The time difference to be adjusted when step 3, by synchronism output adjusts before combining unit synchronizes exports pulse into combining unit data, and the error for exporting pulse is no more than ± 10 microseconds, completes combining unit synchronism output.The system comprises the counting module realized by FPGA, difference calculating module and data export enabled module.
Description
Technical field
The present invention relates to power communication industry field, specially a kind of combining unit pulse per second (PPS) synchronism output based on FPGA
System and method.
Background technique
It is called to the physical unit to electric current and/or voltage data progress time correlation combination from two times transfer device
Combining unit.Combining unit can be a component of mutual inductor, be also possible to a separate unit.It is single for merging in industry
Required in the technical specification of member, combining unit sample frequency is 4kHz, and the sample variance time less than 10 microseconds, along with to adopting
The synchronous of sample data requires, so that synchronizing punctual a key technology as combining unit.In the prior art, combining unit exists
It can be led to the problem of in synchronizing process and send frequency jitter；I.e. sampled value discrete time is more than 10 microseconds, leads to the accurate of sampling
Property reduce.
Summary of the invention
Aiming at the problems existing in the prior art, the present invention provide a kind of combining unit pulse per second (PPS) based on FPGA synchronize it is defeated
System and method out, simple and convenient, parsing is simple, is realized based on FPGA, has good scalability and real-time.
The present invention is to be achieved through the following technical solutions:
A kind of combining unit pulse per second (PPS) synchronism output method, includes the following steps,
Step 1, the inside pulse per second (PPS) of combining unit is counted using external pulse per second (PPS)；It is defeated according to combining unit data
Frequency out carries out cycle count to its output data serial number；Two count in the clearing of pulse per second (PPS) rising edge time；
Step 2, label receives the second count value and data sequence number count value of external pulse per second (PPS) rising edge time, calculates
Interior external clock time difference to be adjusted at the time difference, as synchronism output except period output data, and obtain the time difference
Value；
Step 3, the next cycle of internal pulse per second (PPS) initially enters the presynchronization stage after receiving external pulse per second (PPS)；?
In the presynchronization stage, internal pulse per second (PPS) a cycle is the adjusting stage；It will be in time difference compensation to time adjusting stage
In several preceding pulses, the time that each impulse compensation arrives is in ± 10 milliseconds；After the adjusting stage terminates, combining unit is just
Normal output pulse signal, when next external pulse per second (PPS) rising edge arrives, internal pulse per second (PPS) exports simultaneously, and data counts value is clear
Zero, into synchronous phase, the time difference to be adjusted is adjusted before combining unit synchronizes into combining unit when realizing synchronism output
Data export pulse, and the error for exporting pulse is no more than ± 10 microseconds, completes combining unit synchronism output.
Preferably, in step 1, external pulse per second (PPS) can using program master clock or be converted into pulse per second (PPS) B code or
1588 clocks are as external clock pulse per second (PPS).
Preferably, in step 1, signal source using external program master clock as external pulse per second (PPS), master clock is
50MHz, period were 20 nanoseconds, and for count value range 0~500000000, the frequency of data output is 4kHz, count value model
It is trapped among 0~3999.
Further, in step 2, when detecting external second pulse signal rising edge, label second count value is C1, data sequence
Number count value is C2, and time difference count value is (C1-12500*C2).
Further, in step 3, the frequency of combining unit data output is 4kHz, then the period is 250 microseconds, when corresponding main
Clock is counted as 12500, before combining unit synchronism output, need to adjust output pulse data serial number count value for time difference (C1-
12500*C2) compensation is entered.
Further, in step 3, the range that need to adjust output pulse data serial number count value is 12000~13000.
A kind of combining unit pulse per second (PPS) synchronism output system based on FPGA, including the counting module realized by FPGA,
Difference calculating module and data export enabled module；
Counting module is for marking pulse per second (PPS) inside external pulse per second (PPS) and combining unit；
It needs to adjust when difference calculating module is for calculating combining unit inside pulse per second (PPS) with external pulse per second (PPS) synchronism output
Time difference；
Data export enabled module for generating data output enable signal.
Preferably, output enable signal includes that three kinds of enable signals generate state, respectively asynchronous state, presynchronization shape
State and synchronous regime.
Compared with prior art, the invention has the following beneficial technical effects:
Method of the present invention is synchronized by using synchronism output of the external pulse per second (PPS) to combining unit, will exceed
The time difference of error range is shared in error range in multiple pulses, meets its sample variance time less than 10 microseconds
Requirement, it is simple and convenient；It avoids using markers method synchronism output, the excessively complicated problem of target algorithm in parsing.
Method of the present invention is based on FPGA and is realized, the simple, function with good scalability and real-time, structure
It is short, at low cost to consume the low and development cycle；It is easy to debug by modular setting and searches problem, there is stronger portability.
Detailed description of the invention
Fig. 1 is the principle modules schematic diagram of system described in present example.
Fig. 2 is that internal pulse per second (PPS) and external pulse per second (PPS) difference count schematic diagram in present example.
Fig. 3 is that impulsive synchronization schematic diagram is exported in present example.
Specific embodiment
Below with reference to specific embodiment, the present invention is described in further detail, it is described be explanation of the invention and
It is not to limit.
A kind of combining unit pulse per second (PPS) synchronism output system based on FPGA of the present invention, as shown in Figure 1 comprising count module
Block, difference calculating module and data export enabled module；Counting module is for marking the second inside external pulse per second (PPS) and combining unit
Pulse；Difference calculating module be used to calculate need to adjust when pulse per second (PPS) and external pulse per second (PPS) synchronism output inside combining unit when
Between it is poor；Data export enabled module for generating data output enable signal, generate state comprising three kinds of enable signals: asynchronous
State (without external synchronization signal), presynchronization state (synchronizing preceding adjustment) and synchronous regime.This method is different from the prior art
The markers method synchronism output of middle use, algorithm are simple；It realizes there is good scalability and real-time, structure based on FPGA
Simply, short, at low cost advantage of low in energy consumption and development cycle.Its detailed step is as follows:
(1) the inside pulse per second (PPS) of combining unit is counted using external pulse per second (PPS)；According to combining unit output frequency,
Cycle count is carried out to its output data serial number；Two count in the clearing of pulse per second (PPS) rising edge time.External pulse per second (PPS) can adopt
With multiple signal source, such as B code and 1588 clocks, by the step of being converted to pulse per second (PPS) as external clock pulse per second (PPS)；This is excellent
Examples are selected to connect program master clock of the signal source of pulse per second (PPS) outside, master clock 50MHz, the period was 20 nanoseconds,
Count value range is 0~500000000, and the frequency of data output is 4kHz, and count value range is 0~3999；
(2) as shown in Fig. 2, label receives external clock pulse per second (PPS) rising edge time second count value and data sequence number counts
Value, calculates interior external clock time difference to be adjusted at the time difference, as synchronism output except period output data.Work as inspection
When measuring external second pulse signal rising edge, label second count value is C1, and data sequence number count value is C2, and time difference count value is
(C1-12500*C2)；
(3) by synchronism output the time difference to be adjusted when adjusts before combining unit synchronizes exports arteries and veins into combining unit data
Punching, it is ensured that the error for exporting pulse is no more than ± 10 microseconds, achievees the purpose that combining unit synchronism output with this.Data output
Frequency is 4kHz, then the period is 250 microseconds, and corresponding master clock is counted as 12500, and before combining unit synchronism output, it is appropriate to need
Time difference (C1-12500*C2) compensation is entered in adjustment output data serial number count value (adjusting range 12000~13000).
Specifically, as shown in figure 3, initially entering presynchronization from the next cycle of internal pulse per second (PPS) when receiving external pulse per second (PPS)
Stage；In the presynchronization stage, it is the adjusting stage in internal pulse per second (PPS) a cycle, in the time of adjusting stage, has
4000 data export pulse, several pulses before selecting, and time difference (C1-12500*C2) compensation is entered, each compensation
Time all in ± 10 milliseconds, after the adjusting stage terminates, the normal output pulse signal of combining unit, when next outside
When pulse per second (PPS) rising edge arrives, inside exports simultaneously, and data counts are reset, and into synchronous phase, it is defeated to realize that combining unit synchronizes
Out.
Inventive algorithm is simple, is realized based on FPGA, the simple, power consumption with good scalability and real-time, structure
Low and short, at low cost development cycle advantage.Modularization of the present invention is easy to debugging and searches problem, has stronger portability.
The above shows and describes the basic principles and main features of the present invention and the advantages of the present invention.The technology of the industry
Personnel are it should be appreciated that the present invention is not limited to the above embodiments, and the above embodiments and description only describe this
The principle of invention, without departing from the spirit and scope of the present invention, various changes and improvements may be made to the invention, these changes
Change and improvement all fall within the protetion scope of the claimed invention.The claimed scope of the invention by appended claims and its
Equivalent thereof.
Claims (5)
1. a kind of combining unit pulse per second (PPS) synchronism output method, which is characterized in that include the following steps,
Step 1, the inside pulse per second (PPS) of combining unit is counted using external pulse per second (PPS)；Frequency is exported according to combining unit data
Rate carries out cycle count to combining unit output data serial number；Two count in the clearing of pulse per second (PPS) rising edge time；
Signal source using external program master clock as external pulse per second (PPS), master clock 50MHz, period were 20 nanoseconds,
Count value range is 0~500000000, and data output frequencies 4kHz, count value range is 0~3999；
Step 2, label receives the second count value and data sequence number count value of external pulse per second (PPS) rising edge time, calculates inside and outside
Clock time difference to be adjusted at the time difference, as synchronism output except period output data, and obtain time difference；When
When detecting external pulse per second (PPS) rising edge, label second count value is C1, and data sequence number count value is C2, and time difference count value is
(C1-12500*C2)；
Step 3, the next cycle of internal pulse per second (PPS) initially enters the presynchronization stage after receiving external pulse per second (PPS)；Pre- same
In step section, internal pulse per second (PPS) a cycle is the adjusting stage；If before in time difference compensation to time adjusting stage
In dry pulse, the time that each impulse compensation arrives is in ± 10 milliseconds；After the adjusting stage terminates, combining unit is normally defeated
Pulse signal out, when next external pulse per second (PPS) rising edge arrives, internal pulse per second (PPS) exports simultaneously, and data counts value is reset,
Into synchronous phase, the time difference to be adjusted is adjusted before combining unit synchronizes into combining unit data when realizing synchronism output
Pulse is exported, and the error for exporting pulse is no more than ± 10 microseconds, completes combining unit synchronism output；
Combining unit data output frequencies are 4kHz, then the period is 250 microseconds, and corresponding master clock is counted as 12500, single merging
Before first synchronism output, output pulse data serial number count value need to be adjusted, time difference (C1-12500*C2) compensation is entered.
2. a kind of combining unit pulse per second (PPS) synchronism output method according to claim 1, which is characterized in that in step 1, outside
Pulse per second (PPS) is connect using program master clock or the B code for being converted into pulse per second (PPS) or 1588 clocks as external clock pulse per second (PPS).
3. a kind of combining unit pulse per second (PPS) synchronism output method according to claim 1, which is characterized in that in step 3, need
The range of adjustment output pulse data serial number count value is 12000~13000.
4. a kind of combining unit pulse per second (PPS) synchronism output system based on FPGA, which is characterized in that for realizing claim 1-3
Method described in any one, including the counting module realized by FPGA, difference calculating module and data export enabled module；
Counting module is for marking pulse per second (PPS) inside external pulse per second (PPS) and combining unit；
Difference calculating module be used to calculate need to adjust when pulse per second (PPS) and external pulse per second (PPS) synchronism output inside combining unit when
Between it is poor；
Data export enabled module for generating data output enable signal.
5. a kind of combining unit pulse per second (PPS) synchronism output system based on FPGA according to claim 4, which is characterized in that
Exporting enable signal includes that three kinds of enable signals generate state, respectively asynchronous state, presynchronization state and synchronous regime.
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| CN113900480B (en) * | 2021-12-10 | 2022-03-04 | 成都金诺信高科技有限公司 | Time synchronization method of periodic second pulse output aligned with specified time |
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| CN101420225A (en) * | 2008-12-03 | 2009-04-29 | 中国航天科技集团公司第五研究院第五〇四研究所 | High precision time difference calibrating method based on FPGA |
| CN105634640A (en) * | 2015-12-31 | 2016-06-01 | 武汉凡谷电子技术股份有限公司 | Realization method and device of TDD synchronization switch |
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| CN101420225A (en) * | 2008-12-03 | 2009-04-29 | 中国航天科技集团公司第五研究院第五〇四研究所 | High precision time difference calibrating method based on FPGA |
| CN105634640A (en) * | 2015-12-31 | 2016-06-01 | 武汉凡谷电子技术股份有限公司 | Realization method and device of TDD synchronization switch |
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