CN108428679B - 具有热导柱的集成电路封装 - Google Patents

具有热导柱的集成电路封装 Download PDF

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CN108428679B
CN108428679B CN201810148937.1A CN201810148937A CN108428679B CN 108428679 B CN108428679 B CN 108428679B CN 201810148937 A CN201810148937 A CN 201810148937A CN 108428679 B CN108428679 B CN 108428679B
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die
molding compound
integrated circuit
thermal
stack
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CN108428679A (zh
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卢克·G·英格兰
凯萨琳·C·里维拉
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GlobalFoundries US Inc
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GlobalFoundries US Inc
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Abstract

本揭示内容涉及具有热导柱的集成电路封装，其具体实施例是关于一种集成电路(IC)封装，包括位在一第一晶粒上且侧向邻接位在该第一晶粒上的一晶粒堆栈的一模塑料。该晶粒堆栈使该第一晶粒电气耦合至一最上面晶粒，以及一热导柱从该第一晶粒延伸穿过该模塑料到该模塑料的上表面。该热导柱与该晶粒堆栈及该最上面晶粒电气隔离。该热导柱侧向抵接且接触该模塑料。

Description

具有热导柱的集成电路封装
技术领域
本揭示内容是有关于经结构化成能忍受升高工作温度的集成电路(IC)封装。特别是，本揭示内容的具体实施例包括集成电路封装，其包括延伸穿过封装的模塑料(moldingcompound)的一或更多热导柱(thermally conductive pillar)，及其形成方法。
背景技术
在半导体集成电路(IC)芯片的倒装芯片加工中，可实作例如受控塌陷芯片连接(controlled collapse chip connect，C4)焊球的金属接触，以使IC晶粒(die)连接至封装及/或互相连接。在形成时，各金属接触可提供耦合于直接连接IC芯片之间的导电结构以用作两个芯片之间的机械及电气连接。这些组件可一起界定IC“封装”，亦即，特定芯片或装置的壳体。该封装一般包括用于使特定芯片与外部电路电气连接的各组件，且也可经结构化成可包括及/或耦合至为芯片的主动组件提供物理及化学保护的组件。
在芯片的操作期间，热可能从IC结构的组件耗散到封装。在用于三维封装IC的晶粒对晶片(die-to-wafer)总成中，可包括一或更多模塑料供使用于后续的处理及测试。此类模塑料通常用作热传导的屏障，且在有些情形下，可阻止热从IC结构传递到封装的盖体。因此，模塑料在封装中的存在可与升高工作温度相关，例如，相对于产品规格或没有模塑料在其中的结构类似芯片。
发明内容
本揭示内容的第一方面提供一种集成电路(IC)封装，其包括：一模塑料，其位在一第一晶粒上且侧向邻接位在该第一晶粒上的一晶粒堆栈，其中，该晶粒堆栈使该第一晶粒电气耦合至该晶粒堆栈的一最上面晶粒；以及一热导柱，其从该第一晶粒延伸穿过该模塑料到该模塑料的上表面，其中，该热导柱与该晶粒堆栈及该晶粒堆栈的该最上面晶粒电气隔离，以及其中，该热导柱侧向抵接且接触该模塑料。
本揭示内容的第二方面提供一种集成电路(IC)封装，其包括：一第一晶粒，其耦合至多个金属接触；一晶粒堆栈，其位在该第一晶粒上且电气耦合至该多个金属接触；一模塑料，其位在该第一晶粒上且侧向邻接该晶粒堆栈；一热导柱，其位在该第一晶粒上且延伸穿过该模塑料到其上表面，其中，该热导柱与该晶粒堆栈及该多个金属接触电气隔离，以及其中，该热导柱侧向抵接且接触该模塑料；以及一最上面晶粒，其接触及上覆该晶粒堆栈，其中，该模塑料使该晶粒堆栈的该最上面晶粒与该热导柱电气隔离。
本揭示内容的第三方面提供一种形成集成电路(IC)封装的方法，该方法包括：将多个金属接触装在一第一晶粒上，该第一晶粒包括耦合至该多个金属接触的多个连接通孔；形成一热导柱于该第一晶粒上且侧向偏离该多个连接通孔；形成一晶粒堆栈于该多个连接通孔上，致使该晶粒堆栈侧向偏离该热导柱；以及形成一模塑料于该第一晶粒上，致使该模塑料侧向隔离且电气隔离该热导柱与该晶粒堆栈，其中，在形成后，该模塑料侧向抵接且接触该热导柱。
附图说明
将参考以下附图详述本揭示内容的具体实施例，其中类似的组件用相同的附图标记表示。
图1根据本揭示内容的具体实施例图示装上第一晶粒的多个金属接触在平面X-Z的横截面图。
图2根据本揭示内容的具体实施例图示加工中的第一晶粒在平面X-Z的横截面图。
图3根据本揭示内容的具体实施例图示形成于第一晶粒上的数个热导柱在平面X-Z的横截面图。
图4根据本揭示内容的具体实施例图示形成于第一晶粒上的晶粒堆栈在平面X-Z的横截面图。
图5根据本揭示内容的具体实施例图示形成于第一晶粒上的模塑料的阵列在平面X-Z的横截面图。
图6根据本揭示内容的具体实施例图示正被平坦化的模塑料在平面X-Z的横截面图。
图7根据本揭示内容的具体实施例图示暂时性晶片被移除以暴露金属接触在平面X-Z的横截面图。
图8根据本揭示内容的具体实施例图示集成电路(IC)封装在平面X-Z的横截面图。
图9根据本揭示内容的具体实施例图示集成电路(IC)封装的透视图。
图10根据本揭示内容的具体实施例图示正要从晶片切割的集成电路(IC)封装在平面X-Y的平面图。
应注意，本揭示内容的附图不一定按比例绘制。附图旨在仅仅描绘本揭示内容的典型方面，因此不应被视为用来限制本揭示内容的范畴。附图中，类似的组件用相同的附图标记表示。
具体实施方式
在以下说明中，参考形成其一部份且举例说明可实施本发明教导的特定示范具体实施例的附图。充分详述这些具体实施例使得熟谙此艺者能够实施本发明教导，且应了解，可使用其他具体实施例及做出改变而不脱离本发明教导的范畴。因此，以下说明仅为示范。
请参考图1，本揭示内容是有关于包括例如能忍受升高工作温度的热导柱的集成电路(IC)封装，及其形成方法。提及于本文的各种组件以在平面X-Z中的二维横截面描绘；也在本文的他处描述同一个或类似组件在不同二维平面中或在三维空间中的视图。根据本揭示内容的制造技术可包括：将多个金属接触102装在第一晶粒104上。第一晶粒104可至少部份由任何当前已知或以后开发的半导体材料构成，可包括但不限于：硅、锗、碳化硅，以及实质由有由公式AlX1GaX2InX3AsY1PY2NY3SbY4界定的组合物的一或更多III-V族化合物半导体组成的物质，在此X1、X2、X3、Y1、Y2、Y3及Y4为相对比例，各个大于或等于零且X1+X2+X3+Y1+Y2+Y3+Y4＝1(1为总相对莫耳量)。其他合适物质可包括有组合物ZnA1CdA2SeB1TeB2的II-VI族化合物半导体，在此A1、A2、B1及B2为相对比例，各个大于或等于零且A1+A2+B1+B2＝1(1为总莫耳量)。装在第一晶粒104上的各金属接触102，例如，可由焊锡凸块构成，包括一或更多可焊接材料、传导柱(例如，有传导帽盖的金属柱，例如，以锡为帽盖的铜柱)，及/或任何当前已知或以后开发的导电材料。根据一具体实施例，金属接触102，例如，可由有锡及铅、有锡无铅、有锡及铜或银、锡铋(tin bismuth)、锡铟(tin indium)等等的残留物的材料形成。金属接触102的尺寸至少部份可取决于第一晶粒104及与金属接触102连接的其他结构的尺寸(例如，表面积、深度等等)。例如，一或更多金属接触102可有不同的尺寸以适应产品的变动载流能力(varying current carrying capacity)及/或间隔要求。
如图所示，第一晶粒104可包括在其中的多个连接通孔106。各连接通孔106可至少部份延伸穿过第一晶粒104到在第一晶粒104的一表面上的接触点，例如，连接垫(未图示)。然后，金属接触102可通过形成于其上来电气连接至各个连接通孔106。各金属接触102可经定位成可界定通到一或更多连接通孔106及/或在其下面的连接垫(未图示)的电气连接。连接通孔106一般可包括蚀刻穿过第一晶粒104中的半导体材料的一或更多导电材料，以提供与3D晶片级封装兼容的晶片对晶片(wafer-to-wafer)互连方案，例如，使用形成于接触垫上的金属接触102通到底下结构(例如，BEOL介电质材料及/或其他外部结构)的电气连接。各连接通孔106可用来使第一晶粒104上的电路组件连接至其他组件。连接通孔106可包括以其结构为中心周向设置的实质环形耐火金属衬垫(未图示)用以提供附加电气绝缘及用以防止连接通孔106与在第一晶粒104中的邻近结构之间的电迁移(electromigration)。此类衬垫可由任何当前已知或以后开发的导电材料构成，例如，耐火金属，例如钌(Ru)、钽(Ta)、钛(Ti)、钨(W)、铱(Ir)、铑(Rh)及铂(Pt)等等，或它们的混合物。在一特定具体实施例中，在第一晶粒104内的一或更多连接通孔106可体现为电源供应通孔(power supply via)用以传输大于其他连接通孔106的电流量。如图1所示，各连接通孔106在第一晶粒104的轴端之间可实质垂直延伸穿过它。尽管连接通孔106在附图中呈实质柱形，然而在其他具体实施例中，连接通孔106可具有不同的结构。更一般地，连接通孔106可具有任何所欲形状或尺寸，且可包括，例如，各自可具有线性轮廓、曲线轮廓、波型轮廓、不规则轮廓等等的一或更多电气连接构件。
可形成附加材料以屏蔽金属接触102、连接通孔106及/或其他组件以免在描述于本文的后续制造步骤中被修改及加工。例如，暂时性黏合绝缘体108可涂在第一晶粒104及/或连接通孔106的暴露部份上，例如，通过旋涂及/或膜迭层工艺(film laminationprocess)用以形成聚合物于材料上。黏合绝缘体108可包括有黏性的一或更多电绝缘材料。作为实施例，暂时性黏合绝缘体108可包括一或更多电绝缘黏合材料，例如脲烷(urethane)、硅氧树脂、及/或其他黏合树脂材料。在本技艺或者被识为“操作晶片(handlewafer)”的暂时性晶片110也可位在金属接触102及黏合绝缘体108上(例如，可用机械方式放在其上，如图1中的箭头所示)。黏合绝缘体108可使第一晶粒104机械耦合至暂时性晶片110。暂时性晶片110可包括能够机械接合至第一晶粒104的任何合适材料，例如，包括在第一晶粒104的组合物中的一或更多半导体材料，及/或可包括与导电率无关的一或更多不同材料(例如，玻璃)。
翻到图2，本揭示内容可包括修改第一晶粒104的结构，例如，以为随后形成于其上的结构组件制备第一晶粒104。在一具体实施例中，如图所示，制造者可翻转第一晶粒104及暂时性晶片110以暴露第一晶粒104的反面。然后，可移除第一晶粒104内的半导体材料，例如，通过背面研磨，接着是干蚀刻及化学平面平坦化(chemical planar planarization，CMP)或用于移除部份结构的其他当前已知或以后开发技术，如图2中的箭头所示。CMP通常指用于用化学机械加工移除实心材料层的任何工艺，例如，用以金属互连图案的表面平坦化及界定。在加工后，如图2所示，连接通孔106可在相对两面之间延伸穿过第一晶粒104。在平坦化后，第一晶粒104在相对垂直两面之间可具有例如约50微米(μm)的厚度。因此，第一晶粒104的上表面可与暴露连接通孔106的上表面实质共面。
翻到图3，本揭示内容可包括形成一或更多热导柱120于第一晶粒104上。热导柱120可经结构化成可提供第一晶粒104的热流通，例如，以在IC装置的操作期间使热从第一晶粒104转移到其他结构。各热导柱120可包括一或更多导热金属及/或用以传输热的其他材料。根据一实施例，热导柱120可包括铜(Cu)、铝(Al)及/或其他导电材料。可在第一晶粒104中与连接通孔106电气隔离的区域上形成热导柱120。如图所示，各热导柱120可侧向偏离在第一晶粒104上的连接通孔106，从而与各连接通孔106电气分离。尽管热导柱120在有些情形下可至少部份垂直对齐在第一晶粒102的对面上的金属接触102，然而热导柱120可经定位成与连接通孔106及与其耦合的金属接触102电气隔离。例如，用电镀、沉积及/或形成导电材料于第一晶粒104上的其他方式，可形成热导柱120。“电镀”通常指一种将数个金属薄层镀于浸入其中含有金属离子的电解液的加偏压晶片结构(例如，第一晶粒104)的表面上的工艺。电镀可选择性地在先前已例如通过沉积形成的一或更多种子层上形成材料。如本文所使用的，“沉积(deposition)”或“沉积(depositing)”材料(例如，热导柱120)可包括适用于待沉积材料的任何当前已知或以后开发技术，包括但不限于，例如：化学气相沉积(chemical vapor deposition，CVD)、低压CVD(LPCVD)、电浆增强式CVD(PECVD)、半大气CVD(SACVD)及高密度电浆CVD(HDPCVD)、快速退火CVD(RTCVD)、超过真空CVD(UHVCVD)、有限反应加工CVD(LRPCVD)、金属有机CVD(MOCVD)、溅镀沉积、离子束沉积、电子束沉积、激光辅助沉积、热氧化、热氮化、旋涂方法、物理气相沉积(physical vapor deposition，PVD)、原子层沉积(atomic layer deposition，ALD)、化学氧化、分子束磊晶(molecular beamepitaxy，MBE)、喷镀(plating)、蒸发，除了当前已知或以后开发的其他沉积工艺以外。
翻到图4，本揭示内容的具体实施例可包括在形成热导柱120后，形成一群堆栈晶粒(stacked dies)130至第一晶粒104的连接通孔106。如图所示，堆栈晶粒130可包括通过第一晶粒104的连接通孔106至金属接触102的一或更多电气耦合。可用在习知集成电路封装制造中形成包括金属线等等的晶粒堆栈的任何当前已知或以后开发工艺制成堆栈晶粒130。例如，通过顺序晶粒对晶片堆栈配线层于在第一晶粒104上面的介电质材料(例如，一或更多层间介电质材料(inter-level dielectric material，ILD))中，可形成堆栈晶粒130。因此，堆栈晶粒130可包括相继配置于诸层中的金属线132，其中通孔134延伸穿过绝缘体材料且将金属线132连接在一起。图4所示金属线132及通孔134的组态为示范配置，以及本揭示内容的具体实施例可想到金属线132及通孔134的替代配置。
堆栈晶粒130可包括位在它们的上表面上的最上面晶粒136，例如，以界定最上面层及/或电气连接至其他结构或接触。最上面晶粒136主要可包括描述于本文与第一晶粒104有关的一或更多半导体材料及/或可包括其他半导体材料。最上面晶粒136视需要可包括，例如，导电线、通孔、接触等等(未图示)，以使底下的结构电气连接在一起。最上面晶粒136也可有比第一晶粒104大的厚度，例如，以适应在后续工艺被移除的材料。不论任何选定设计及配置如何，堆栈晶粒130可与热导柱120侧向分离及电气隔离。尽管为了示范将堆栈晶粒130描述成是在热导柱120后形成，然而应了解，在替代具体实施例中，堆栈晶粒130在热导柱120之前可形成于第一晶粒104的连接通孔106上。
请参考图5，本揭示内容的具体实施例可包括形成模塑料140于第一晶粒104上。形成模塑料140于第一晶粒104上可埋藏热导柱120及在其下的堆栈晶粒130。模塑料140可包括，例如，一或更多电绝缘树脂材料，包括但不限于：二氧化硅(SiO2)、氧化铝(Al2O3)、或有类似性质的其他模塑料。模塑料140可形成于第一晶粒104上，而热导柱120在被处理或以其他方式允许它在底下结构上固化成固相之前处于未固化的液相。不管用什么方法体现，模塑料140可侧向抵接且接触热导柱120而不干预侧向位在其间的材料。亦即，与例如半导体贯穿孔(through-semiconductor vias，TSV)的其他传导结构相比，热导柱120可缺少耐火金属衬垫及/或使其材料组合物与模塑料140分离的其他结构。因此，模塑料140可使热导柱120与经组配成可传输电流通过的其他结构(例如，连接通孔106与堆栈晶粒130)物理及电气分离。在模塑料140形成后，热导柱120、最上面晶粒136及/或模塑料140在第一晶粒104以上的总高度可大于各结构组件在最终集成电路封装中的规定高度。
翻到图6，根据本揭示内容的方法可包括修改先前形成的结构以产生预定的尺寸及形状供随后使用于集成电路封装。例如，本揭示内容的具体实施例可包括平坦化模塑料140及位于其下的其他结构。如图6中的箭头所示，本揭示内容可包括平坦化模塑料140以及导热柱120及/或堆栈晶粒130，例如，用机械研磨及/或用于从先驱结构产生平坦化上表面的其他工艺。此类工艺可移除模塑料140的暴露部份且可进一步部份减少位于其下的材料的厚度。在平坦化结束后，模塑料140的上表面可与导热柱120及堆栈晶粒130的上表面实质共面，例如，沿着图6的参考线P。可控制平坦化的数量及/或对应时间长度以产生有预定尺寸的各种组件，例如，热导柱120及堆栈晶粒130，以满足预定规格。在一示范具体实施例中，热导柱120在第一晶粒104以上可延伸到有至少约250微米的高度，例如，约300微米。可略减(shade)各热导柱120的直径-高度的深宽比(aspect ratio)以适应堆栈晶粒130的尺寸及形状。例如，在堆栈晶粒包括例如总共4个晶粒时，各热导柱120的直径-高度的深宽比可约为一比一，例如，如热导柱120的直径与高度图示为约有相同的直径J。在其他情形下，例如，堆栈晶粒130含有8个晶粒，相应地，可调整各热导柱120的直径-高度的深宽比，例如，达大约二比一。因此，各热导柱120的尺寸及尺寸比例在结构上可与IC中的习知传导结构(例如，通孔、TSV等等)不同，除了在操作上可与此类结构区别以外。
翻到图7，本揭示内容可包括从暂时性晶片110移除描述于本文的各种结构(图1至图6)。特别是，暂时性晶片110可与金属接触102分离以暴露黏合绝缘体108(图1至图6)。可从金属接触102移除暂时性晶片110，例如，用任何当前已知或以后开发的晶片分离技术(例如，化学及/或机械晶片分离)。黏合绝缘体108的移除也可通过用于从结构移除绝缘材料的任何当前已知或以后开发工艺，例如，化学溶解、选择性或非选择性蚀刻等等。根据用于使电路在焊接互连处连结在一起的任何当前已知或以后开发工艺流程，例如，倒装芯片加工方案，移除黏合绝缘体108及暂时性晶片110可让金属接触102链接至封装结构。无论如何，描述本文的本揭示内容具体实施例可产生集成于较大IC结构中的集成电路封装150。
在操作期间，通过流通通过容纳于模塑料140内的热导柱120，累积于第一晶粒104、堆栈晶粒130等等内的热能可逸出到环境及/或其他结构。在习知装置中，由于模塑料140的热绝缘，在习知封装中的第一晶粒的温度可接近或超过临界限度(threshold limit)(例如，比规定操作温度高30或更多℃)。通过提供在第一晶粒104与一或更多散热器之间的热途径(thermal pathway)，例如描述本文别处的封装盖170，有热导柱120在其中的集成电路封装150可使第一晶粒104的操作温度降到临界值以下。此外，如本文所证实的，在少许修改习知加工技术下，热导柱120在结构上可集成于集成电路封装150中。
请参考一起图8及图9，集成电路封装150图标成与各种结构组件集成以形成较大的结构。在图8的平面X-Z中图示集成电路封装150的横截面图。为了进一步图解说明，图9描绘在三维(X-Y-Z)空间中的集成电路封装150。如本文所述，集成电路封装150可包括模塑料140，其位在第一晶粒104上且侧向邻接位在第一晶粒104上的堆栈晶粒130。堆栈晶粒130可使第一晶粒104电气耦合至最上面晶粒136，如本文所述。一或更多热导柱120可从第一晶粒104延伸穿过模塑料140到它的上表面，以及各热导柱120与堆栈晶粒130及最上面晶粒136电气隔离。尽管如此，热导柱120可侧向抵接且接触模塑料140，藉此传导来自集成电路封装150的第一晶粒104的热。
金属接触102可经定位成与在直接位于第一晶粒104下面的有机迭层154(例如，一或更多印刷电路板(PCB))上的由互连垫152组成的对应集合(图8)接触。有机迭层(organiclaminate)154更可包括电路及/或其他传导组件(未图标)，以使第一晶粒104电气耦合至IC结构的其他组件。有机迭层154本身可包括一或更多焊锡凸块156用于提供通到外部组件的电气连接。相对于金属接触102，有机迭层154的焊锡凸块156可有较大的尺寸，例如，以适合一或更多设计规格或限制。应了解，金属接触102、156在制造期间可完全或部份熔解以增加集成电路封装150和与其连接的电路组件之间的机械及/或电气接合。此外，应了解，可形成与金属接触102、156接触及/或紧邻的一或更多黏合绝缘体以增加结构接合，如在说明暂时性晶片110(图1至图6)时所述。
只参考图8，可提供附加结构以结构性保护及/或隐藏集成电路封装150。例如，在有机迭层154的一部份及/或外圆周上可形成黏合涂层(adhesive coating)160。黏合涂层160可包括包括在描述于本文他处的黏合绝缘体108(图1至图6)的组合物中的一或更多材料，及/或可包括任何其他当前已知或以后开发的材料用于把IC装置的两个结构组件接合在一起。通过黏合涂层160，封装盖170可机械耦合至有机迭层154。封装盖170可包括，例如，一或更多金属及/或陶瓷材料，其经组配成可通过黏合涂层160及/或通过一或更多硬焊接合(brazed coupling)、密封件及/或其他结构接合技术接合至有机迭层154。
翻到图10，形成多个集成电路封装150可通过使它的组件与较大的结构分离，例如，在描述于本文的各种制造技术之后。如在图10的平面X-Y内的平面图所示，单一晶片结构180可经制造成包括模塑料140、多个热导柱120，各自具有位在其上的最上面晶粒136的多个晶粒堆栈130。包括在晶片结构180中的各种结构可聚集在一起以便包括在个别产品单元内，例如，使一最上面晶粒136沿着假想线与模塑料140在附近的部份及形成于其中的热导柱120群组聚集在一起。尽管热导柱120包括在模塑料140内，然而制造者可将晶片结构180切割成个别的集成电路封装150，例如，用任何当前已知或以后开发的程序用于将晶片分成数个单一产品单元。然后，各集成电路封装150可连接至其他结构及/或封装组件，如本文在说明图8至图9时所述。尽管图10的实施例的一晶片结构180被切割成有热导柱120在其中的12个单元，然而晶片结构180的尺寸及形状可制作成含有任何所欲单元个数(例如，20个单元、50个单元、100个单元、1000个单元等等)。
如以上所述的方法是在制造集成电路芯片时使用。所得集成电路芯片可由制造者以原始晶片形式(raw wafer form)(也就是具有多个未封装芯片的单一晶片)、作为裸晶粒(bare die)或已封装的形式来销售。在后一情形下，芯片装在单芯片封装中(例如，塑料载体(plastic carrier)，具有固定至主板或其他更高层载体的引脚(lead))，或多芯片封装体中(例如，具有表面互连件(surface interconnection)或内嵌互连件(buriedinterconnection)任一或两者兼具的陶瓷载体)。然后，在任一情形下，芯片与其他芯片、离散电路组件及/或其他信号处理装置集成成为(a)中间产品(例如，主板)，或(b)最终产品中的任一者的一部分。
用于本文的术语只为了要描述特定具体实施例而非旨在限制本揭示内容。如本文所使用的，单数形式“一(a)”、“一(an)”、及“该(the)”旨在也包括多形式，除非上下文中另有明确指示。更应了解，用语“包含(comprises)”及/或“包含(comprising)”在使用于专利说明书中时具体描述提及的特征、整数、步骤、操作、组件及/或组件的存在，但不排除存在或加入一或更多其他特征、整数、步骤、操作、组件及/或它们的群组。“视需要的”或“视需要地”意指随后所述事件或情况可能发生也可能不发生，以及该描述包括发生事件的实例与不发生事件的实例。
可应用如用于本专利说明书及权利要求书中的近似语以修饰允许改变而不导致相关基本功能改变的任何数量表示法。因此，用一用语或数个用语例如“约”、“大约”及“实质上”修饰的数值，不受限于指定的确切数值。至少在某些情况下，该近似语可对应至用于测量该数值的仪器的精确度。在本专利说明书及权利要求书中，范围限制可予以组合及/或互换，此类范围被识别且包括包含于其中的所有子范围，除非上下文或语言另有说明。适用于一范围中的一特定数值的“大约”适用于可表示提及数值的+/-10％的两个数值，且除非取决于测量该数值的仪器的精确度。
所有构件或步骤的对应结构、材料、动作以及等效物加上下列权利要求书之中的功能组件旨在包括用于与其他主张组件结合一起按具体主张方式完成功能的任何结构、材料或动作。提出本揭示内容的描述是为了图解说明而非旨在穷尽或以所揭示的形式限制本揭示内容。本技艺一般技术人员明白有许多修改及变体而不脱离本揭示内容的范畴及精神。该具体实施例经选择及描述成可最佳地解释本揭示内容的原理及其实际应用，且使得本技艺的其他一般技术人员能够了解本揭示内容有不同修改的不同具体实施例适合使用于想到的特定用途。

Claims (20)

1.一种集成电路(IC)封装，包含：
一模塑料，其位在一第一晶粒上且侧向邻接位在该第一晶粒上的一晶粒堆栈，其中，该第一晶粒包括多个连接通孔，该晶粒堆栈形成至该多个连接通孔，且该晶粒堆栈使该第一晶粒电气耦合至在该晶粒堆栈中的一最上面晶粒；以及
一热导柱，其从该第一晶粒延伸穿过该模塑料到该模塑料的上表面，其中，该热导柱直接位在该第一晶粒上且与该多个连接通孔、该晶粒堆栈及该最上面晶粒电气隔离，以及其中，该热导柱侧向抵接且接触该模塑料。
2.如权利要求1所述的集成电路封装，其中，该热导柱包含铜(Cu)或铝(Al)中的一者。
3.如权利要求1所述的集成电路封装，其中，该模塑料包含其中具有二氧化硅(SiO2)或氧化铝(Al2O3)中的一者的一树脂材料。
4.如权利要求1所述的集成电路封装，其中，该热导柱包含位在该第一晶粒上且与该晶粒堆栈电气隔离的多个热导柱中的一者。
5.如权利要求1所述的集成电路封装，进一步包含多个金属接触，其位在该晶粒堆栈与一互连垫之间，其中，该多个金属接触使该第一晶粒电气耦合至该互连垫。
6.如权利要求1所述的集成电路封装，其中，该热导柱的上表面经定位成至少高于该第一晶粒有250微米(μm)。
7.如权利要求1所述的集成电路封装，其中，该热导柱的上表面与该热导柱的一侧向侧壁的深宽比在一比一与二比一之间。
8.一种集成电路(IC)封装，包含：
一第一晶粒，其耦合至多个金属接触且包括多个连接通孔；
一晶粒堆栈，其位在该第一晶粒的该多个连接通孔上且电气耦合至该多个金属接触；
一模塑料，其位在该第一晶粒上且侧向邻接该晶粒堆栈；
一热导柱，其直接位在该第一晶粒上且延伸穿过该模塑料到该模塑料的上表面，其中，该热导柱与该多个连接通孔、该晶粒堆栈及该多个金属接触电气隔离，以及其中，该热导柱侧向抵接且接触该模塑料；以及
一最上面晶粒，其接触及上覆该晶粒堆栈，其中，该模塑料使该最上面晶粒与该热导柱电气隔离。
9.如权利要求8所述的集成电路封装，其中，该热导柱包含铜(Cu)或铝(Al)中的一者。
10.如权利要求8所述的集成电路封装，其中，该模塑料包含其中具有二氧化硅(SiO2)或氧化铝(Al2O3)中的一者的一树脂材料。
11.如权利要求8所述的集成电路封装，其中，该热导柱包含位在该第一晶粒上且与该晶粒堆栈电气隔离的多个热导柱中的一者。
12.如权利要求8所述的集成电路封装，其中，该多个金属接触使该第一晶粒电气耦合至位在该多个金属接触下面的一互连垫。
13.一种形成集成电路(IC)封装的方法，该方法包含：
将多个金属接触装在一第一晶粒上，该第一晶粒包括耦合至该多个金属接触的多个连接通孔；
形成一热导柱直接于该第一晶粒上且侧向偏离该多个连接通孔，使得该热导柱与该多个连接通孔电气隔离；
形成一晶粒堆栈于该多个连接通孔上，致使该晶粒堆栈侧向偏离该热导柱；以及
形成一模塑料于该第一晶粒上，致使该模塑料侧向且电气隔离该热导柱与该晶粒堆栈，其中，在形成后，该模塑料侧向抵接且接触该热导柱。
14.如权利要求13所述的方法，其中，将该多个金属接触装在该第一晶粒上包括：
使具有该多个连接通孔的该第一晶粒耦合至一暂时性晶片，该多个金属接触位在该第一晶粒与该暂时性晶片之间；以及
移除该第一晶粒的数个部份以暴露该多个连接通孔，致使该第一晶粒的上表面与该多个连接通孔的上表面实质共面。
15.如权利要求14所述的方法，进一步包含从该多个金属接触移除该暂时性晶片。
16.如权利要求13所述的方法，其中，该热导柱包含铜(Cu)或铝(Al)中的一者。
17.如权利要求13所述的方法，其中，该模塑料包含其中具有二氧化硅(SiO2)或氧化铝(Al2O3)中的一者的一树脂材料。
18.如权利要求13所述的方法，其中，形成该模塑料于该第一晶粒上包括：
形成该模塑料于该第一晶粒、该热导柱及该晶粒堆栈上；以及
平坦化该模塑料，致使该模塑料的上表面与该热导柱的上表面及该晶粒堆栈实质共面。
19.如权利要求13所述的方法，其中，形成该热导柱包括电镀该热导柱至该第一晶粒。
20.如权利要求13所述的方法，进一步包含从一晶片结构切割出该热导柱及该晶粒堆栈。
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