CN202424687U - Self-adjustable delay locking loop circuit - Google Patents
Self-adjustable delay locking loop circuit Download PDFInfo
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- CN202424687U CN202424687U CN2011205722129U CN201120572212U CN202424687U CN 202424687 U CN202424687 U CN 202424687U CN 2011205722129 U CN2011205722129 U CN 2011205722129U CN 201120572212 U CN201120572212 U CN 201120572212U CN 202424687 U CN202424687 U CN 202424687U
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Abstract
The utility model discloses a self-adjusting delay locking loop circuit which comprises a phase comparator, a charge pump, a voltage control delay chain and a filtering capacitor and further comprises a detection circuit, a voltage control current source and a switch. The detection circuit is configured to be used for judging relation between delay time of the voltage control delay chain and clock period of input clock signals and outputting control signals used for controlling the voltage control current source and a switch. The voltage control current source is configured to be used for receiving control signals and adjusting output current according to control signals. The switch is arranged on an output circuit of a charge pump and is configured to receive control signals and close or open according to the control signals. The delay locking loop circuit is capable of automatically detecting the working state of the voltage control delay chain and adjusting the delay time by adding the detection circuit and does not need to design an extra upper layer system to reset the delay locking ring circuit.
Description
Technical field
The utility model relates to a kind of delay lock loop (DLL) circuit, particularly a kind of can self-regulating delay-locked loop circuit.
Background technology
As shown in Figure 1, delay lock loop of the prior art (DLL) circuit comprises charge pump (CP) 2 that the phase relation that is used for comparison input clock signal Fref and feedback signal Fbck controls with the phase comparator (PD) 1 that generates anticipating signal up (the leading input clock signal of feedback signal) and delay signal dn (feedback signal lags input clock signal), by said anticipating signal up and delay signal dn, be connected to the output of charge pump 2 and the filter capacitor cap of d. c. voltage signal be provided and be used for this response d. c. voltage signal said input clock signal Fref is postponed to generate the voltage-controlled delay chain (VCDL) 3 of said feedback signal Fbck.
As shown in Figure 2, comprise the delay cell of a plurality of cascades in the voltage-controlled delay chain (VCDL) 3.During delay lock loop (DLL) circuit working; Phase comparator (PD) 1 is through the input clock signal Fref of relatively its input and the phase relation of feedback signal Fbck; And produce anticipating signal up and delay signal dn controls discharging and recharging of charge pump (CP) 2; Thereby change voltage Vctrl, finally change the time of delay of voltage-controlled delay chain (VCDL) 3, realize the purpose of the phase information of adjustment feedback signal Fbck.When delay lock loop (DLL) when circuit is stable, the phase difference of input clock signal Fref and feedback signal Fbck can be regarded as " 0 ".Generally speaking, need feedback signal Fbck to fall behind the whole one-period of input clock signal Fref (2pi phase place), just Td time of delay of voltage-controlled delay chain (VCDL) 3 equals the clock cycle Tref of an input clock signal Fref.
In delay lock loop (DLL) circuit, often run into following two problems:
If 1 delay lock loop (DLL) is when circuit is initialized, voltage Vctrl is high, can make that the time of delay of voltage-controlled delay chain is too small, may cause whole delay lock loop (DLL) circuit not lock;
If 2 delay lock loops (DLL) are when circuit is initialized; Voltage Vctrl is low excessively, can make that the time of delay of voltage-controlled delay chain is excessive, because the phase comparator of delay lock loop (DLL) circuit just compares phase relation; May make Td=N*Tref time of delay of voltage-controlled delay chain; Rather than the Td=Tref that requires, this situation can occur and be because during Td=N*Tref, also can make delay lock loop (DLL) circuit stable the time of delay of voltage-controlled delay chain.
The delay lock loop of prior art (DLL) circuit adopts the upper system of design separately to solve above-mentioned two problems usually; To guarantee that delay lock loop (DLL) circuit can operate as normal; When delay lock loop (DLL) when circuit working is made mistakes, need upper system to provide a reset signal delay lock loop (DLL) circuit is resetted, delay lock loop (DLL) circuit is operate as normal once more; This design to upper system has proposed requirement, and design difficulty increases.
The utility model content
The utility model provides a kind of delay-locked loop circuit to the problems referred to above that exist in the prior art; Can't adjust automatically when solving delay-locked loop circuit miswork of the prior art, can only rely on upper system to provide the problem that a reset signal just can make the circuit operate as normal.
In order to address the above problem; The utility model provides a kind of self-regulating delay-locked loop circuit; Comprise that the phase relation that is used for comparison input clock signal and feedback signal is to generate the phase comparator of anticipating signal and delay signal; Charge pump by said anticipating signal and delay signal control; The filter capacitor that is connected to the electric charge delivery side of pump and is used to provide d. c. voltage signal be used to respond this d. c. voltage signal said input clock signal is postponed to generate the voltage-controlled delay chain of said feedback signal; Said delay-locked loop circuit also comprises testing circuit; Voltage-controlled current source and switch; Wherein
Said testing circuit is configured to judge the magnitude relationship between clock cycle of time of delay and said input clock signal of said voltage-controlled delay chain, and output is used to control the control signal of said voltage-controlled current source and switch;
Said voltage-controlled current source is configured to receive said control signal, and according to the size of its output current of said control signal adjustment with lifting or reduce said d. c. voltage signal;
Said switch is positioned on the outlet line of said charge pump, and it is configured to receive said control signal, and the closed or disconnection according to said control signal.
As preferably; Said testing circuit concrete configuration for when said time of delay during more than or equal to 8/7 times of said clock cycle said control signal control said voltage-controlled current source and increase its output current and control said switch disconnection; Said control signal is controlled said voltage-controlled current source and is reduced its output current and control said switch and break off when be less than or equal to 6/7 times of said clock cycle said time of delay, when said time of delay greater than 6/7 times of the said clock cycle and during less than 8/7 times of said clock cycle during said clock cycle said control signal control said switch closure.
Preferred as further; Said voltage-controlled delay chain comprises the delay cell of 16 cascades; Said testing circuit comprises 5 d type flip flops; The Qn output of first d type flip flop connects the D input of its D input and second d type flip flop; The Q output of second d type flip flop connects the D input and the Rn reset terminal of the 3rd d type flip flop; The Q output of the 3rd d type flip flop connects the D input and the Rn reset terminal of the 4th d type flip flop; The Q output of the 4th d type flip flop connects the D input and the Rn reset terminal of the 5th d type flip flop; The output of the output of the output of the input of first delay cell, the 3rd delay cell, the output of the 7th delay cell, the 12 delay cell and the 16 delay cell is connected the ck input end of clock of said 5 d type flip flops respectively in the said voltage-controlled delay chain, and said testing circuit is exported the signal of Q output of said the 4th d type flip flop and the 5th d type flip flop with as said control signal, and the signal of the output of the 14 delay cell is as said feedback signal in the said voltage-controlled delay chain.
Compared with prior art; The utlity model has following beneficial effect: the delay-locked loop circuit of the utility model is through increasing said testing circuit; Can detect the operating state of said voltage-controlled delay chain automatically; When the time of delay of said voltage-controlled delay chain, Td was away from the clock cycle Tref of said input clock signal, testing circuit detected automatically and controls said voltage-controlled current source and switch is regulated and control delay-locked loop circuit, make said voltage-controlled delay chain time of delay Td to the clock cycle of said input clock signal Tref near; Avoid the employing upper system to give the reset signal trouble caused, reduced design difficulty; In addition, even said input clock signal changes, said testing circuit also can detect and make system restoration stable automatically.
Description of drawings
Fig. 1 is the structural representation of delay-locked loop circuit in the prior art.
Fig. 2 is the structural representation of voltage-controlled delay chain in the delay-locked loop circuit shown in Figure 1.
Fig. 3 is the structural representation of the delay-locked loop circuit of the utility model.
Fig. 4 is the structural representation of testing circuit in the delay-locked loop circuit shown in Figure 3.
Fig. 5 is the signal waveforms when Td testing circuit shown in Figure 4 during much larger than Tref.
Fig. 6 is the signal waveforms when Td testing circuit shown in Figure 4 during much smaller than Tref.
Fig. 7 is the signal waveforms of testing circuit shown in Figure 4 when Td approximates Tref.
Embodiment
Be elaborated below in conjunction with the specific embodiment of accompanying drawing to the utility model.
As shown in Figure 3; The self-regulating delay-locked loop circuit of the utility model removes and comprises that the phase relation that is used for comparison input clock signal Fref and feedback signal Fbck is to generate the phase comparator (PD) 1 of anticipating signal up and delay signal dn; Charge pump (CP) 2 by said anticipating signal up and delay signal dn control; The filter capacitor cap that is connected to the output of charge pump 2 and is used to provide said d. c. voltage signal be used to respond this d. c. voltage signal said input clock signal Fref is postponed generate outside the voltage-controlled delay chain (VCDL) 3 of said feedback signal Fbck; Also comprise testing circuit 4; Voltage-controlled current source 5 and switch 6; Wherein
Said testing circuit 4 is configured to judge the magnitude relationship between the clock cycle Tref of time of delay and said input clock signal Fref of said voltage-controlled delay chain (VCDL) 3, and output is used to control the control signal of said voltage-controlled current source 5 and switch 6;
Said voltage-controlled current source 5 is configured to receive said control signal, and according to the size of its output current of said control signal adjustment with lifting or reduce said d. c. voltage signal;
Said switch 6 is positioned on the outlet line of said charge pump (CP) 2, and it is configured to receive said control signal, and the closed or disconnection according to said control signal.
In the present embodiment; As embodiment preferred; Said testing circuit 4 concrete configurations for when said time of delay during more than or equal to 8/7 times of said clock cycle Tref said control signal control said voltage-controlled current source 5 and increase its output currents and control said switch 6 disconnections; Said control signal is controlled said voltage-controlled current source 5 and is reduced its output current and control said switch 6 and break off when be less than or equal to 6/7 times of said clock cycle Tref said time of delay, when said time of delay greater than 6/7 times of said clock cycle Tref and during less than 8/7 times of said clock cycle Tref during said clock cycle Tref said control signal control said switch 6 closures.
Like Fig. 3 and shown in Figure 4; Said voltage-controlled delay chain (VCDL) 3 comprises the delay cell of 16 cascades; Said testing circuit 4 comprises 5 d type flip flops; The Qn output of first d type flip flop 401 connects the D input of its D input and second d type flip flop 402; The Q output of second d type flip flop 402 connects the D input and the Rn reset terminal of the 3rd d type flip flop 403; The Q output of the 3rd d type flip flop 403 connects the D input and the Rn reset terminal of the 4th d type flip flop 404; The Q output of the 4th d type flip flop 404 connects the D input and the Rn reset terminal of the 5th d type flip flop 405; The output of the output of the output of the input of first delay cell, the 3rd delay cell, the output of the 7th delay cell, the 12 delay cell and the 16 delay cell is connected the ck input end of clock of said 5 d type flip flops respectively among said voltage-controlled delay chain (VCDL) 3; For said 5 d type flip flops provide clock input signal clk_0, clk_3, clk_7, clk_12 and clk_16, the signal samp16 of the signal samp12 of the Q output of said the 4th d type flip flop 404 of said testing circuit 4 outputs and the Q output of the 5th d type flip flop 405 is with as said control signal, and the signal of the output of the 14 delay cell is as said feedback signal Fbck among said voltage-controlled delay chain (VCDL) 3.Because the Q output of second d type flip flop 402 connects the Rn reset terminal of the 3rd d type flip flop 403; The Q output of the 3rd d type flip flop 403 connects the Rn reset terminal of the 4th d type flip flop 404; The Q output of the 4th d type flip flop 404 connects the Rn reset terminal of the 5th d type flip flop 405; Therefore, only behind the Q of second d type flip flop 402 output output high level signal, the 3rd d type flip flop 403 just begins the signal samp3 that imports its D input is sampled; Only behind the Q output output high level signal of the 3rd d type flip flop 403, the 4th d type flip flop 404 just begins the signal samp7 that imports its D input is sampled; Only behind the Q output output high level signal of the 4th d type flip flop 404, the 5th d type flip flop 405 just begins the signal samp12 that imports its D input is sampled.
As shown in Figure 5; As Td >=8/7Tref; Be that Td is during much larger than Tref; After the 5th d type flip flop 405 begins the signal samp12 that imports its D input sampled; After promptly the rising edge of the clock signal clk_16 of the ck input end of clock of the Q output of the 4th d type flip flop 404 output high level signal and the 5th d type flip flop 405 arrives; The signal samp16 of the Q output of the signal samp12 of the Q output of the 4th d type flip flop 404 and the 5th d type flip flop 405 is 0; Therefore Td is much larger than Tref when the signal samp16 of the Q output of the signal samp12 of the Q output of the 4th d type flip flop 404 and the 5th d type flip flop 405 is 0 in definition, and the signal samp16 of Q output of signal samp12 and the 5th d type flip flop 405 of Q output of the 4th d type flip flop 404 controlled said voltage-controlled current source 5 and increased its output currents and control said switch 6 and break off this moment, voltage Vctrl is raise and the outlet line disconnection of charge pump (CP) 2.
As shown in Figure 6; As Td≤6/7Tref; Be that Td is during much smaller than Tref; After the 5th d type flip flop 405 begins the signal samp12 that imports its D input sampled; After promptly the rising edge of the clock signal clk_16 of the ck input end of clock of the Q output of the 4th d type flip flop 404 output high level signal and the 5th d type flip flop 405 arrives; The signal samp16 of the Q output of the signal samp12 of the Q output of the 4th d type flip flop 404 and the 5th d type flip flop 405 is 1; Therefore Td is much smaller than Tref when the signal samp16 of the Q output of the signal samp12 of the Q output of the 4th d type flip flop 404 and the 5th d type flip flop 405 is 1 in definition, and the signal samp16 of Q output of signal samp12 and the 5th d type flip flop 405 of Q output of the 4th d type flip flop 404 controlled said voltage-controlled current source 5 and reduced its output current and control said switch 6 and break off this moment, voltage Vctrl is reduced and the outlet line disconnection of charge pump (CP) 2.
As shown in Figure 7; As 6/7Tref＜Td＜8/7Tref; Be that Td is when approximating Tref; After the 5th d type flip flop 405 begins the signal samp12 that imports its D input sampled; After promptly the rising edge of the clock signal clk_16 of the ck input end of clock of the Q output of the 4th d type flip flop 404 output high level signal and the 5th d type flip flop 405 arrived, the signal samp12 of the Q output of the 4th d type flip flop 404 was that the signal samp16 of the Q output of 1, the five d type flip flop 405 is 0; Therefore definition when the signal samp12 of the Q output of the 4th d type flip flop 404 be that the signal samp16 of the Q output of 1 and the 5th d type flip flop 405 is when being 0; Td approximates Tref, and the said voltage-controlled current source 5 of signal controlling of Q output of signal samp12 and the 5th d type flip flop 405 of Q output of the 4th d type flip flop 404 kept its output currents and controlled said switch 6 closures this moment, voltage Vctrl is remained unchanged and the outlet line of charge pump (CP) 2 closed.
The delay-locked loop circuit of the utility model is through increasing said testing circuit 4; Can detect the operating state of said voltage-controlled delay chain (VCDL) 3 automatically; When the time of delay of said voltage-controlled delay chain (VCDL) 3, Td was away from the clock cycle Tref of said input clock signal Fref; Testing circuit 4 detects and control said voltage-controlled current source 5 automatically to be regulated and control with 6 pairs of delay-locked loop circuits of switch, make said voltage-controlled delay chain (VCDL) 3 time of delay Td to the clock cycle of said input clock signal Fref Tref near; In addition, even said input clock signal Fref changes, said testing circuit 4 also can detect and make system restoration stable automatically, has avoided the employing upper system to give the reset signal trouble caused.
Above embodiment is merely the exemplary embodiment of the utility model, is not used in restriction the utility model, and the protection range of the utility model is defined by the claims.Those skilled in the art can make various modifications or be equal to replacement the utility model in the essence and protection range of the utility model, this modification or be equal to replacement and also should be regarded as dropping in the protection range of the utility model.
Claims (3)
1. self-regulating delay-locked loop circuit; Comprise that the phase relation that is used for comparison input clock signal and feedback signal is to generate the phase comparator of anticipating signal and delay signal; Charge pump by said anticipating signal and delay signal control; The filter capacitor that is connected to the electric charge delivery side of pump and is used to provide d. c. voltage signal be used to respond this d. c. voltage signal said input clock signal is postponed to generate the voltage-controlled delay chain of said feedback signal; It is characterized in that; Said delay-locked loop circuit also comprises testing circuit; Voltage-controlled current source and switch; Wherein
Said testing circuit is configured to judge the magnitude relationship between clock cycle of time of delay and said input clock signal of said voltage-controlled delay chain, and output is used to control the control signal of said voltage-controlled current source and switch;
Said voltage-controlled current source is configured to receive said control signal, and according to the size of its output current of said control signal adjustment with lifting or reduce said d. c. voltage signal;
Said switch is positioned on the outlet line of said charge pump, and it is configured to receive said control signal, and the closed or disconnection according to said control signal.
2. self-regulating delay-locked loop circuit according to claim 1; It is characterized in that; Said testing circuit concrete configuration for when said time of delay during more than or equal to 8/7 times of said clock cycle said control signal control said voltage-controlled current source and increase its output current and control said switch disconnection; Said control signal is controlled said voltage-controlled current source and is reduced its output current and control said switch and break off when be less than or equal to 6/7 times of said clock cycle said time of delay, when said time of delay greater than 6/7 times of the said clock cycle and during less than 8/7 times of said clock cycle during said clock cycle said control signal control said switch closure.
3. self-regulating delay-locked loop circuit according to claim 1 and 2; It is characterized in that; Said voltage-controlled delay chain comprises the delay cell of 16 cascades; Said testing circuit comprises 5 d type flip flops; The Qn output of first d type flip flop connects the D input of its D input and second d type flip flop; The Q output of second d type flip flop connects the D input and the Rn reset terminal of the 3rd d type flip flop; The Q output of the 3rd d type flip flop connects the D input and the Rn reset terminal of the 4th d type flip flop, and the Q output of the 4th d type flip flop connects the D input and the Rn reset terminal of the 5th d type flip flop, and the output of the output of the output of the input of first delay cell, the 3rd delay cell, the output of the 7th delay cell, the 12 delay cell and the 16 delay cell is connected the ck input end of clock of said 5 d type flip flops respectively in the said voltage-controlled delay chain; Said testing circuit is exported the signal of Q output of said the 4th d type flip flop and the 5th d type flip flop with as said control signal, and the signal of the output of the 14 delay cell is as said feedback signal in the said voltage-controlled delay chain.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011205722129U CN202424687U (en) | 2011-12-31 | 2011-12-31 | Self-adjustable delay locking loop circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011205722129U CN202424687U (en) | 2011-12-31 | 2011-12-31 | Self-adjustable delay locking loop circuit |
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| Publication Number | Publication Date |
|---|---|
| CN202424687U true CN202424687U (en) | 2012-09-05 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011205722129U Withdrawn - After Issue CN202424687U (en) | 2011-12-31 | 2011-12-31 | Self-adjustable delay locking loop circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102571081A (en) * | 2011-12-31 | 2012-07-11 | 上海贝岭股份有限公司 | Delay lock loop circuit |
| CN108566195A (en) * | 2018-03-20 | 2018-09-21 | 上海集成电路研发中心有限公司 | A kind of delay phase-locked loop with broadband input range |
| CN112073059A (en) * | 2020-08-27 | 2020-12-11 | 灿芯半导体(上海)有限公司 | DLL circuit |
-
2011
- 2011-12-31 CN CN2011205722129U patent/CN202424687U/en not_active Withdrawn - After Issue
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102571081A (en) * | 2011-12-31 | 2012-07-11 | 上海贝岭股份有限公司 | Delay lock loop circuit |
| CN102571081B (en) * | 2011-12-31 | 2014-08-13 | 上海贝岭股份有限公司 | Delay lock loop circuit |
| CN108566195A (en) * | 2018-03-20 | 2018-09-21 | 上海集成电路研发中心有限公司 | A kind of delay phase-locked loop with broadband input range |
| CN112073059A (en) * | 2020-08-27 | 2020-12-11 | 灿芯半导体(上海)有限公司 | DLL circuit |
| CN112073059B (en) * | 2020-08-27 | 2023-11-21 | 灿芯半导体(上海)股份有限公司 | DLL circuit |
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| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20120905 Effective date of abandoning: 20140813 |
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| RGAV | Abandon patent right to avoid regrant |